1 /* 2 * Allwinner A10 timer device emulation 3 * 4 * Copyright (C) 2013 Li Guang 5 * Written by Li Guang <lig.fnst@cn.fujitsu.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #include "qemu/osdep.h" 19 #include "hw/irq.h" 20 #include "hw/sysbus.h" 21 #include "sysemu/sysemu.h" 22 #include "hw/timer/allwinner-a10-pit.h" 23 #include "qemu/log.h" 24 #include "qemu/module.h" 25 26 static void a10_pit_update_irq(AwA10PITState *s) 27 { 28 int i; 29 30 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 31 qemu_set_irq(s->irq[i], !!(s->irq_status & s->irq_enable & (1 << i))); 32 } 33 } 34 35 static uint64_t a10_pit_read(void *opaque, hwaddr offset, unsigned size) 36 { 37 AwA10PITState *s = AW_A10_PIT(opaque); 38 uint8_t index; 39 40 switch (offset) { 41 case AW_A10_PIT_TIMER_IRQ_EN: 42 return s->irq_enable; 43 case AW_A10_PIT_TIMER_IRQ_ST: 44 return s->irq_status; 45 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 46 index = offset & 0xf0; 47 index >>= 4; 48 index -= 1; 49 switch (offset & 0x0f) { 50 case AW_A10_PIT_TIMER_CONTROL: 51 return s->control[index]; 52 case AW_A10_PIT_TIMER_INTERVAL: 53 return s->interval[index]; 54 case AW_A10_PIT_TIMER_COUNT: 55 s->count[index] = ptimer_get_count(s->timer[index]); 56 return s->count[index]; 57 default: 58 qemu_log_mask(LOG_GUEST_ERROR, 59 "%s: Bad offset 0x%x\n", __func__, (int)offset); 60 break; 61 } 62 case AW_A10_PIT_WDOG_CONTROL: 63 break; 64 case AW_A10_PIT_WDOG_MODE: 65 break; 66 case AW_A10_PIT_COUNT_LO: 67 return s->count_lo; 68 case AW_A10_PIT_COUNT_HI: 69 return s->count_hi; 70 case AW_A10_PIT_COUNT_CTL: 71 return s->count_ctl; 72 default: 73 qemu_log_mask(LOG_GUEST_ERROR, 74 "%s: Bad offset 0x%x\n", __func__, (int)offset); 75 break; 76 } 77 78 return 0; 79 } 80 81 static void a10_pit_set_freq(AwA10PITState *s, int index) 82 { 83 uint32_t prescaler, source, source_freq; 84 85 prescaler = 1 << extract32(s->control[index], 4, 3); 86 source = extract32(s->control[index], 2, 2); 87 source_freq = s->clk_freq[source]; 88 89 if (source_freq) { 90 ptimer_set_freq(s->timer[index], source_freq / prescaler); 91 } else { 92 qemu_log_mask(LOG_GUEST_ERROR, "%s: Invalid clock source %u\n", 93 __func__, source); 94 } 95 } 96 97 static void a10_pit_write(void *opaque, hwaddr offset, uint64_t value, 98 unsigned size) 99 { 100 AwA10PITState *s = AW_A10_PIT(opaque); 101 uint8_t index; 102 103 switch (offset) { 104 case AW_A10_PIT_TIMER_IRQ_EN: 105 s->irq_enable = value; 106 a10_pit_update_irq(s); 107 break; 108 case AW_A10_PIT_TIMER_IRQ_ST: 109 s->irq_status &= ~value; 110 a10_pit_update_irq(s); 111 break; 112 case AW_A10_PIT_TIMER_BASE ... AW_A10_PIT_TIMER_BASE_END: 113 index = offset & 0xf0; 114 index >>= 4; 115 index -= 1; 116 switch (offset & 0x0f) { 117 case AW_A10_PIT_TIMER_CONTROL: 118 s->control[index] = value; 119 a10_pit_set_freq(s, index); 120 if (s->control[index] & AW_A10_PIT_TIMER_RELOAD) { 121 ptimer_set_count(s->timer[index], s->interval[index]); 122 } 123 if (s->control[index] & AW_A10_PIT_TIMER_EN) { 124 int oneshot = 0; 125 if (s->control[index] & AW_A10_PIT_TIMER_MODE) { 126 oneshot = 1; 127 } 128 ptimer_run(s->timer[index], oneshot); 129 } else { 130 ptimer_stop(s->timer[index]); 131 } 132 break; 133 case AW_A10_PIT_TIMER_INTERVAL: 134 s->interval[index] = value; 135 ptimer_set_limit(s->timer[index], s->interval[index], 1); 136 break; 137 case AW_A10_PIT_TIMER_COUNT: 138 s->count[index] = value; 139 break; 140 default: 141 qemu_log_mask(LOG_GUEST_ERROR, 142 "%s: Bad offset 0x%x\n", __func__, (int)offset); 143 } 144 break; 145 case AW_A10_PIT_WDOG_CONTROL: 146 s->watch_dog_control = value; 147 break; 148 case AW_A10_PIT_WDOG_MODE: 149 s->watch_dog_mode = value; 150 break; 151 case AW_A10_PIT_COUNT_LO: 152 s->count_lo = value; 153 break; 154 case AW_A10_PIT_COUNT_HI: 155 s->count_hi = value; 156 break; 157 case AW_A10_PIT_COUNT_CTL: 158 s->count_ctl = value; 159 if (s->count_ctl & AW_A10_PIT_COUNT_RL_EN) { 160 uint64_t tmp_count = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 161 162 s->count_lo = tmp_count; 163 s->count_hi = tmp_count >> 32; 164 s->count_ctl &= ~AW_A10_PIT_COUNT_RL_EN; 165 } 166 if (s->count_ctl & AW_A10_PIT_COUNT_CLR_EN) { 167 s->count_lo = 0; 168 s->count_hi = 0; 169 s->count_ctl &= ~AW_A10_PIT_COUNT_CLR_EN; 170 } 171 break; 172 default: 173 qemu_log_mask(LOG_GUEST_ERROR, 174 "%s: Bad offset 0x%x\n", __func__, (int)offset); 175 break; 176 } 177 } 178 179 static const MemoryRegionOps a10_pit_ops = { 180 .read = a10_pit_read, 181 .write = a10_pit_write, 182 .endianness = DEVICE_NATIVE_ENDIAN, 183 }; 184 185 static Property a10_pit_properties[] = { 186 DEFINE_PROP_UINT32("clk0-freq", AwA10PITState, clk_freq[0], 0), 187 DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), 188 DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), 189 DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), 190 DEFINE_PROP_END_OF_LIST(), 191 }; 192 193 static const VMStateDescription vmstate_a10_pit = { 194 .name = "a10.pit", 195 .version_id = 1, 196 .minimum_version_id = 1, 197 .fields = (VMStateField[]) { 198 VMSTATE_UINT32(irq_enable, AwA10PITState), 199 VMSTATE_UINT32(irq_status, AwA10PITState), 200 VMSTATE_UINT32_ARRAY(control, AwA10PITState, AW_A10_PIT_TIMER_NR), 201 VMSTATE_UINT32_ARRAY(interval, AwA10PITState, AW_A10_PIT_TIMER_NR), 202 VMSTATE_UINT32_ARRAY(count, AwA10PITState, AW_A10_PIT_TIMER_NR), 203 VMSTATE_UINT32(watch_dog_mode, AwA10PITState), 204 VMSTATE_UINT32(watch_dog_control, AwA10PITState), 205 VMSTATE_UINT32(count_lo, AwA10PITState), 206 VMSTATE_UINT32(count_hi, AwA10PITState), 207 VMSTATE_UINT32(count_ctl, AwA10PITState), 208 VMSTATE_PTIMER_ARRAY(timer, AwA10PITState, AW_A10_PIT_TIMER_NR), 209 VMSTATE_END_OF_LIST() 210 } 211 }; 212 213 static void a10_pit_reset(DeviceState *dev) 214 { 215 AwA10PITState *s = AW_A10_PIT(dev); 216 uint8_t i; 217 218 s->irq_enable = 0; 219 s->irq_status = 0; 220 a10_pit_update_irq(s); 221 222 for (i = 0; i < 6; i++) { 223 s->control[i] = AW_A10_PIT_DEFAULT_CLOCK; 224 s->interval[i] = 0; 225 s->count[i] = 0; 226 ptimer_stop(s->timer[i]); 227 a10_pit_set_freq(s, i); 228 } 229 s->watch_dog_mode = 0; 230 s->watch_dog_control = 0; 231 s->count_lo = 0; 232 s->count_hi = 0; 233 s->count_ctl = 0; 234 } 235 236 static void a10_pit_timer_cb(void *opaque) 237 { 238 AwA10TimerContext *tc = opaque; 239 AwA10PITState *s = tc->container; 240 uint8_t i = tc->index; 241 242 if (s->control[i] & AW_A10_PIT_TIMER_EN) { 243 s->irq_status |= 1 << i; 244 if (s->control[i] & AW_A10_PIT_TIMER_MODE) { 245 ptimer_stop(s->timer[i]); 246 s->control[i] &= ~AW_A10_PIT_TIMER_EN; 247 } 248 a10_pit_update_irq(s); 249 } 250 } 251 252 static void a10_pit_init(Object *obj) 253 { 254 AwA10PITState *s = AW_A10_PIT(obj); 255 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 256 QEMUBH * bh[AW_A10_PIT_TIMER_NR]; 257 uint8_t i; 258 259 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 260 sysbus_init_irq(sbd, &s->irq[i]); 261 } 262 memory_region_init_io(&s->iomem, OBJECT(s), &a10_pit_ops, s, 263 TYPE_AW_A10_PIT, 0x400); 264 sysbus_init_mmio(sbd, &s->iomem); 265 266 for (i = 0; i < AW_A10_PIT_TIMER_NR; i++) { 267 AwA10TimerContext *tc = &s->timer_context[i]; 268 269 tc->container = s; 270 tc->index = i; 271 bh[i] = qemu_bh_new(a10_pit_timer_cb, tc); 272 s->timer[i] = ptimer_init(bh[i], PTIMER_POLICY_DEFAULT); 273 } 274 } 275 276 static void a10_pit_class_init(ObjectClass *klass, void *data) 277 { 278 DeviceClass *dc = DEVICE_CLASS(klass); 279 280 dc->reset = a10_pit_reset; 281 dc->props = a10_pit_properties; 282 dc->desc = "allwinner a10 timer"; 283 dc->vmsd = &vmstate_a10_pit; 284 } 285 286 static const TypeInfo a10_pit_info = { 287 .name = TYPE_AW_A10_PIT, 288 .parent = TYPE_SYS_BUS_DEVICE, 289 .instance_size = sizeof(AwA10PITState), 290 .instance_init = a10_pit_init, 291 .class_init = a10_pit_class_init, 292 }; 293 294 static void a10_register_types(void) 295 { 296 type_register_static(&a10_pit_info); 297 } 298 299 type_init(a10_register_types); 300