1 /* 2 * QEMU GRLIB GPTimer Emulator 3 * 4 * Copyright (c) 2010-2011 AdaCore 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/sysbus.h" 27 #include "qemu/timer.h" 28 #include "hw/ptimer.h" 29 #include "qemu/timer.h" 30 #include "qemu/main-loop.h" 31 32 #include "trace.h" 33 34 #define UNIT_REG_SIZE 16 /* Size of memory mapped regs for the unit */ 35 #define GPTIMER_REG_SIZE 16 /* Size of memory mapped regs for a GPTimer */ 36 37 #define GPTIMER_MAX_TIMERS 8 38 39 /* GPTimer Config register fields */ 40 #define GPTIMER_ENABLE (1 << 0) 41 #define GPTIMER_RESTART (1 << 1) 42 #define GPTIMER_LOAD (1 << 2) 43 #define GPTIMER_INT_ENABLE (1 << 3) 44 #define GPTIMER_INT_PENDING (1 << 4) 45 #define GPTIMER_CHAIN (1 << 5) /* Not supported */ 46 #define GPTIMER_DEBUG_HALT (1 << 6) /* Not supported */ 47 48 /* Memory mapped register offsets */ 49 #define SCALER_OFFSET 0x00 50 #define SCALER_RELOAD_OFFSET 0x04 51 #define CONFIG_OFFSET 0x08 52 #define COUNTER_OFFSET 0x00 53 #define COUNTER_RELOAD_OFFSET 0x04 54 #define TIMER_BASE 0x10 55 56 #define TYPE_GRLIB_GPTIMER "grlib,gptimer" 57 #define GRLIB_GPTIMER(obj) \ 58 OBJECT_CHECK(GPTimerUnit, (obj), TYPE_GRLIB_GPTIMER) 59 60 typedef struct GPTimer GPTimer; 61 typedef struct GPTimerUnit GPTimerUnit; 62 63 struct GPTimer { 64 QEMUBH *bh; 65 struct ptimer_state *ptimer; 66 67 qemu_irq irq; 68 int id; 69 GPTimerUnit *unit; 70 71 /* registers */ 72 uint32_t counter; 73 uint32_t reload; 74 uint32_t config; 75 }; 76 77 struct GPTimerUnit { 78 SysBusDevice parent_obj; 79 80 MemoryRegion iomem; 81 82 uint32_t nr_timers; /* Number of timers available */ 83 uint32_t freq_hz; /* System frequency */ 84 uint32_t irq_line; /* Base irq line */ 85 86 GPTimer *timers; 87 88 /* registers */ 89 uint32_t scaler; 90 uint32_t reload; 91 uint32_t config; 92 }; 93 94 static void grlib_gptimer_enable(GPTimer *timer) 95 { 96 assert(timer != NULL); 97 98 99 ptimer_stop(timer->ptimer); 100 101 if (!(timer->config & GPTIMER_ENABLE)) { 102 /* Timer disabled */ 103 trace_grlib_gptimer_disabled(timer->id, timer->config); 104 return; 105 } 106 107 /* ptimer is triggered when the counter reach 0 but GPTimer is triggered at 108 underflow. Set count + 1 to simulate the GPTimer behavior. */ 109 110 trace_grlib_gptimer_enable(timer->id, timer->counter); 111 112 ptimer_set_count(timer->ptimer, (uint64_t)timer->counter + 1); 113 ptimer_run(timer->ptimer, 1); 114 } 115 116 static void grlib_gptimer_restart(GPTimer *timer) 117 { 118 assert(timer != NULL); 119 120 trace_grlib_gptimer_restart(timer->id, timer->reload); 121 122 timer->counter = timer->reload; 123 grlib_gptimer_enable(timer); 124 } 125 126 static void grlib_gptimer_set_scaler(GPTimerUnit *unit, uint32_t scaler) 127 { 128 int i = 0; 129 uint32_t value = 0; 130 131 assert(unit != NULL); 132 133 if (scaler > 0) { 134 value = unit->freq_hz / (scaler + 1); 135 } else { 136 value = unit->freq_hz; 137 } 138 139 trace_grlib_gptimer_set_scaler(scaler, value); 140 141 for (i = 0; i < unit->nr_timers; i++) { 142 ptimer_set_freq(unit->timers[i].ptimer, value); 143 } 144 } 145 146 static void grlib_gptimer_hit(void *opaque) 147 { 148 GPTimer *timer = opaque; 149 assert(timer != NULL); 150 151 trace_grlib_gptimer_hit(timer->id); 152 153 /* Timer expired */ 154 155 if (timer->config & GPTIMER_INT_ENABLE) { 156 /* Set the pending bit (only unset by write in the config register) */ 157 timer->config |= GPTIMER_INT_PENDING; 158 qemu_irq_pulse(timer->irq); 159 } 160 161 if (timer->config & GPTIMER_RESTART) { 162 grlib_gptimer_restart(timer); 163 } 164 } 165 166 static uint64_t grlib_gptimer_read(void *opaque, hwaddr addr, 167 unsigned size) 168 { 169 GPTimerUnit *unit = opaque; 170 hwaddr timer_addr; 171 int id; 172 uint32_t value = 0; 173 174 addr &= 0xff; 175 176 /* Unit registers */ 177 switch (addr) { 178 case SCALER_OFFSET: 179 trace_grlib_gptimer_readl(-1, addr, unit->scaler); 180 return unit->scaler; 181 182 case SCALER_RELOAD_OFFSET: 183 trace_grlib_gptimer_readl(-1, addr, unit->reload); 184 return unit->reload; 185 186 case CONFIG_OFFSET: 187 trace_grlib_gptimer_readl(-1, addr, unit->config); 188 return unit->config; 189 190 default: 191 break; 192 } 193 194 timer_addr = (addr % TIMER_BASE); 195 id = (addr - TIMER_BASE) / TIMER_BASE; 196 197 if (id >= 0 && id < unit->nr_timers) { 198 199 /* GPTimer registers */ 200 switch (timer_addr) { 201 case COUNTER_OFFSET: 202 value = ptimer_get_count(unit->timers[id].ptimer); 203 trace_grlib_gptimer_readl(id, addr, value); 204 return value; 205 206 case COUNTER_RELOAD_OFFSET: 207 value = unit->timers[id].reload; 208 trace_grlib_gptimer_readl(id, addr, value); 209 return value; 210 211 case CONFIG_OFFSET: 212 trace_grlib_gptimer_readl(id, addr, unit->timers[id].config); 213 return unit->timers[id].config; 214 215 default: 216 break; 217 } 218 219 } 220 221 trace_grlib_gptimer_readl(-1, addr, 0); 222 return 0; 223 } 224 225 static void grlib_gptimer_write(void *opaque, hwaddr addr, 226 uint64_t value, unsigned size) 227 { 228 GPTimerUnit *unit = opaque; 229 hwaddr timer_addr; 230 int id; 231 232 addr &= 0xff; 233 234 /* Unit registers */ 235 switch (addr) { 236 case SCALER_OFFSET: 237 value &= 0xFFFF; /* clean up the value */ 238 unit->scaler = value; 239 trace_grlib_gptimer_writel(-1, addr, unit->scaler); 240 return; 241 242 case SCALER_RELOAD_OFFSET: 243 value &= 0xFFFF; /* clean up the value */ 244 unit->reload = value; 245 trace_grlib_gptimer_writel(-1, addr, unit->reload); 246 grlib_gptimer_set_scaler(unit, value); 247 return; 248 249 case CONFIG_OFFSET: 250 /* Read Only (disable timer freeze not supported) */ 251 trace_grlib_gptimer_writel(-1, addr, 0); 252 return; 253 254 default: 255 break; 256 } 257 258 timer_addr = (addr % TIMER_BASE); 259 id = (addr - TIMER_BASE) / TIMER_BASE; 260 261 if (id >= 0 && id < unit->nr_timers) { 262 263 /* GPTimer registers */ 264 switch (timer_addr) { 265 case COUNTER_OFFSET: 266 trace_grlib_gptimer_writel(id, addr, value); 267 unit->timers[id].counter = value; 268 grlib_gptimer_enable(&unit->timers[id]); 269 return; 270 271 case COUNTER_RELOAD_OFFSET: 272 trace_grlib_gptimer_writel(id, addr, value); 273 unit->timers[id].reload = value; 274 return; 275 276 case CONFIG_OFFSET: 277 trace_grlib_gptimer_writel(id, addr, value); 278 279 if (value & GPTIMER_INT_PENDING) { 280 /* clear pending bit */ 281 value &= ~GPTIMER_INT_PENDING; 282 } else { 283 /* keep pending bit */ 284 value |= unit->timers[id].config & GPTIMER_INT_PENDING; 285 } 286 287 unit->timers[id].config = value; 288 289 /* gptimer_restart calls gptimer_enable, so if "enable" and "load" 290 bits are present, we just have to call restart. */ 291 292 if (value & GPTIMER_LOAD) { 293 grlib_gptimer_restart(&unit->timers[id]); 294 } else if (value & GPTIMER_ENABLE) { 295 grlib_gptimer_enable(&unit->timers[id]); 296 } 297 298 /* These fields must always be read as 0 */ 299 value &= ~(GPTIMER_LOAD & GPTIMER_DEBUG_HALT); 300 301 unit->timers[id].config = value; 302 return; 303 304 default: 305 break; 306 } 307 308 } 309 310 trace_grlib_gptimer_writel(-1, addr, value); 311 } 312 313 static const MemoryRegionOps grlib_gptimer_ops = { 314 .read = grlib_gptimer_read, 315 .write = grlib_gptimer_write, 316 .endianness = DEVICE_NATIVE_ENDIAN, 317 .valid = { 318 .min_access_size = 4, 319 .max_access_size = 4, 320 }, 321 }; 322 323 static void grlib_gptimer_reset(DeviceState *d) 324 { 325 GPTimerUnit *unit = GRLIB_GPTIMER(d); 326 int i = 0; 327 328 assert(unit != NULL); 329 330 unit->scaler = 0; 331 unit->reload = 0; 332 333 unit->config = unit->nr_timers; 334 unit->config |= unit->irq_line << 3; 335 unit->config |= 1 << 8; /* separate interrupt */ 336 unit->config |= 1 << 9; /* Disable timer freeze */ 337 338 339 for (i = 0; i < unit->nr_timers; i++) { 340 GPTimer *timer = &unit->timers[i]; 341 342 timer->counter = 0; 343 timer->reload = 0; 344 timer->config = 0; 345 ptimer_stop(timer->ptimer); 346 ptimer_set_count(timer->ptimer, 0); 347 ptimer_set_freq(timer->ptimer, unit->freq_hz); 348 } 349 } 350 351 static int grlib_gptimer_init(SysBusDevice *dev) 352 { 353 GPTimerUnit *unit = GRLIB_GPTIMER(dev); 354 unsigned int i; 355 356 assert(unit->nr_timers > 0); 357 assert(unit->nr_timers <= GPTIMER_MAX_TIMERS); 358 359 unit->timers = g_malloc0(sizeof unit->timers[0] * unit->nr_timers); 360 361 for (i = 0; i < unit->nr_timers; i++) { 362 GPTimer *timer = &unit->timers[i]; 363 364 timer->unit = unit; 365 timer->bh = qemu_bh_new(grlib_gptimer_hit, timer); 366 timer->ptimer = ptimer_init(timer->bh); 367 timer->id = i; 368 369 /* One IRQ line for each timer */ 370 sysbus_init_irq(dev, &timer->irq); 371 372 ptimer_set_freq(timer->ptimer, unit->freq_hz); 373 } 374 375 memory_region_init_io(&unit->iomem, OBJECT(unit), &grlib_gptimer_ops, 376 unit, "gptimer", 377 UNIT_REG_SIZE + GPTIMER_REG_SIZE * unit->nr_timers); 378 379 sysbus_init_mmio(dev, &unit->iomem); 380 return 0; 381 } 382 383 static Property grlib_gptimer_properties[] = { 384 DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000), 385 DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8), 386 DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2), 387 DEFINE_PROP_END_OF_LIST(), 388 }; 389 390 static void grlib_gptimer_class_init(ObjectClass *klass, void *data) 391 { 392 DeviceClass *dc = DEVICE_CLASS(klass); 393 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 394 395 k->init = grlib_gptimer_init; 396 dc->reset = grlib_gptimer_reset; 397 dc->props = grlib_gptimer_properties; 398 } 399 400 static const TypeInfo grlib_gptimer_info = { 401 .name = TYPE_GRLIB_GPTIMER, 402 .parent = TYPE_SYS_BUS_DEVICE, 403 .instance_size = sizeof(GPTimerUnit), 404 .class_init = grlib_gptimer_class_init, 405 }; 406 407 static void grlib_gptimer_register_types(void) 408 { 409 type_register_static(&grlib_gptimer_info); 410 } 411 412 type_init(grlib_gptimer_register_types) 413