1 /* 2 * High Precisition Event Timer emulation 3 * 4 * Copyright (c) 2007 Alexander Graf 5 * Copyright (c) 2008 IBM Corporation 6 * 7 * Authors: Beth Kon <bkon@us.ibm.com> 8 * 9 * This library is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU Lesser General Public 11 * License as published by the Free Software Foundation; either 12 * version 2 of the License, or (at your option) any later version. 13 * 14 * This library is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 17 * Lesser General Public License for more details. 18 * 19 * You should have received a copy of the GNU Lesser General Public 20 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 21 * 22 * ***************************************************************** 23 * 24 * This driver attempts to emulate an HPET device in software. 25 */ 26 27 #include "hw/hw.h" 28 #include "hw/i386/pc.h" 29 #include "ui/console.h" 30 #include "qemu/timer.h" 31 #include "hw/timer/hpet.h" 32 #include "hw/sysbus.h" 33 #include "hw/timer/mc146818rtc.h" 34 #include "hw/timer/i8254.h" 35 36 //#define HPET_DEBUG 37 #ifdef HPET_DEBUG 38 #define DPRINTF printf 39 #else 40 #define DPRINTF(...) 41 #endif 42 43 #define HPET_MSI_SUPPORT 0 44 45 #define HPET(obj) OBJECT_CHECK(HPETState, (obj), TYPE_HPET) 46 47 struct HPETState; 48 typedef struct HPETTimer { /* timers */ 49 uint8_t tn; /*timer number*/ 50 QEMUTimer *qemu_timer; 51 struct HPETState *state; 52 /* Memory-mapped, software visible timer registers */ 53 uint64_t config; /* configuration/cap */ 54 uint64_t cmp; /* comparator */ 55 uint64_t fsb; /* FSB route */ 56 /* Hidden register state */ 57 uint64_t period; /* Last value written to comparator */ 58 uint8_t wrap_flag; /* timer pop will indicate wrap for one-shot 32-bit 59 * mode. Next pop will be actual timer expiration. 60 */ 61 } HPETTimer; 62 63 typedef struct HPETState { 64 /*< private >*/ 65 SysBusDevice parent_obj; 66 /*< public >*/ 67 68 MemoryRegion iomem; 69 uint64_t hpet_offset; 70 qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; 71 uint32_t flags; 72 uint8_t rtc_irq_level; 73 qemu_irq pit_enabled; 74 uint8_t num_timers; 75 uint32_t intcap; 76 HPETTimer timer[HPET_MAX_TIMERS]; 77 78 /* Memory-mapped, software visible registers */ 79 uint64_t capability; /* capabilities */ 80 uint64_t config; /* configuration */ 81 uint64_t isr; /* interrupt status reg */ 82 uint64_t hpet_counter; /* main counter */ 83 uint8_t hpet_id; /* instance id */ 84 } HPETState; 85 86 static uint32_t hpet_in_legacy_mode(HPETState *s) 87 { 88 return s->config & HPET_CFG_LEGACY; 89 } 90 91 static uint32_t timer_int_route(struct HPETTimer *timer) 92 { 93 return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT; 94 } 95 96 static uint32_t timer_fsb_route(HPETTimer *t) 97 { 98 return t->config & HPET_TN_FSB_ENABLE; 99 } 100 101 static uint32_t hpet_enabled(HPETState *s) 102 { 103 return s->config & HPET_CFG_ENABLE; 104 } 105 106 static uint32_t timer_is_periodic(HPETTimer *t) 107 { 108 return t->config & HPET_TN_PERIODIC; 109 } 110 111 static uint32_t timer_enabled(HPETTimer *t) 112 { 113 return t->config & HPET_TN_ENABLE; 114 } 115 116 static uint32_t hpet_time_after(uint64_t a, uint64_t b) 117 { 118 return ((int32_t)(b) - (int32_t)(a) < 0); 119 } 120 121 static uint32_t hpet_time_after64(uint64_t a, uint64_t b) 122 { 123 return ((int64_t)(b) - (int64_t)(a) < 0); 124 } 125 126 static uint64_t ticks_to_ns(uint64_t value) 127 { 128 return (muldiv64(value, HPET_CLK_PERIOD, FS_PER_NS)); 129 } 130 131 static uint64_t ns_to_ticks(uint64_t value) 132 { 133 return (muldiv64(value, FS_PER_NS, HPET_CLK_PERIOD)); 134 } 135 136 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old, uint64_t mask) 137 { 138 new &= mask; 139 new |= old & ~mask; 140 return new; 141 } 142 143 static int activating_bit(uint64_t old, uint64_t new, uint64_t mask) 144 { 145 return (!(old & mask) && (new & mask)); 146 } 147 148 static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask) 149 { 150 return ((old & mask) && !(new & mask)); 151 } 152 153 static uint64_t hpet_get_ticks(HPETState *s) 154 { 155 return ns_to_ticks(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hpet_offset); 156 } 157 158 /* 159 * calculate diff between comparator value and current ticks 160 */ 161 static inline uint64_t hpet_calculate_diff(HPETTimer *t, uint64_t current) 162 { 163 164 if (t->config & HPET_TN_32BIT) { 165 uint32_t diff, cmp; 166 167 cmp = (uint32_t)t->cmp; 168 diff = cmp - (uint32_t)current; 169 diff = (int32_t)diff > 0 ? diff : (uint32_t)1; 170 return (uint64_t)diff; 171 } else { 172 uint64_t diff, cmp; 173 174 cmp = t->cmp; 175 diff = cmp - current; 176 diff = (int64_t)diff > 0 ? diff : (uint64_t)1; 177 return diff; 178 } 179 } 180 181 static void update_irq(struct HPETTimer *timer, int set) 182 { 183 uint64_t mask; 184 HPETState *s; 185 int route; 186 187 if (timer->tn <= 1 && hpet_in_legacy_mode(timer->state)) { 188 /* if LegacyReplacementRoute bit is set, HPET specification requires 189 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC, 190 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC. 191 */ 192 route = (timer->tn == 0) ? 0 : RTC_ISA_IRQ; 193 } else { 194 route = timer_int_route(timer); 195 } 196 s = timer->state; 197 mask = 1 << timer->tn; 198 if (!set || !timer_enabled(timer) || !hpet_enabled(timer->state)) { 199 s->isr &= ~mask; 200 if (!timer_fsb_route(timer)) { 201 /* fold the ICH PIRQ# pin's internal inversion logic into hpet */ 202 if (route >= ISA_NUM_IRQS) { 203 qemu_irq_raise(s->irqs[route]); 204 } else { 205 qemu_irq_lower(s->irqs[route]); 206 } 207 } 208 } else if (timer_fsb_route(timer)) { 209 stl_le_phys(&address_space_memory, 210 timer->fsb >> 32, timer->fsb & 0xffffffff); 211 } else if (timer->config & HPET_TN_TYPE_LEVEL) { 212 s->isr |= mask; 213 /* fold the ICH PIRQ# pin's internal inversion logic into hpet */ 214 if (route >= ISA_NUM_IRQS) { 215 qemu_irq_lower(s->irqs[route]); 216 } else { 217 qemu_irq_raise(s->irqs[route]); 218 } 219 } else { 220 s->isr &= ~mask; 221 qemu_irq_pulse(s->irqs[route]); 222 } 223 } 224 225 static void hpet_pre_save(void *opaque) 226 { 227 HPETState *s = opaque; 228 229 /* save current counter value */ 230 s->hpet_counter = hpet_get_ticks(s); 231 } 232 233 static int hpet_pre_load(void *opaque) 234 { 235 HPETState *s = opaque; 236 237 /* version 1 only supports 3, later versions will load the actual value */ 238 s->num_timers = HPET_MIN_TIMERS; 239 return 0; 240 } 241 242 static int hpet_post_load(void *opaque, int version_id) 243 { 244 HPETState *s = opaque; 245 246 /* Recalculate the offset between the main counter and guest time */ 247 s->hpet_offset = ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 248 249 /* Push number of timers into capability returned via HPET_ID */ 250 s->capability &= ~HPET_ID_NUM_TIM_MASK; 251 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; 252 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; 253 254 /* Derive HPET_MSI_SUPPORT from the capability of the first timer. */ 255 s->flags &= ~(1 << HPET_MSI_SUPPORT); 256 if (s->timer[0].config & HPET_TN_FSB_CAP) { 257 s->flags |= 1 << HPET_MSI_SUPPORT; 258 } 259 return 0; 260 } 261 262 static bool hpet_rtc_irq_level_needed(void *opaque) 263 { 264 HPETState *s = opaque; 265 266 return s->rtc_irq_level != 0; 267 } 268 269 static const VMStateDescription vmstate_hpet_rtc_irq_level = { 270 .name = "hpet/rtc_irq_level", 271 .version_id = 1, 272 .minimum_version_id = 1, 273 .minimum_version_id_old = 1, 274 .fields = (VMStateField[]) { 275 VMSTATE_UINT8(rtc_irq_level, HPETState), 276 VMSTATE_END_OF_LIST() 277 } 278 }; 279 280 static const VMStateDescription vmstate_hpet_timer = { 281 .name = "hpet_timer", 282 .version_id = 1, 283 .minimum_version_id = 1, 284 .minimum_version_id_old = 1, 285 .fields = (VMStateField []) { 286 VMSTATE_UINT8(tn, HPETTimer), 287 VMSTATE_UINT64(config, HPETTimer), 288 VMSTATE_UINT64(cmp, HPETTimer), 289 VMSTATE_UINT64(fsb, HPETTimer), 290 VMSTATE_UINT64(period, HPETTimer), 291 VMSTATE_UINT8(wrap_flag, HPETTimer), 292 VMSTATE_TIMER(qemu_timer, HPETTimer), 293 VMSTATE_END_OF_LIST() 294 } 295 }; 296 297 static const VMStateDescription vmstate_hpet = { 298 .name = "hpet", 299 .version_id = 2, 300 .minimum_version_id = 1, 301 .minimum_version_id_old = 1, 302 .pre_save = hpet_pre_save, 303 .pre_load = hpet_pre_load, 304 .post_load = hpet_post_load, 305 .fields = (VMStateField []) { 306 VMSTATE_UINT64(config, HPETState), 307 VMSTATE_UINT64(isr, HPETState), 308 VMSTATE_UINT64(hpet_counter, HPETState), 309 VMSTATE_UINT8_V(num_timers, HPETState, 2), 310 VMSTATE_STRUCT_VARRAY_UINT8(timer, HPETState, num_timers, 0, 311 vmstate_hpet_timer, HPETTimer), 312 VMSTATE_END_OF_LIST() 313 }, 314 .subsections = (VMStateSubsection[]) { 315 { 316 .vmsd = &vmstate_hpet_rtc_irq_level, 317 .needed = hpet_rtc_irq_level_needed, 318 }, { 319 /* empty */ 320 } 321 } 322 }; 323 324 /* 325 * timer expiration callback 326 */ 327 static void hpet_timer(void *opaque) 328 { 329 HPETTimer *t = opaque; 330 uint64_t diff; 331 332 uint64_t period = t->period; 333 uint64_t cur_tick = hpet_get_ticks(t->state); 334 335 if (timer_is_periodic(t) && period != 0) { 336 if (t->config & HPET_TN_32BIT) { 337 while (hpet_time_after(cur_tick, t->cmp)) { 338 t->cmp = (uint32_t)(t->cmp + t->period); 339 } 340 } else { 341 while (hpet_time_after64(cur_tick, t->cmp)) { 342 t->cmp += period; 343 } 344 } 345 diff = hpet_calculate_diff(t, cur_tick); 346 timer_mod(t->qemu_timer, 347 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff)); 348 } else if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { 349 if (t->wrap_flag) { 350 diff = hpet_calculate_diff(t, cur_tick); 351 timer_mod(t->qemu_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 352 (int64_t)ticks_to_ns(diff)); 353 t->wrap_flag = 0; 354 } 355 } 356 update_irq(t, 1); 357 } 358 359 static void hpet_set_timer(HPETTimer *t) 360 { 361 uint64_t diff; 362 uint32_t wrap_diff; /* how many ticks until we wrap? */ 363 uint64_t cur_tick = hpet_get_ticks(t->state); 364 365 /* whenever new timer is being set up, make sure wrap_flag is 0 */ 366 t->wrap_flag = 0; 367 diff = hpet_calculate_diff(t, cur_tick); 368 369 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when 370 * counter wraps in addition to an interrupt with comparator match. 371 */ 372 if (t->config & HPET_TN_32BIT && !timer_is_periodic(t)) { 373 wrap_diff = 0xffffffff - (uint32_t)cur_tick; 374 if (wrap_diff < (uint32_t)diff) { 375 diff = wrap_diff; 376 t->wrap_flag = 1; 377 } 378 } 379 timer_mod(t->qemu_timer, 380 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (int64_t)ticks_to_ns(diff)); 381 } 382 383 static void hpet_del_timer(HPETTimer *t) 384 { 385 timer_del(t->qemu_timer); 386 update_irq(t, 0); 387 } 388 389 #ifdef HPET_DEBUG 390 static uint32_t hpet_ram_readb(void *opaque, hwaddr addr) 391 { 392 printf("qemu: hpet_read b at %" PRIx64 "\n", addr); 393 return 0; 394 } 395 396 static uint32_t hpet_ram_readw(void *opaque, hwaddr addr) 397 { 398 printf("qemu: hpet_read w at %" PRIx64 "\n", addr); 399 return 0; 400 } 401 #endif 402 403 static uint64_t hpet_ram_read(void *opaque, hwaddr addr, 404 unsigned size) 405 { 406 HPETState *s = opaque; 407 uint64_t cur_tick, index; 408 409 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64 "\n", addr); 410 index = addr; 411 /*address range of all TN regs*/ 412 if (index >= 0x100 && index <= 0x3ff) { 413 uint8_t timer_id = (addr - 0x100) / 0x20; 414 HPETTimer *timer = &s->timer[timer_id]; 415 416 if (timer_id > s->num_timers) { 417 DPRINTF("qemu: timer id out of range\n"); 418 return 0; 419 } 420 421 switch ((addr - 0x100) % 0x20) { 422 case HPET_TN_CFG: 423 return timer->config; 424 case HPET_TN_CFG + 4: // Interrupt capabilities 425 return timer->config >> 32; 426 case HPET_TN_CMP: // comparator register 427 return timer->cmp; 428 case HPET_TN_CMP + 4: 429 return timer->cmp >> 32; 430 case HPET_TN_ROUTE: 431 return timer->fsb; 432 case HPET_TN_ROUTE + 4: 433 return timer->fsb >> 32; 434 default: 435 DPRINTF("qemu: invalid hpet_ram_readl\n"); 436 break; 437 } 438 } else { 439 switch (index) { 440 case HPET_ID: 441 return s->capability; 442 case HPET_PERIOD: 443 return s->capability >> 32; 444 case HPET_CFG: 445 return s->config; 446 case HPET_CFG + 4: 447 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl\n"); 448 return 0; 449 case HPET_COUNTER: 450 if (hpet_enabled(s)) { 451 cur_tick = hpet_get_ticks(s); 452 } else { 453 cur_tick = s->hpet_counter; 454 } 455 DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick); 456 return cur_tick; 457 case HPET_COUNTER + 4: 458 if (hpet_enabled(s)) { 459 cur_tick = hpet_get_ticks(s); 460 } else { 461 cur_tick = s->hpet_counter; 462 } 463 DPRINTF("qemu: reading counter + 4 = %" PRIx64 "\n", cur_tick); 464 return cur_tick >> 32; 465 case HPET_STATUS: 466 return s->isr; 467 default: 468 DPRINTF("qemu: invalid hpet_ram_readl\n"); 469 break; 470 } 471 } 472 return 0; 473 } 474 475 static void hpet_ram_write(void *opaque, hwaddr addr, 476 uint64_t value, unsigned size) 477 { 478 int i; 479 HPETState *s = opaque; 480 uint64_t old_val, new_val, val, index; 481 482 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64 " = %#x\n", addr, value); 483 index = addr; 484 old_val = hpet_ram_read(opaque, addr, 4); 485 new_val = value; 486 487 /*address range of all TN regs*/ 488 if (index >= 0x100 && index <= 0x3ff) { 489 uint8_t timer_id = (addr - 0x100) / 0x20; 490 HPETTimer *timer = &s->timer[timer_id]; 491 492 DPRINTF("qemu: hpet_ram_writel timer_id = %#x\n", timer_id); 493 if (timer_id > s->num_timers) { 494 DPRINTF("qemu: timer id out of range\n"); 495 return; 496 } 497 switch ((addr - 0x100) % 0x20) { 498 case HPET_TN_CFG: 499 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n"); 500 if (activating_bit(old_val, new_val, HPET_TN_FSB_ENABLE)) { 501 update_irq(timer, 0); 502 } 503 val = hpet_fixup_reg(new_val, old_val, HPET_TN_CFG_WRITE_MASK); 504 timer->config = (timer->config & 0xffffffff00000000ULL) | val; 505 if (new_val & HPET_TN_32BIT) { 506 timer->cmp = (uint32_t)timer->cmp; 507 timer->period = (uint32_t)timer->period; 508 } 509 if (activating_bit(old_val, new_val, HPET_TN_ENABLE) && 510 hpet_enabled(s)) { 511 hpet_set_timer(timer); 512 } else if (deactivating_bit(old_val, new_val, HPET_TN_ENABLE)) { 513 hpet_del_timer(timer); 514 } 515 break; 516 case HPET_TN_CFG + 4: // Interrupt capabilities 517 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n"); 518 break; 519 case HPET_TN_CMP: // comparator register 520 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP\n"); 521 if (timer->config & HPET_TN_32BIT) { 522 new_val = (uint32_t)new_val; 523 } 524 if (!timer_is_periodic(timer) 525 || (timer->config & HPET_TN_SETVAL)) { 526 timer->cmp = (timer->cmp & 0xffffffff00000000ULL) | new_val; 527 } 528 if (timer_is_periodic(timer)) { 529 /* 530 * FIXME: Clamp period to reasonable min value? 531 * Clamp period to reasonable max value 532 */ 533 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; 534 timer->period = 535 (timer->period & 0xffffffff00000000ULL) | new_val; 536 } 537 timer->config &= ~HPET_TN_SETVAL; 538 if (hpet_enabled(s)) { 539 hpet_set_timer(timer); 540 } 541 break; 542 case HPET_TN_CMP + 4: // comparator register high order 543 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n"); 544 if (!timer_is_periodic(timer) 545 || (timer->config & HPET_TN_SETVAL)) { 546 timer->cmp = (timer->cmp & 0xffffffffULL) | new_val << 32; 547 } else { 548 /* 549 * FIXME: Clamp period to reasonable min value? 550 * Clamp period to reasonable max value 551 */ 552 new_val &= (timer->config & HPET_TN_32BIT ? ~0u : ~0ull) >> 1; 553 timer->period = 554 (timer->period & 0xffffffffULL) | new_val << 32; 555 } 556 timer->config &= ~HPET_TN_SETVAL; 557 if (hpet_enabled(s)) { 558 hpet_set_timer(timer); 559 } 560 break; 561 case HPET_TN_ROUTE: 562 timer->fsb = (timer->fsb & 0xffffffff00000000ULL) | new_val; 563 break; 564 case HPET_TN_ROUTE + 4: 565 timer->fsb = (new_val << 32) | (timer->fsb & 0xffffffff); 566 break; 567 default: 568 DPRINTF("qemu: invalid hpet_ram_writel\n"); 569 break; 570 } 571 return; 572 } else { 573 switch (index) { 574 case HPET_ID: 575 return; 576 case HPET_CFG: 577 val = hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MASK); 578 s->config = (s->config & 0xffffffff00000000ULL) | val; 579 if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { 580 /* Enable main counter and interrupt generation. */ 581 s->hpet_offset = 582 ticks_to_ns(s->hpet_counter) - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 583 for (i = 0; i < s->num_timers; i++) { 584 if ((&s->timer[i])->cmp != ~0ULL) { 585 hpet_set_timer(&s->timer[i]); 586 } 587 } 588 } else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) { 589 /* Halt main counter and disable interrupt generation. */ 590 s->hpet_counter = hpet_get_ticks(s); 591 for (i = 0; i < s->num_timers; i++) { 592 hpet_del_timer(&s->timer[i]); 593 } 594 } 595 /* i8254 and RTC output pins are disabled 596 * when HPET is in legacy mode */ 597 if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { 598 qemu_set_irq(s->pit_enabled, 0); 599 qemu_irq_lower(s->irqs[0]); 600 qemu_irq_lower(s->irqs[RTC_ISA_IRQ]); 601 } else if (deactivating_bit(old_val, new_val, HPET_CFG_LEGACY)) { 602 qemu_irq_lower(s->irqs[0]); 603 qemu_set_irq(s->pit_enabled, 1); 604 qemu_set_irq(s->irqs[RTC_ISA_IRQ], s->rtc_irq_level); 605 } 606 break; 607 case HPET_CFG + 4: 608 DPRINTF("qemu: invalid HPET_CFG+4 write\n"); 609 break; 610 case HPET_STATUS: 611 val = new_val & s->isr; 612 for (i = 0; i < s->num_timers; i++) { 613 if (val & (1 << i)) { 614 update_irq(&s->timer[i], 0); 615 } 616 } 617 break; 618 case HPET_COUNTER: 619 if (hpet_enabled(s)) { 620 DPRINTF("qemu: Writing counter while HPET enabled!\n"); 621 } 622 s->hpet_counter = 623 (s->hpet_counter & 0xffffffff00000000ULL) | value; 624 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64 "\n", 625 value, s->hpet_counter); 626 break; 627 case HPET_COUNTER + 4: 628 if (hpet_enabled(s)) { 629 DPRINTF("qemu: Writing counter while HPET enabled!\n"); 630 } 631 s->hpet_counter = 632 (s->hpet_counter & 0xffffffffULL) | (((uint64_t)value) << 32); 633 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64 "\n", 634 value, s->hpet_counter); 635 break; 636 default: 637 DPRINTF("qemu: invalid hpet_ram_writel\n"); 638 break; 639 } 640 } 641 } 642 643 static const MemoryRegionOps hpet_ram_ops = { 644 .read = hpet_ram_read, 645 .write = hpet_ram_write, 646 .valid = { 647 .min_access_size = 4, 648 .max_access_size = 4, 649 }, 650 .endianness = DEVICE_NATIVE_ENDIAN, 651 }; 652 653 static void hpet_reset(DeviceState *d) 654 { 655 HPETState *s = HPET(d); 656 SysBusDevice *sbd = SYS_BUS_DEVICE(d); 657 int i; 658 659 for (i = 0; i < s->num_timers; i++) { 660 HPETTimer *timer = &s->timer[i]; 661 662 hpet_del_timer(timer); 663 timer->cmp = ~0ULL; 664 timer->config = HPET_TN_PERIODIC_CAP | HPET_TN_SIZE_CAP; 665 if (s->flags & (1 << HPET_MSI_SUPPORT)) { 666 timer->config |= HPET_TN_FSB_CAP; 667 } 668 /* advertise availability of ioapic int */ 669 timer->config |= (uint64_t)s->intcap << 32; 670 timer->period = 0ULL; 671 timer->wrap_flag = 0; 672 } 673 674 qemu_set_irq(s->pit_enabled, 1); 675 s->hpet_counter = 0ULL; 676 s->hpet_offset = 0ULL; 677 s->config = 0ULL; 678 hpet_cfg.hpet[s->hpet_id].event_timer_block_id = (uint32_t)s->capability; 679 hpet_cfg.hpet[s->hpet_id].address = sbd->mmio[0].addr; 680 681 /* to document that the RTC lowers its output on reset as well */ 682 s->rtc_irq_level = 0; 683 } 684 685 static void hpet_handle_legacy_irq(void *opaque, int n, int level) 686 { 687 HPETState *s = HPET(opaque); 688 689 if (n == HPET_LEGACY_PIT_INT) { 690 if (!hpet_in_legacy_mode(s)) { 691 qemu_set_irq(s->irqs[0], level); 692 } 693 } else { 694 s->rtc_irq_level = level; 695 if (!hpet_in_legacy_mode(s)) { 696 qemu_set_irq(s->irqs[RTC_ISA_IRQ], level); 697 } 698 } 699 } 700 701 static void hpet_init(Object *obj) 702 { 703 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 704 HPETState *s = HPET(obj); 705 706 /* HPET Area */ 707 memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", 0x400); 708 sysbus_init_mmio(sbd, &s->iomem); 709 } 710 711 static void hpet_realize(DeviceState *dev, Error **errp) 712 { 713 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 714 HPETState *s = HPET(dev); 715 int i; 716 HPETTimer *timer; 717 718 if (!s->intcap) { 719 error_printf("Hpet's intcap not initialized.\n"); 720 } 721 if (hpet_cfg.count == UINT8_MAX) { 722 /* first instance */ 723 hpet_cfg.count = 0; 724 } 725 726 if (hpet_cfg.count == 8) { 727 error_setg(errp, "Only 8 instances of HPET is allowed"); 728 return; 729 } 730 731 s->hpet_id = hpet_cfg.count++; 732 733 for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) { 734 sysbus_init_irq(sbd, &s->irqs[i]); 735 } 736 737 if (s->num_timers < HPET_MIN_TIMERS) { 738 s->num_timers = HPET_MIN_TIMERS; 739 } else if (s->num_timers > HPET_MAX_TIMERS) { 740 s->num_timers = HPET_MAX_TIMERS; 741 } 742 for (i = 0; i < HPET_MAX_TIMERS; i++) { 743 timer = &s->timer[i]; 744 timer->qemu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, hpet_timer, timer); 745 timer->tn = i; 746 timer->state = s; 747 } 748 749 /* 64-bit main counter; LegacyReplacementRoute. */ 750 s->capability = 0x8086a001ULL; 751 s->capability |= (s->num_timers - 1) << HPET_ID_NUM_TIM_SHIFT; 752 s->capability |= ((HPET_CLK_PERIOD) << 32); 753 754 qdev_init_gpio_in(dev, hpet_handle_legacy_irq, 2); 755 qdev_init_gpio_out(dev, &s->pit_enabled, 1); 756 } 757 758 static Property hpet_device_properties[] = { 759 DEFINE_PROP_UINT8("timers", HPETState, num_timers, HPET_MIN_TIMERS), 760 DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false), 761 DEFINE_PROP_UINT32(HPET_INTCAP, HPETState, intcap, 0), 762 DEFINE_PROP_END_OF_LIST(), 763 }; 764 765 static void hpet_device_class_init(ObjectClass *klass, void *data) 766 { 767 DeviceClass *dc = DEVICE_CLASS(klass); 768 769 dc->realize = hpet_realize; 770 dc->reset = hpet_reset; 771 dc->vmsd = &vmstate_hpet; 772 dc->props = hpet_device_properties; 773 } 774 775 static const TypeInfo hpet_device_info = { 776 .name = TYPE_HPET, 777 .parent = TYPE_SYS_BUS_DEVICE, 778 .instance_size = sizeof(HPETState), 779 .instance_init = hpet_init, 780 .class_init = hpet_device_class_init, 781 }; 782 783 static void hpet_register_types(void) 784 { 785 type_register_static(&hpet_device_info); 786 } 787 788 type_init(hpet_register_types) 789