xref: /qemu/hw/timer/imx_gpt.c (revision 52ea63de)
1 /*
2  * IMX GPT Timer
3  *
4  * Copyright (c) 2008 OK Labs
5  * Copyright (c) 2011 NICTA Pty Ltd
6  * Originally written by Hans Jiang
7  * Updated by Peter Chubb
8  * Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
9  *
10  * This code is licensed under GPL version 2 or later.  See
11  * the COPYING file in the top-level directory.
12  *
13  */
14 
15 #include "qemu/osdep.h"
16 #include "hw/timer/imx_gpt.h"
17 #include "hw/misc/imx_ccm.h"
18 #include "qemu/main-loop.h"
19 #include "qemu/log.h"
20 
21 #ifndef DEBUG_IMX_GPT
22 #define DEBUG_IMX_GPT 0
23 #endif
24 
25 #define DPRINTF(fmt, args...) \
26     do { \
27         if (DEBUG_IMX_GPT) { \
28             fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_GPT, \
29                                              __func__, ##args); \
30         } \
31     } while (0)
32 
33 static char const *imx_gpt_reg_name(uint32_t reg)
34 {
35     switch (reg) {
36     case 0:
37         return "CR";
38     case 1:
39         return "PR";
40     case 2:
41         return "SR";
42     case 3:
43         return "IR";
44     case 4:
45         return "OCR1";
46     case 5:
47         return "OCR2";
48     case 6:
49         return "OCR3";
50     case 7:
51         return "ICR1";
52     case 8:
53         return "ICR2";
54     case 9:
55         return "CNT";
56     default:
57         return "[?]";
58     }
59 }
60 
61 static const VMStateDescription vmstate_imx_timer_gpt = {
62     .name = TYPE_IMX_GPT,
63     .version_id = 3,
64     .minimum_version_id = 3,
65     .fields = (VMStateField[]) {
66         VMSTATE_UINT32(cr, IMXGPTState),
67         VMSTATE_UINT32(pr, IMXGPTState),
68         VMSTATE_UINT32(sr, IMXGPTState),
69         VMSTATE_UINT32(ir, IMXGPTState),
70         VMSTATE_UINT32(ocr1, IMXGPTState),
71         VMSTATE_UINT32(ocr2, IMXGPTState),
72         VMSTATE_UINT32(ocr3, IMXGPTState),
73         VMSTATE_UINT32(icr1, IMXGPTState),
74         VMSTATE_UINT32(icr2, IMXGPTState),
75         VMSTATE_UINT32(cnt, IMXGPTState),
76         VMSTATE_UINT32(next_timeout, IMXGPTState),
77         VMSTATE_UINT32(next_int, IMXGPTState),
78         VMSTATE_UINT32(freq, IMXGPTState),
79         VMSTATE_PTIMER(timer, IMXGPTState),
80         VMSTATE_END_OF_LIST()
81     }
82 };
83 
84 static const IMXClk imx_gpt_clocks[] = {
85     CLK_NONE,      /* 000 No clock source */
86     CLK_IPG,       /* 001 ipg_clk, 532MHz*/
87     CLK_IPG_HIGH,  /* 010 ipg_clk_highfreq */
88     CLK_NONE,      /* 011 not defined */
89     CLK_32k,       /* 100 ipg_clk_32k */
90     CLK_NONE,      /* 101 not defined */
91     CLK_NONE,      /* 110 not defined */
92     CLK_NONE,      /* 111 not defined */
93 };
94 
95 static void imx_gpt_set_freq(IMXGPTState *s)
96 {
97     uint32_t clksrc = extract32(s->cr, GPT_CR_CLKSRC_SHIFT, 3);
98 
99     s->freq = imx_ccm_get_clock_frequency(s->ccm,
100                                 imx_gpt_clocks[clksrc]) / (1 + s->pr);
101 
102     DPRINTF("Setting clksrc %d to frequency %d\n", clksrc, s->freq);
103 
104     if (s->freq) {
105         ptimer_set_freq(s->timer, s->freq);
106     }
107 }
108 
109 static void imx_gpt_update_int(IMXGPTState *s)
110 {
111     if ((s->sr & s->ir) && (s->cr & GPT_CR_EN)) {
112         qemu_irq_raise(s->irq);
113     } else {
114         qemu_irq_lower(s->irq);
115     }
116 }
117 
118 static uint32_t imx_gpt_update_count(IMXGPTState *s)
119 {
120     s->cnt = s->next_timeout - (uint32_t)ptimer_get_count(s->timer);
121 
122     return s->cnt;
123 }
124 
125 static inline uint32_t imx_gpt_find_limit(uint32_t count, uint32_t reg,
126                                           uint32_t timeout)
127 {
128     if ((count < reg) && (timeout > reg)) {
129         timeout = reg;
130     }
131 
132     return timeout;
133 }
134 
135 static void imx_gpt_compute_next_timeout(IMXGPTState *s, bool event)
136 {
137     uint32_t timeout = GPT_TIMER_MAX;
138     uint32_t count;
139     long long limit;
140 
141     if (!(s->cr & GPT_CR_EN)) {
142         /* if not enabled just return */
143         return;
144     }
145 
146     /* update the count */
147     count = imx_gpt_update_count(s);
148 
149     if (event) {
150         /*
151          * This is an event (the ptimer reached 0 and stopped), and the
152          * timer counter is now equal to s->next_timeout.
153          */
154         if (!(s->cr & GPT_CR_FRR) && (count == s->ocr1)) {
155             /* We are in restart mode and we crossed the compare channel 1
156              * value. We need to reset the counter to 0.
157              */
158             count = s->cnt = s->next_timeout = 0;
159         } else if (count == GPT_TIMER_MAX) {
160             /* We reached GPT_TIMER_MAX so we need to rollover */
161             count = s->cnt = s->next_timeout = 0;
162         }
163     }
164 
165     /* now, find the next timeout related to count */
166 
167     if (s->ir & GPT_IR_OF1IE) {
168         timeout = imx_gpt_find_limit(count, s->ocr1, timeout);
169     }
170     if (s->ir & GPT_IR_OF2IE) {
171         timeout = imx_gpt_find_limit(count, s->ocr2, timeout);
172     }
173     if (s->ir & GPT_IR_OF3IE) {
174         timeout = imx_gpt_find_limit(count, s->ocr3, timeout);
175     }
176 
177     /* find the next set of interrupts to raise for next timer event */
178 
179     s->next_int = 0;
180     if ((s->ir & GPT_IR_OF1IE) && (timeout == s->ocr1)) {
181         s->next_int |= GPT_SR_OF1;
182     }
183     if ((s->ir & GPT_IR_OF2IE) && (timeout == s->ocr2)) {
184         s->next_int |= GPT_SR_OF2;
185     }
186     if ((s->ir & GPT_IR_OF3IE) && (timeout == s->ocr3)) {
187         s->next_int |= GPT_SR_OF3;
188     }
189     if ((s->ir & GPT_IR_ROVIE) && (timeout == GPT_TIMER_MAX)) {
190         s->next_int |= GPT_SR_ROV;
191     }
192 
193     /* the new range to count down from */
194     limit = timeout - imx_gpt_update_count(s);
195 
196     if (limit < 0) {
197         /*
198          * if we reach here, then QEMU is running too slow and we pass the
199          * timeout limit while computing it. Let's deliver the interrupt
200          * and compute a new limit.
201          */
202         s->sr |= s->next_int;
203 
204         imx_gpt_compute_next_timeout(s, event);
205 
206         imx_gpt_update_int(s);
207     } else {
208         /* New timeout value */
209         s->next_timeout = timeout;
210 
211         /* reset the limit to the computed range */
212         ptimer_set_limit(s->timer, limit, 1);
213     }
214 }
215 
216 static uint64_t imx_gpt_read(void *opaque, hwaddr offset, unsigned size)
217 {
218     IMXGPTState *s = IMX_GPT(opaque);
219     uint32_t reg_value = 0;
220 
221     switch (offset >> 2) {
222     case 0: /* Control Register */
223         reg_value = s->cr;
224         break;
225 
226     case 1: /* prescaler */
227         reg_value = s->pr;
228         break;
229 
230     case 2: /* Status Register */
231         reg_value = s->sr;
232         break;
233 
234     case 3: /* Interrupt Register */
235         reg_value = s->ir;
236         break;
237 
238     case 4: /* Output Compare Register 1 */
239         reg_value = s->ocr1;
240         break;
241 
242     case 5: /* Output Compare Register 2 */
243         reg_value = s->ocr2;
244         break;
245 
246     case 6: /* Output Compare Register 3 */
247         reg_value = s->ocr3;
248         break;
249 
250     case 7: /* input Capture Register 1 */
251         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr1 feature is not implemented\n",
252                       TYPE_IMX_GPT, __func__);
253         reg_value = s->icr1;
254         break;
255 
256     case 8: /* input Capture Register 2 */
257         qemu_log_mask(LOG_UNIMP, "[%s]%s: icr2 feature is not implemented\n",
258                       TYPE_IMX_GPT, __func__);
259         reg_value = s->icr2;
260         break;
261 
262     case 9: /* cnt */
263         imx_gpt_update_count(s);
264         reg_value = s->cnt;
265         break;
266 
267     default:
268         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
269                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
270         break;
271     }
272 
273     DPRINTF("(%s) = 0x%08x\n", imx_gpt_reg_name(offset >> 2), reg_value);
274 
275     return reg_value;
276 }
277 
278 static void imx_gpt_reset(DeviceState *dev)
279 {
280     IMXGPTState *s = IMX_GPT(dev);
281 
282     /* stop timer */
283     ptimer_stop(s->timer);
284 
285     /*
286      * Soft reset doesn't touch some bits; hard reset clears them
287      */
288     s->cr &= ~(GPT_CR_EN|GPT_CR_ENMOD|GPT_CR_STOPEN|GPT_CR_DOZEN|
289                GPT_CR_WAITEN|GPT_CR_DBGEN);
290     s->sr = 0;
291     s->pr = 0;
292     s->ir = 0;
293     s->cnt = 0;
294     s->ocr1 = GPT_TIMER_MAX;
295     s->ocr2 = GPT_TIMER_MAX;
296     s->ocr3 = GPT_TIMER_MAX;
297     s->icr1 = 0;
298     s->icr2 = 0;
299 
300     s->next_timeout = GPT_TIMER_MAX;
301     s->next_int = 0;
302 
303     /* compute new freq */
304     imx_gpt_set_freq(s);
305 
306     /* reset the limit to GPT_TIMER_MAX */
307     ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
308 
309     /* if the timer is still enabled, restart it */
310     if (s->freq && (s->cr & GPT_CR_EN)) {
311         ptimer_run(s->timer, 1);
312     }
313 }
314 
315 static void imx_gpt_write(void *opaque, hwaddr offset, uint64_t value,
316                           unsigned size)
317 {
318     IMXGPTState *s = IMX_GPT(opaque);
319     uint32_t oldreg;
320 
321     DPRINTF("(%s, value = 0x%08x)\n", imx_gpt_reg_name(offset >> 2),
322             (uint32_t)value);
323 
324     switch (offset >> 2) {
325     case 0:
326         oldreg = s->cr;
327         s->cr = value & ~0x7c14;
328         if (s->cr & GPT_CR_SWR) { /* force reset */
329             /* handle the reset */
330             imx_gpt_reset(DEVICE(s));
331         } else {
332             /* set our freq, as the source might have changed */
333             imx_gpt_set_freq(s);
334 
335             if ((oldreg ^ s->cr) & GPT_CR_EN) {
336                 if (s->cr & GPT_CR_EN) {
337                     if (s->cr & GPT_CR_ENMOD) {
338                         s->next_timeout = GPT_TIMER_MAX;
339                         ptimer_set_count(s->timer, GPT_TIMER_MAX);
340                         imx_gpt_compute_next_timeout(s, false);
341                     }
342                     ptimer_run(s->timer, 1);
343                 } else {
344                     /* stop timer */
345                     ptimer_stop(s->timer);
346                 }
347             }
348         }
349         break;
350 
351     case 1: /* Prescaler */
352         s->pr = value & 0xfff;
353         imx_gpt_set_freq(s);
354         break;
355 
356     case 2: /* SR */
357         s->sr &= ~(value & 0x3f);
358         imx_gpt_update_int(s);
359         break;
360 
361     case 3: /* IR -- interrupt register */
362         s->ir = value & 0x3f;
363         imx_gpt_update_int(s);
364 
365         imx_gpt_compute_next_timeout(s, false);
366 
367         break;
368 
369     case 4: /* OCR1 -- output compare register */
370         s->ocr1 = value;
371 
372         /* In non-freerun mode, reset count when this register is written */
373         if (!(s->cr & GPT_CR_FRR)) {
374             s->next_timeout = GPT_TIMER_MAX;
375             ptimer_set_limit(s->timer, GPT_TIMER_MAX, 1);
376         }
377 
378         /* compute the new timeout */
379         imx_gpt_compute_next_timeout(s, false);
380 
381         break;
382 
383     case 5: /* OCR2 -- output compare register */
384         s->ocr2 = value;
385 
386         /* compute the new timeout */
387         imx_gpt_compute_next_timeout(s, false);
388 
389         break;
390 
391     case 6: /* OCR3 -- output compare register */
392         s->ocr3 = value;
393 
394         /* compute the new timeout */
395         imx_gpt_compute_next_timeout(s, false);
396 
397         break;
398 
399     default:
400         qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
401                       HWADDR_PRIx "\n", TYPE_IMX_GPT, __func__, offset);
402         break;
403     }
404 }
405 
406 static void imx_gpt_timeout(void *opaque)
407 {
408     IMXGPTState *s = IMX_GPT(opaque);
409 
410     DPRINTF("\n");
411 
412     s->sr |= s->next_int;
413     s->next_int = 0;
414 
415     imx_gpt_compute_next_timeout(s, true);
416 
417     imx_gpt_update_int(s);
418 
419     if (s->freq && (s->cr & GPT_CR_EN)) {
420         ptimer_run(s->timer, 1);
421     }
422 }
423 
424 static const MemoryRegionOps imx_gpt_ops = {
425     .read = imx_gpt_read,
426     .write = imx_gpt_write,
427     .endianness = DEVICE_NATIVE_ENDIAN,
428 };
429 
430 
431 static void imx_gpt_realize(DeviceState *dev, Error **errp)
432 {
433     IMXGPTState *s = IMX_GPT(dev);
434     SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
435     QEMUBH *bh;
436 
437     sysbus_init_irq(sbd, &s->irq);
438     memory_region_init_io(&s->iomem, OBJECT(s), &imx_gpt_ops, s, TYPE_IMX_GPT,
439                           0x00001000);
440     sysbus_init_mmio(sbd, &s->iomem);
441 
442     bh = qemu_bh_new(imx_gpt_timeout, s);
443     s->timer = ptimer_init(bh);
444 }
445 
446 static void imx_gpt_class_init(ObjectClass *klass, void *data)
447 {
448     DeviceClass *dc = DEVICE_CLASS(klass);
449 
450     dc->realize = imx_gpt_realize;
451     dc->reset = imx_gpt_reset;
452     dc->vmsd = &vmstate_imx_timer_gpt;
453     dc->desc = "i.MX general timer";
454 }
455 
456 static const TypeInfo imx_gpt_info = {
457     .name = TYPE_IMX_GPT,
458     .parent = TYPE_SYS_BUS_DEVICE,
459     .instance_size = sizeof(IMXGPTState),
460     .class_init = imx_gpt_class_init,
461 };
462 
463 static void imx_gpt_register_types(void)
464 {
465     type_register_static(&imx_gpt_info);
466 }
467 
468 type_init(imx_gpt_register_types)
469