185fdd74fSHavard Skinnemoen /* 285fdd74fSHavard Skinnemoen * Nuvoton NPCM7xx Timer Controller 385fdd74fSHavard Skinnemoen * 485fdd74fSHavard Skinnemoen * Copyright 2020 Google LLC 585fdd74fSHavard Skinnemoen * 685fdd74fSHavard Skinnemoen * This program is free software; you can redistribute it and/or modify it 785fdd74fSHavard Skinnemoen * under the terms of the GNU General Public License as published by the 885fdd74fSHavard Skinnemoen * Free Software Foundation; either version 2 of the License, or 985fdd74fSHavard Skinnemoen * (at your option) any later version. 1085fdd74fSHavard Skinnemoen * 1185fdd74fSHavard Skinnemoen * This program is distributed in the hope that it will be useful, but WITHOUT 1285fdd74fSHavard Skinnemoen * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 1385fdd74fSHavard Skinnemoen * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 1485fdd74fSHavard Skinnemoen * for more details. 1585fdd74fSHavard Skinnemoen */ 1685fdd74fSHavard Skinnemoen 1785fdd74fSHavard Skinnemoen #include "qemu/osdep.h" 1885fdd74fSHavard Skinnemoen 1985fdd74fSHavard Skinnemoen #include "hw/irq.h" 20*0be12dc7SHao Wu #include "hw/qdev-clock.h" 217d378ed6SHao Wu #include "hw/qdev-properties.h" 2285fdd74fSHavard Skinnemoen #include "hw/timer/npcm7xx_timer.h" 2385fdd74fSHavard Skinnemoen #include "migration/vmstate.h" 2485fdd74fSHavard Skinnemoen #include "qemu/bitops.h" 2585fdd74fSHavard Skinnemoen #include "qemu/error-report.h" 2685fdd74fSHavard Skinnemoen #include "qemu/log.h" 2785fdd74fSHavard Skinnemoen #include "qemu/module.h" 2885fdd74fSHavard Skinnemoen #include "qemu/timer.h" 2985fdd74fSHavard Skinnemoen #include "qemu/units.h" 3085fdd74fSHavard Skinnemoen #include "trace.h" 3185fdd74fSHavard Skinnemoen 3285fdd74fSHavard Skinnemoen /* 32-bit register indices. */ 3385fdd74fSHavard Skinnemoen enum NPCM7xxTimerRegisters { 3485fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TCSR0, 3585fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TCSR1, 3685fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TICR0, 3785fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TICR1, 3885fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TDR0, 3985fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TDR1, 4085fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TISR, 4185fdd74fSHavard Skinnemoen NPCM7XX_TIMER_WTCR, 4285fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TCSR2, 4385fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TCSR3, 4485fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TICR2, 4585fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TICR3, 4685fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TDR2, 4785fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TDR3, 4885fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TCSR4 = 0x0040 / sizeof(uint32_t), 4985fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TICR4 = 0x0048 / sizeof(uint32_t), 5085fdd74fSHavard Skinnemoen NPCM7XX_TIMER_TDR4 = 0x0050 / sizeof(uint32_t), 5185fdd74fSHavard Skinnemoen NPCM7XX_TIMER_REGS_END, 5285fdd74fSHavard Skinnemoen }; 5385fdd74fSHavard Skinnemoen 5485fdd74fSHavard Skinnemoen /* Register field definitions. */ 5585fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_CEN BIT(30) 5685fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_IE BIT(29) 5785fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_PERIODIC BIT(27) 5885fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_CRST BIT(26) 5985fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_CACT BIT(25) 6085fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_RSVD 0x01ffff00 6185fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_PRESCALE_START 0 6285fdd74fSHavard Skinnemoen #define NPCM7XX_TCSR_PRESCALE_LEN 8 6385fdd74fSHavard Skinnemoen 647d378ed6SHao Wu #define NPCM7XX_WTCR_WTCLK(rv) extract32(rv, 10, 2) 657d378ed6SHao Wu #define NPCM7XX_WTCR_FREEZE_EN BIT(9) 667d378ed6SHao Wu #define NPCM7XX_WTCR_WTE BIT(7) 677d378ed6SHao Wu #define NPCM7XX_WTCR_WTIE BIT(6) 687d378ed6SHao Wu #define NPCM7XX_WTCR_WTIS(rv) extract32(rv, 4, 2) 697d378ed6SHao Wu #define NPCM7XX_WTCR_WTIF BIT(3) 707d378ed6SHao Wu #define NPCM7XX_WTCR_WTRF BIT(2) 717d378ed6SHao Wu #define NPCM7XX_WTCR_WTRE BIT(1) 727d378ed6SHao Wu #define NPCM7XX_WTCR_WTR BIT(0) 737d378ed6SHao Wu 747d378ed6SHao Wu /* 757d378ed6SHao Wu * The number of clock cycles between interrupt and reset in watchdog, used 767d378ed6SHao Wu * by the software to handle the interrupt before system is reset. 777d378ed6SHao Wu */ 787d378ed6SHao Wu #define NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES 1024 797d378ed6SHao Wu 807d378ed6SHao Wu /* Start or resume the timer. */ 817d378ed6SHao Wu static void npcm7xx_timer_start(NPCM7xxBaseTimer *t) 827d378ed6SHao Wu { 837d378ed6SHao Wu int64_t now; 847d378ed6SHao Wu 857d378ed6SHao Wu now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 867d378ed6SHao Wu t->expires_ns = now + t->remaining_ns; 877d378ed6SHao Wu timer_mod(&t->qtimer, t->expires_ns); 887d378ed6SHao Wu } 897d378ed6SHao Wu 907d378ed6SHao Wu /* Stop counting. Record the time remaining so we can continue later. */ 917d378ed6SHao Wu static void npcm7xx_timer_pause(NPCM7xxBaseTimer *t) 927d378ed6SHao Wu { 937d378ed6SHao Wu int64_t now; 947d378ed6SHao Wu 957d378ed6SHao Wu timer_del(&t->qtimer); 967d378ed6SHao Wu now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 977d378ed6SHao Wu t->remaining_ns = t->expires_ns - now; 987d378ed6SHao Wu } 997d378ed6SHao Wu 1007d378ed6SHao Wu /* Delete the timer and reset it to default state. */ 1017d378ed6SHao Wu static void npcm7xx_timer_clear(NPCM7xxBaseTimer *t) 1027d378ed6SHao Wu { 1037d378ed6SHao Wu timer_del(&t->qtimer); 1047d378ed6SHao Wu t->expires_ns = 0; 1057d378ed6SHao Wu t->remaining_ns = 0; 1067d378ed6SHao Wu } 1077d378ed6SHao Wu 10885fdd74fSHavard Skinnemoen /* 10985fdd74fSHavard Skinnemoen * Returns the index of timer in the tc->timer array. This can be used to 11085fdd74fSHavard Skinnemoen * locate the registers that belong to this timer. 11185fdd74fSHavard Skinnemoen */ 11285fdd74fSHavard Skinnemoen static int npcm7xx_timer_index(NPCM7xxTimerCtrlState *tc, NPCM7xxTimer *timer) 11385fdd74fSHavard Skinnemoen { 11485fdd74fSHavard Skinnemoen int index = timer - tc->timer; 11585fdd74fSHavard Skinnemoen 11685fdd74fSHavard Skinnemoen g_assert(index >= 0 && index < NPCM7XX_TIMERS_PER_CTRL); 11785fdd74fSHavard Skinnemoen 11885fdd74fSHavard Skinnemoen return index; 11985fdd74fSHavard Skinnemoen } 12085fdd74fSHavard Skinnemoen 12185fdd74fSHavard Skinnemoen /* Return the value by which to divide the reference clock rate. */ 12285fdd74fSHavard Skinnemoen static uint32_t npcm7xx_tcsr_prescaler(uint32_t tcsr) 12385fdd74fSHavard Skinnemoen { 12485fdd74fSHavard Skinnemoen return extract32(tcsr, NPCM7XX_TCSR_PRESCALE_START, 12585fdd74fSHavard Skinnemoen NPCM7XX_TCSR_PRESCALE_LEN) + 1; 12685fdd74fSHavard Skinnemoen } 12785fdd74fSHavard Skinnemoen 12885fdd74fSHavard Skinnemoen /* Convert a timer cycle count to a time interval in nanoseconds. */ 12985fdd74fSHavard Skinnemoen static int64_t npcm7xx_timer_count_to_ns(NPCM7xxTimer *t, uint32_t count) 13085fdd74fSHavard Skinnemoen { 131*0be12dc7SHao Wu int64_t ticks = count; 13285fdd74fSHavard Skinnemoen 133*0be12dc7SHao Wu ticks *= npcm7xx_tcsr_prescaler(t->tcsr); 13485fdd74fSHavard Skinnemoen 135*0be12dc7SHao Wu return clock_ticks_to_ns(t->ctrl->clock, ticks); 13685fdd74fSHavard Skinnemoen } 13785fdd74fSHavard Skinnemoen 13885fdd74fSHavard Skinnemoen /* Convert a time interval in nanoseconds to a timer cycle count. */ 13985fdd74fSHavard Skinnemoen static uint32_t npcm7xx_timer_ns_to_count(NPCM7xxTimer *t, int64_t ns) 14085fdd74fSHavard Skinnemoen { 141*0be12dc7SHao Wu return ns / clock_ticks_to_ns(t->ctrl->clock, 142*0be12dc7SHao Wu npcm7xx_tcsr_prescaler(t->tcsr)); 14385fdd74fSHavard Skinnemoen } 14485fdd74fSHavard Skinnemoen 1457d378ed6SHao Wu static uint32_t npcm7xx_watchdog_timer_prescaler(const NPCM7xxWatchdogTimer *t) 1467d378ed6SHao Wu { 1477d378ed6SHao Wu switch (NPCM7XX_WTCR_WTCLK(t->wtcr)) { 1487d378ed6SHao Wu case 0: 1497d378ed6SHao Wu return 1; 1507d378ed6SHao Wu case 1: 1517d378ed6SHao Wu return 256; 1527d378ed6SHao Wu case 2: 1537d378ed6SHao Wu return 2048; 1547d378ed6SHao Wu case 3: 1557d378ed6SHao Wu return 65536; 1567d378ed6SHao Wu default: 1577d378ed6SHao Wu g_assert_not_reached(); 1587d378ed6SHao Wu } 1597d378ed6SHao Wu } 1607d378ed6SHao Wu 1617d378ed6SHao Wu static void npcm7xx_watchdog_timer_reset_cycles(NPCM7xxWatchdogTimer *t, 1627d378ed6SHao Wu int64_t cycles) 1637d378ed6SHao Wu { 164*0be12dc7SHao Wu int64_t ticks = cycles * npcm7xx_watchdog_timer_prescaler(t); 165*0be12dc7SHao Wu int64_t ns = clock_ticks_to_ns(t->ctrl->clock, ticks); 1667d378ed6SHao Wu 1677d378ed6SHao Wu /* 1687d378ed6SHao Wu * The reset function always clears the current timer. The caller of the 1697d378ed6SHao Wu * this needs to decide whether to start the watchdog timer based on 1707d378ed6SHao Wu * specific flag in WTCR. 1717d378ed6SHao Wu */ 1727d378ed6SHao Wu npcm7xx_timer_clear(&t->base_timer); 1737d378ed6SHao Wu 1747d378ed6SHao Wu t->base_timer.remaining_ns = ns; 1757d378ed6SHao Wu } 1767d378ed6SHao Wu 1777d378ed6SHao Wu static void npcm7xx_watchdog_timer_reset(NPCM7xxWatchdogTimer *t) 1787d378ed6SHao Wu { 1797d378ed6SHao Wu int64_t cycles = 1; 1807d378ed6SHao Wu uint32_t s = NPCM7XX_WTCR_WTIS(t->wtcr); 1817d378ed6SHao Wu 1827d378ed6SHao Wu g_assert(s <= 3); 1837d378ed6SHao Wu 1847d378ed6SHao Wu cycles <<= NPCM7XX_WATCHDOG_BASETIME_SHIFT; 1857d378ed6SHao Wu cycles <<= 2 * s; 1867d378ed6SHao Wu 1877d378ed6SHao Wu npcm7xx_watchdog_timer_reset_cycles(t, cycles); 1887d378ed6SHao Wu } 1897d378ed6SHao Wu 19085fdd74fSHavard Skinnemoen /* 19185fdd74fSHavard Skinnemoen * Raise the interrupt line if there's a pending interrupt and interrupts are 19285fdd74fSHavard Skinnemoen * enabled for this timer. If not, lower it. 19385fdd74fSHavard Skinnemoen */ 19485fdd74fSHavard Skinnemoen static void npcm7xx_timer_check_interrupt(NPCM7xxTimer *t) 19585fdd74fSHavard Skinnemoen { 19685fdd74fSHavard Skinnemoen NPCM7xxTimerCtrlState *tc = t->ctrl; 19785fdd74fSHavard Skinnemoen int index = npcm7xx_timer_index(tc, t); 19885fdd74fSHavard Skinnemoen bool pending = (t->tcsr & NPCM7XX_TCSR_IE) && (tc->tisr & BIT(index)); 19985fdd74fSHavard Skinnemoen 20085fdd74fSHavard Skinnemoen qemu_set_irq(t->irq, pending); 20185fdd74fSHavard Skinnemoen trace_npcm7xx_timer_irq(DEVICE(tc)->canonical_path, index, pending); 20285fdd74fSHavard Skinnemoen } 20385fdd74fSHavard Skinnemoen 20485fdd74fSHavard Skinnemoen /* 20585fdd74fSHavard Skinnemoen * Called when the counter reaches zero. Sets the interrupt flag, and either 20685fdd74fSHavard Skinnemoen * restarts or disables the timer. 20785fdd74fSHavard Skinnemoen */ 20885fdd74fSHavard Skinnemoen static void npcm7xx_timer_reached_zero(NPCM7xxTimer *t) 20985fdd74fSHavard Skinnemoen { 21085fdd74fSHavard Skinnemoen NPCM7xxTimerCtrlState *tc = t->ctrl; 21185fdd74fSHavard Skinnemoen int index = npcm7xx_timer_index(tc, t); 21285fdd74fSHavard Skinnemoen 21385fdd74fSHavard Skinnemoen tc->tisr |= BIT(index); 21485fdd74fSHavard Skinnemoen 21585fdd74fSHavard Skinnemoen if (t->tcsr & NPCM7XX_TCSR_PERIODIC) { 2167d378ed6SHao Wu t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr); 21785fdd74fSHavard Skinnemoen if (t->tcsr & NPCM7XX_TCSR_CEN) { 2187d378ed6SHao Wu npcm7xx_timer_start(&t->base_timer); 21985fdd74fSHavard Skinnemoen } 22085fdd74fSHavard Skinnemoen } else { 22185fdd74fSHavard Skinnemoen t->tcsr &= ~(NPCM7XX_TCSR_CEN | NPCM7XX_TCSR_CACT); 22285fdd74fSHavard Skinnemoen } 22385fdd74fSHavard Skinnemoen 22485fdd74fSHavard Skinnemoen npcm7xx_timer_check_interrupt(t); 22585fdd74fSHavard Skinnemoen } 22685fdd74fSHavard Skinnemoen 22785fdd74fSHavard Skinnemoen 22885fdd74fSHavard Skinnemoen /* 22985fdd74fSHavard Skinnemoen * Restart the timer from its initial value. If the timer was enabled and stays 23085fdd74fSHavard Skinnemoen * enabled, adjust the QEMU timer according to the new count. If the timer is 23185fdd74fSHavard Skinnemoen * transitioning from disabled to enabled, the caller is expected to start the 23285fdd74fSHavard Skinnemoen * timer later. 23385fdd74fSHavard Skinnemoen */ 23485fdd74fSHavard Skinnemoen static void npcm7xx_timer_restart(NPCM7xxTimer *t, uint32_t old_tcsr) 23585fdd74fSHavard Skinnemoen { 2367d378ed6SHao Wu t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, t->ticr); 23785fdd74fSHavard Skinnemoen 23885fdd74fSHavard Skinnemoen if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) { 2397d378ed6SHao Wu npcm7xx_timer_start(&t->base_timer); 24085fdd74fSHavard Skinnemoen } 24185fdd74fSHavard Skinnemoen } 24285fdd74fSHavard Skinnemoen 24385fdd74fSHavard Skinnemoen /* Register read and write handlers */ 24485fdd74fSHavard Skinnemoen 24585fdd74fSHavard Skinnemoen static uint32_t npcm7xx_timer_read_tdr(NPCM7xxTimer *t) 24685fdd74fSHavard Skinnemoen { 24785fdd74fSHavard Skinnemoen if (t->tcsr & NPCM7XX_TCSR_CEN) { 24885fdd74fSHavard Skinnemoen int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 24985fdd74fSHavard Skinnemoen 2507d378ed6SHao Wu return npcm7xx_timer_ns_to_count(t, t->base_timer.expires_ns - now); 25185fdd74fSHavard Skinnemoen } 25285fdd74fSHavard Skinnemoen 2537d378ed6SHao Wu return npcm7xx_timer_ns_to_count(t, t->base_timer.remaining_ns); 25485fdd74fSHavard Skinnemoen } 25585fdd74fSHavard Skinnemoen 25685fdd74fSHavard Skinnemoen static void npcm7xx_timer_write_tcsr(NPCM7xxTimer *t, uint32_t new_tcsr) 25785fdd74fSHavard Skinnemoen { 25885fdd74fSHavard Skinnemoen uint32_t old_tcsr = t->tcsr; 25985fdd74fSHavard Skinnemoen uint32_t tdr; 26085fdd74fSHavard Skinnemoen 26185fdd74fSHavard Skinnemoen if (new_tcsr & NPCM7XX_TCSR_RSVD) { 26285fdd74fSHavard Skinnemoen qemu_log_mask(LOG_GUEST_ERROR, "%s: reserved bits in 0x%08x ignored\n", 26385fdd74fSHavard Skinnemoen __func__, new_tcsr); 26485fdd74fSHavard Skinnemoen new_tcsr &= ~NPCM7XX_TCSR_RSVD; 26585fdd74fSHavard Skinnemoen } 26685fdd74fSHavard Skinnemoen if (new_tcsr & NPCM7XX_TCSR_CACT) { 26785fdd74fSHavard Skinnemoen qemu_log_mask(LOG_GUEST_ERROR, "%s: read-only bits in 0x%08x ignored\n", 26885fdd74fSHavard Skinnemoen __func__, new_tcsr); 26985fdd74fSHavard Skinnemoen new_tcsr &= ~NPCM7XX_TCSR_CACT; 27085fdd74fSHavard Skinnemoen } 27185fdd74fSHavard Skinnemoen if ((new_tcsr & NPCM7XX_TCSR_CRST) && (new_tcsr & NPCM7XX_TCSR_CEN)) { 27285fdd74fSHavard Skinnemoen qemu_log_mask(LOG_GUEST_ERROR, 27385fdd74fSHavard Skinnemoen "%s: both CRST and CEN set; ignoring CEN.\n", 27485fdd74fSHavard Skinnemoen __func__); 27585fdd74fSHavard Skinnemoen new_tcsr &= ~NPCM7XX_TCSR_CEN; 27685fdd74fSHavard Skinnemoen } 27785fdd74fSHavard Skinnemoen 27885fdd74fSHavard Skinnemoen /* Calculate the value of TDR before potentially changing the prescaler. */ 27985fdd74fSHavard Skinnemoen tdr = npcm7xx_timer_read_tdr(t); 28085fdd74fSHavard Skinnemoen 28185fdd74fSHavard Skinnemoen t->tcsr = (t->tcsr & NPCM7XX_TCSR_CACT) | new_tcsr; 28285fdd74fSHavard Skinnemoen 28385fdd74fSHavard Skinnemoen if (npcm7xx_tcsr_prescaler(old_tcsr) != npcm7xx_tcsr_prescaler(new_tcsr)) { 28485fdd74fSHavard Skinnemoen /* Recalculate time remaining based on the current TDR value. */ 2857d378ed6SHao Wu t->base_timer.remaining_ns = npcm7xx_timer_count_to_ns(t, tdr); 28685fdd74fSHavard Skinnemoen if (old_tcsr & t->tcsr & NPCM7XX_TCSR_CEN) { 2877d378ed6SHao Wu npcm7xx_timer_start(&t->base_timer); 28885fdd74fSHavard Skinnemoen } 28985fdd74fSHavard Skinnemoen } 29085fdd74fSHavard Skinnemoen 29185fdd74fSHavard Skinnemoen if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_IE) { 29285fdd74fSHavard Skinnemoen npcm7xx_timer_check_interrupt(t); 29385fdd74fSHavard Skinnemoen } 29485fdd74fSHavard Skinnemoen if (new_tcsr & NPCM7XX_TCSR_CRST) { 29585fdd74fSHavard Skinnemoen npcm7xx_timer_restart(t, old_tcsr); 29685fdd74fSHavard Skinnemoen t->tcsr &= ~NPCM7XX_TCSR_CRST; 29785fdd74fSHavard Skinnemoen } 29885fdd74fSHavard Skinnemoen if ((old_tcsr ^ new_tcsr) & NPCM7XX_TCSR_CEN) { 29985fdd74fSHavard Skinnemoen if (new_tcsr & NPCM7XX_TCSR_CEN) { 30085fdd74fSHavard Skinnemoen t->tcsr |= NPCM7XX_TCSR_CACT; 3017d378ed6SHao Wu npcm7xx_timer_start(&t->base_timer); 30285fdd74fSHavard Skinnemoen } else { 30385fdd74fSHavard Skinnemoen t->tcsr &= ~NPCM7XX_TCSR_CACT; 3047d378ed6SHao Wu npcm7xx_timer_pause(&t->base_timer); 3057d378ed6SHao Wu if (t->base_timer.remaining_ns <= 0) { 3062ac88848SHavard Skinnemoen npcm7xx_timer_reached_zero(t); 3072ac88848SHavard Skinnemoen } 30885fdd74fSHavard Skinnemoen } 30985fdd74fSHavard Skinnemoen } 31085fdd74fSHavard Skinnemoen } 31185fdd74fSHavard Skinnemoen 31285fdd74fSHavard Skinnemoen static void npcm7xx_timer_write_ticr(NPCM7xxTimer *t, uint32_t new_ticr) 31385fdd74fSHavard Skinnemoen { 31485fdd74fSHavard Skinnemoen t->ticr = new_ticr; 31585fdd74fSHavard Skinnemoen 31685fdd74fSHavard Skinnemoen npcm7xx_timer_restart(t, t->tcsr); 31785fdd74fSHavard Skinnemoen } 31885fdd74fSHavard Skinnemoen 31985fdd74fSHavard Skinnemoen static void npcm7xx_timer_write_tisr(NPCM7xxTimerCtrlState *s, uint32_t value) 32085fdd74fSHavard Skinnemoen { 32185fdd74fSHavard Skinnemoen int i; 32285fdd74fSHavard Skinnemoen 32385fdd74fSHavard Skinnemoen s->tisr &= ~value; 32485fdd74fSHavard Skinnemoen for (i = 0; i < ARRAY_SIZE(s->timer); i++) { 32585fdd74fSHavard Skinnemoen if (value & (1U << i)) { 32685fdd74fSHavard Skinnemoen npcm7xx_timer_check_interrupt(&s->timer[i]); 32785fdd74fSHavard Skinnemoen } 3287d378ed6SHao Wu 32985fdd74fSHavard Skinnemoen } 33085fdd74fSHavard Skinnemoen } 33185fdd74fSHavard Skinnemoen 3327d378ed6SHao Wu static void npcm7xx_timer_write_wtcr(NPCM7xxWatchdogTimer *t, uint32_t new_wtcr) 3337d378ed6SHao Wu { 3347d378ed6SHao Wu uint32_t old_wtcr = t->wtcr; 3357d378ed6SHao Wu 3367d378ed6SHao Wu /* 3377d378ed6SHao Wu * WTIF and WTRF are cleared by writing 1. Writing 0 makes these bits 3387d378ed6SHao Wu * unchanged. 3397d378ed6SHao Wu */ 3407d378ed6SHao Wu if (new_wtcr & NPCM7XX_WTCR_WTIF) { 3417d378ed6SHao Wu new_wtcr &= ~NPCM7XX_WTCR_WTIF; 3427d378ed6SHao Wu } else if (old_wtcr & NPCM7XX_WTCR_WTIF) { 3437d378ed6SHao Wu new_wtcr |= NPCM7XX_WTCR_WTIF; 3447d378ed6SHao Wu } 3457d378ed6SHao Wu if (new_wtcr & NPCM7XX_WTCR_WTRF) { 3467d378ed6SHao Wu new_wtcr &= ~NPCM7XX_WTCR_WTRF; 3477d378ed6SHao Wu } else if (old_wtcr & NPCM7XX_WTCR_WTRF) { 3487d378ed6SHao Wu new_wtcr |= NPCM7XX_WTCR_WTRF; 3497d378ed6SHao Wu } 3507d378ed6SHao Wu 3517d378ed6SHao Wu t->wtcr = new_wtcr; 3527d378ed6SHao Wu 3537d378ed6SHao Wu if (new_wtcr & NPCM7XX_WTCR_WTR) { 3547d378ed6SHao Wu t->wtcr &= ~NPCM7XX_WTCR_WTR; 3557d378ed6SHao Wu npcm7xx_watchdog_timer_reset(t); 3567d378ed6SHao Wu if (new_wtcr & NPCM7XX_WTCR_WTE) { 3577d378ed6SHao Wu npcm7xx_timer_start(&t->base_timer); 3587d378ed6SHao Wu } 3597d378ed6SHao Wu } else if ((old_wtcr ^ new_wtcr) & NPCM7XX_WTCR_WTE) { 3607d378ed6SHao Wu if (new_wtcr & NPCM7XX_WTCR_WTE) { 3617d378ed6SHao Wu npcm7xx_timer_start(&t->base_timer); 3627d378ed6SHao Wu } else { 3637d378ed6SHao Wu npcm7xx_timer_pause(&t->base_timer); 3647d378ed6SHao Wu } 3657d378ed6SHao Wu } 3667d378ed6SHao Wu 3677d378ed6SHao Wu } 3687d378ed6SHao Wu 36985fdd74fSHavard Skinnemoen static hwaddr npcm7xx_tcsr_index(hwaddr reg) 37085fdd74fSHavard Skinnemoen { 37185fdd74fSHavard Skinnemoen switch (reg) { 37285fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR0: 37385fdd74fSHavard Skinnemoen return 0; 37485fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR1: 37585fdd74fSHavard Skinnemoen return 1; 37685fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR2: 37785fdd74fSHavard Skinnemoen return 2; 37885fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR3: 37985fdd74fSHavard Skinnemoen return 3; 38085fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR4: 38185fdd74fSHavard Skinnemoen return 4; 38285fdd74fSHavard Skinnemoen default: 38385fdd74fSHavard Skinnemoen g_assert_not_reached(); 38485fdd74fSHavard Skinnemoen } 38585fdd74fSHavard Skinnemoen } 38685fdd74fSHavard Skinnemoen 38785fdd74fSHavard Skinnemoen static hwaddr npcm7xx_ticr_index(hwaddr reg) 38885fdd74fSHavard Skinnemoen { 38985fdd74fSHavard Skinnemoen switch (reg) { 39085fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR0: 39185fdd74fSHavard Skinnemoen return 0; 39285fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR1: 39385fdd74fSHavard Skinnemoen return 1; 39485fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR2: 39585fdd74fSHavard Skinnemoen return 2; 39685fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR3: 39785fdd74fSHavard Skinnemoen return 3; 39885fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR4: 39985fdd74fSHavard Skinnemoen return 4; 40085fdd74fSHavard Skinnemoen default: 40185fdd74fSHavard Skinnemoen g_assert_not_reached(); 40285fdd74fSHavard Skinnemoen } 40385fdd74fSHavard Skinnemoen } 40485fdd74fSHavard Skinnemoen 40585fdd74fSHavard Skinnemoen static hwaddr npcm7xx_tdr_index(hwaddr reg) 40685fdd74fSHavard Skinnemoen { 40785fdd74fSHavard Skinnemoen switch (reg) { 40885fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR0: 40985fdd74fSHavard Skinnemoen return 0; 41085fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR1: 41185fdd74fSHavard Skinnemoen return 1; 41285fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR2: 41385fdd74fSHavard Skinnemoen return 2; 41485fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR3: 41585fdd74fSHavard Skinnemoen return 3; 41685fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR4: 41785fdd74fSHavard Skinnemoen return 4; 41885fdd74fSHavard Skinnemoen default: 41985fdd74fSHavard Skinnemoen g_assert_not_reached(); 42085fdd74fSHavard Skinnemoen } 42185fdd74fSHavard Skinnemoen } 42285fdd74fSHavard Skinnemoen 42385fdd74fSHavard Skinnemoen static uint64_t npcm7xx_timer_read(void *opaque, hwaddr offset, unsigned size) 42485fdd74fSHavard Skinnemoen { 42585fdd74fSHavard Skinnemoen NPCM7xxTimerCtrlState *s = opaque; 42685fdd74fSHavard Skinnemoen uint64_t value = 0; 42785fdd74fSHavard Skinnemoen hwaddr reg; 42885fdd74fSHavard Skinnemoen 42985fdd74fSHavard Skinnemoen reg = offset / sizeof(uint32_t); 43085fdd74fSHavard Skinnemoen switch (reg) { 43185fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR0: 43285fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR1: 43385fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR2: 43485fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR3: 43585fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR4: 43685fdd74fSHavard Skinnemoen value = s->timer[npcm7xx_tcsr_index(reg)].tcsr; 43785fdd74fSHavard Skinnemoen break; 43885fdd74fSHavard Skinnemoen 43985fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR0: 44085fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR1: 44185fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR2: 44285fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR3: 44385fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR4: 44485fdd74fSHavard Skinnemoen value = s->timer[npcm7xx_ticr_index(reg)].ticr; 44585fdd74fSHavard Skinnemoen break; 44685fdd74fSHavard Skinnemoen 44785fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR0: 44885fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR1: 44985fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR2: 45085fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR3: 45185fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR4: 45285fdd74fSHavard Skinnemoen value = npcm7xx_timer_read_tdr(&s->timer[npcm7xx_tdr_index(reg)]); 45385fdd74fSHavard Skinnemoen break; 45485fdd74fSHavard Skinnemoen 45585fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TISR: 45685fdd74fSHavard Skinnemoen value = s->tisr; 45785fdd74fSHavard Skinnemoen break; 45885fdd74fSHavard Skinnemoen 45985fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_WTCR: 4607d378ed6SHao Wu value = s->watchdog_timer.wtcr; 46185fdd74fSHavard Skinnemoen break; 46285fdd74fSHavard Skinnemoen 46385fdd74fSHavard Skinnemoen default: 46485fdd74fSHavard Skinnemoen qemu_log_mask(LOG_GUEST_ERROR, 46585fdd74fSHavard Skinnemoen "%s: invalid offset 0x%04" HWADDR_PRIx "\n", 46685fdd74fSHavard Skinnemoen __func__, offset); 46785fdd74fSHavard Skinnemoen break; 46885fdd74fSHavard Skinnemoen } 46985fdd74fSHavard Skinnemoen 47085fdd74fSHavard Skinnemoen trace_npcm7xx_timer_read(DEVICE(s)->canonical_path, offset, value); 47185fdd74fSHavard Skinnemoen 47285fdd74fSHavard Skinnemoen return value; 47385fdd74fSHavard Skinnemoen } 47485fdd74fSHavard Skinnemoen 47585fdd74fSHavard Skinnemoen static void npcm7xx_timer_write(void *opaque, hwaddr offset, 47685fdd74fSHavard Skinnemoen uint64_t v, unsigned size) 47785fdd74fSHavard Skinnemoen { 47885fdd74fSHavard Skinnemoen uint32_t reg = offset / sizeof(uint32_t); 47985fdd74fSHavard Skinnemoen NPCM7xxTimerCtrlState *s = opaque; 48085fdd74fSHavard Skinnemoen uint32_t value = v; 48185fdd74fSHavard Skinnemoen 48285fdd74fSHavard Skinnemoen trace_npcm7xx_timer_write(DEVICE(s)->canonical_path, offset, value); 48385fdd74fSHavard Skinnemoen 48485fdd74fSHavard Skinnemoen switch (reg) { 48585fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR0: 48685fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR1: 48785fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR2: 48885fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR3: 48985fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TCSR4: 49085fdd74fSHavard Skinnemoen npcm7xx_timer_write_tcsr(&s->timer[npcm7xx_tcsr_index(reg)], value); 49185fdd74fSHavard Skinnemoen return; 49285fdd74fSHavard Skinnemoen 49385fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR0: 49485fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR1: 49585fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR2: 49685fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR3: 49785fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TICR4: 49885fdd74fSHavard Skinnemoen npcm7xx_timer_write_ticr(&s->timer[npcm7xx_ticr_index(reg)], value); 49985fdd74fSHavard Skinnemoen return; 50085fdd74fSHavard Skinnemoen 50185fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR0: 50285fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR1: 50385fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR2: 50485fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR3: 50585fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TDR4: 50685fdd74fSHavard Skinnemoen qemu_log_mask(LOG_GUEST_ERROR, 50785fdd74fSHavard Skinnemoen "%s: register @ 0x%04" HWADDR_PRIx " is read-only\n", 50885fdd74fSHavard Skinnemoen __func__, offset); 50985fdd74fSHavard Skinnemoen return; 51085fdd74fSHavard Skinnemoen 51185fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_TISR: 51285fdd74fSHavard Skinnemoen npcm7xx_timer_write_tisr(s, value); 51385fdd74fSHavard Skinnemoen return; 51485fdd74fSHavard Skinnemoen 51585fdd74fSHavard Skinnemoen case NPCM7XX_TIMER_WTCR: 5167d378ed6SHao Wu npcm7xx_timer_write_wtcr(&s->watchdog_timer, value); 51785fdd74fSHavard Skinnemoen return; 51885fdd74fSHavard Skinnemoen } 51985fdd74fSHavard Skinnemoen 52085fdd74fSHavard Skinnemoen qemu_log_mask(LOG_GUEST_ERROR, 52185fdd74fSHavard Skinnemoen "%s: invalid offset 0x%04" HWADDR_PRIx "\n", 52285fdd74fSHavard Skinnemoen __func__, offset); 52385fdd74fSHavard Skinnemoen } 52485fdd74fSHavard Skinnemoen 52585fdd74fSHavard Skinnemoen static const struct MemoryRegionOps npcm7xx_timer_ops = { 52685fdd74fSHavard Skinnemoen .read = npcm7xx_timer_read, 52785fdd74fSHavard Skinnemoen .write = npcm7xx_timer_write, 52885fdd74fSHavard Skinnemoen .endianness = DEVICE_LITTLE_ENDIAN, 52985fdd74fSHavard Skinnemoen .valid = { 53085fdd74fSHavard Skinnemoen .min_access_size = 4, 53185fdd74fSHavard Skinnemoen .max_access_size = 4, 53285fdd74fSHavard Skinnemoen .unaligned = false, 53385fdd74fSHavard Skinnemoen }, 53485fdd74fSHavard Skinnemoen }; 53585fdd74fSHavard Skinnemoen 53685fdd74fSHavard Skinnemoen /* Called when the QEMU timer expires. */ 53785fdd74fSHavard Skinnemoen static void npcm7xx_timer_expired(void *opaque) 53885fdd74fSHavard Skinnemoen { 53985fdd74fSHavard Skinnemoen NPCM7xxTimer *t = opaque; 54085fdd74fSHavard Skinnemoen 54185fdd74fSHavard Skinnemoen if (t->tcsr & NPCM7XX_TCSR_CEN) { 54285fdd74fSHavard Skinnemoen npcm7xx_timer_reached_zero(t); 54385fdd74fSHavard Skinnemoen } 54485fdd74fSHavard Skinnemoen } 54585fdd74fSHavard Skinnemoen 54685fdd74fSHavard Skinnemoen static void npcm7xx_timer_enter_reset(Object *obj, ResetType type) 54785fdd74fSHavard Skinnemoen { 54885fdd74fSHavard Skinnemoen NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); 54985fdd74fSHavard Skinnemoen int i; 55085fdd74fSHavard Skinnemoen 55185fdd74fSHavard Skinnemoen for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) { 55285fdd74fSHavard Skinnemoen NPCM7xxTimer *t = &s->timer[i]; 55385fdd74fSHavard Skinnemoen 5547d378ed6SHao Wu npcm7xx_timer_clear(&t->base_timer); 55585fdd74fSHavard Skinnemoen t->tcsr = 0x00000005; 55685fdd74fSHavard Skinnemoen t->ticr = 0x00000000; 55785fdd74fSHavard Skinnemoen } 55885fdd74fSHavard Skinnemoen 55985fdd74fSHavard Skinnemoen s->tisr = 0x00000000; 5607d378ed6SHao Wu /* 5617d378ed6SHao Wu * Set WTCLK to 1(default) and reset all flags except WTRF. 5627d378ed6SHao Wu * WTRF is not reset during a core domain reset. 5637d378ed6SHao Wu */ 5647d378ed6SHao Wu s->watchdog_timer.wtcr = 0x00000400 | (s->watchdog_timer.wtcr & 5657d378ed6SHao Wu NPCM7XX_WTCR_WTRF); 5667d378ed6SHao Wu } 5677d378ed6SHao Wu 5687d378ed6SHao Wu static void npcm7xx_watchdog_timer_expired(void *opaque) 5697d378ed6SHao Wu { 5707d378ed6SHao Wu NPCM7xxWatchdogTimer *t = opaque; 5717d378ed6SHao Wu 5727d378ed6SHao Wu if (t->wtcr & NPCM7XX_WTCR_WTE) { 5737d378ed6SHao Wu if (t->wtcr & NPCM7XX_WTCR_WTIF) { 5747d378ed6SHao Wu if (t->wtcr & NPCM7XX_WTCR_WTRE) { 5757d378ed6SHao Wu t->wtcr |= NPCM7XX_WTCR_WTRF; 5767d378ed6SHao Wu /* send reset signal to CLK module*/ 5777d378ed6SHao Wu qemu_irq_raise(t->reset_signal); 5787d378ed6SHao Wu } 5797d378ed6SHao Wu } else { 5807d378ed6SHao Wu t->wtcr |= NPCM7XX_WTCR_WTIF; 5817d378ed6SHao Wu if (t->wtcr & NPCM7XX_WTCR_WTIE) { 5827d378ed6SHao Wu /* send interrupt */ 5837d378ed6SHao Wu qemu_irq_raise(t->irq); 5847d378ed6SHao Wu } 5857d378ed6SHao Wu npcm7xx_watchdog_timer_reset_cycles(t, 5867d378ed6SHao Wu NPCM7XX_WATCHDOG_INTERRUPT_TO_RESET_CYCLES); 5877d378ed6SHao Wu npcm7xx_timer_start(&t->base_timer); 5887d378ed6SHao Wu } 5897d378ed6SHao Wu } 59085fdd74fSHavard Skinnemoen } 59185fdd74fSHavard Skinnemoen 59285fdd74fSHavard Skinnemoen static void npcm7xx_timer_hold_reset(Object *obj) 59385fdd74fSHavard Skinnemoen { 59485fdd74fSHavard Skinnemoen NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); 59585fdd74fSHavard Skinnemoen int i; 59685fdd74fSHavard Skinnemoen 59785fdd74fSHavard Skinnemoen for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) { 59885fdd74fSHavard Skinnemoen qemu_irq_lower(s->timer[i].irq); 59985fdd74fSHavard Skinnemoen } 6007d378ed6SHao Wu qemu_irq_lower(s->watchdog_timer.irq); 60185fdd74fSHavard Skinnemoen } 60285fdd74fSHavard Skinnemoen 603*0be12dc7SHao Wu static void npcm7xx_timer_init(Object *obj) 60485fdd74fSHavard Skinnemoen { 605*0be12dc7SHao Wu NPCM7xxTimerCtrlState *s = NPCM7XX_TIMER(obj); 606*0be12dc7SHao Wu DeviceState *dev = DEVICE(obj); 607*0be12dc7SHao Wu SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 60885fdd74fSHavard Skinnemoen int i; 6097d378ed6SHao Wu NPCM7xxWatchdogTimer *w; 61085fdd74fSHavard Skinnemoen 61185fdd74fSHavard Skinnemoen for (i = 0; i < NPCM7XX_TIMERS_PER_CTRL; i++) { 61285fdd74fSHavard Skinnemoen NPCM7xxTimer *t = &s->timer[i]; 61385fdd74fSHavard Skinnemoen t->ctrl = s; 6147d378ed6SHao Wu timer_init_ns(&t->base_timer.qtimer, QEMU_CLOCK_VIRTUAL, 6157d378ed6SHao Wu npcm7xx_timer_expired, t); 61685fdd74fSHavard Skinnemoen sysbus_init_irq(sbd, &t->irq); 61785fdd74fSHavard Skinnemoen } 61885fdd74fSHavard Skinnemoen 6197d378ed6SHao Wu w = &s->watchdog_timer; 6207d378ed6SHao Wu w->ctrl = s; 6217d378ed6SHao Wu timer_init_ns(&w->base_timer.qtimer, QEMU_CLOCK_VIRTUAL, 6227d378ed6SHao Wu npcm7xx_watchdog_timer_expired, w); 6237d378ed6SHao Wu sysbus_init_irq(sbd, &w->irq); 6247d378ed6SHao Wu 625*0be12dc7SHao Wu memory_region_init_io(&s->iomem, obj, &npcm7xx_timer_ops, s, 62685fdd74fSHavard Skinnemoen TYPE_NPCM7XX_TIMER, 4 * KiB); 62785fdd74fSHavard Skinnemoen sysbus_init_mmio(sbd, &s->iomem); 6287d378ed6SHao Wu qdev_init_gpio_out_named(dev, &w->reset_signal, 6297d378ed6SHao Wu NPCM7XX_WATCHDOG_RESET_GPIO_OUT, 1); 630*0be12dc7SHao Wu s->clock = qdev_init_clock_in(dev, "clock", NULL, NULL); 63185fdd74fSHavard Skinnemoen } 63285fdd74fSHavard Skinnemoen 6337d378ed6SHao Wu static const VMStateDescription vmstate_npcm7xx_base_timer = { 6347d378ed6SHao Wu .name = "npcm7xx-base-timer", 63585fdd74fSHavard Skinnemoen .version_id = 0, 63685fdd74fSHavard Skinnemoen .minimum_version_id = 0, 63785fdd74fSHavard Skinnemoen .fields = (VMStateField[]) { 6387d378ed6SHao Wu VMSTATE_TIMER(qtimer, NPCM7xxBaseTimer), 6397d378ed6SHao Wu VMSTATE_INT64(expires_ns, NPCM7xxBaseTimer), 6407d378ed6SHao Wu VMSTATE_INT64(remaining_ns, NPCM7xxBaseTimer), 6417d378ed6SHao Wu VMSTATE_END_OF_LIST(), 6427d378ed6SHao Wu }, 6437d378ed6SHao Wu }; 6447d378ed6SHao Wu 6457d378ed6SHao Wu static const VMStateDescription vmstate_npcm7xx_timer = { 6467d378ed6SHao Wu .name = "npcm7xx-timer", 6477d378ed6SHao Wu .version_id = 1, 6487d378ed6SHao Wu .minimum_version_id = 1, 6497d378ed6SHao Wu .fields = (VMStateField[]) { 6507d378ed6SHao Wu VMSTATE_STRUCT(base_timer, NPCM7xxTimer, 6517d378ed6SHao Wu 0, vmstate_npcm7xx_base_timer, 6527d378ed6SHao Wu NPCM7xxBaseTimer), 65385fdd74fSHavard Skinnemoen VMSTATE_UINT32(tcsr, NPCM7xxTimer), 65485fdd74fSHavard Skinnemoen VMSTATE_UINT32(ticr, NPCM7xxTimer), 65585fdd74fSHavard Skinnemoen VMSTATE_END_OF_LIST(), 65685fdd74fSHavard Skinnemoen }, 65785fdd74fSHavard Skinnemoen }; 65885fdd74fSHavard Skinnemoen 6597d378ed6SHao Wu static const VMStateDescription vmstate_npcm7xx_watchdog_timer = { 6607d378ed6SHao Wu .name = "npcm7xx-watchdog-timer", 66185fdd74fSHavard Skinnemoen .version_id = 0, 66285fdd74fSHavard Skinnemoen .minimum_version_id = 0, 66385fdd74fSHavard Skinnemoen .fields = (VMStateField[]) { 6647d378ed6SHao Wu VMSTATE_STRUCT(base_timer, NPCM7xxWatchdogTimer, 6657d378ed6SHao Wu 0, vmstate_npcm7xx_base_timer, 6667d378ed6SHao Wu NPCM7xxBaseTimer), 6677d378ed6SHao Wu VMSTATE_UINT32(wtcr, NPCM7xxWatchdogTimer), 6687d378ed6SHao Wu VMSTATE_END_OF_LIST(), 6697d378ed6SHao Wu }, 6707d378ed6SHao Wu }; 6717d378ed6SHao Wu 6727d378ed6SHao Wu static const VMStateDescription vmstate_npcm7xx_timer_ctrl = { 6737d378ed6SHao Wu .name = "npcm7xx-timer-ctrl", 674*0be12dc7SHao Wu .version_id = 2, 675*0be12dc7SHao Wu .minimum_version_id = 2, 6767d378ed6SHao Wu .fields = (VMStateField[]) { 67785fdd74fSHavard Skinnemoen VMSTATE_UINT32(tisr, NPCM7xxTimerCtrlState), 678*0be12dc7SHao Wu VMSTATE_CLOCK(clock, NPCM7xxTimerCtrlState), 67985fdd74fSHavard Skinnemoen VMSTATE_STRUCT_ARRAY(timer, NPCM7xxTimerCtrlState, 68085fdd74fSHavard Skinnemoen NPCM7XX_TIMERS_PER_CTRL, 0, vmstate_npcm7xx_timer, 68185fdd74fSHavard Skinnemoen NPCM7xxTimer), 6827d378ed6SHao Wu VMSTATE_STRUCT(watchdog_timer, NPCM7xxTimerCtrlState, 6837d378ed6SHao Wu 0, vmstate_npcm7xx_watchdog_timer, 6847d378ed6SHao Wu NPCM7xxWatchdogTimer), 68585fdd74fSHavard Skinnemoen VMSTATE_END_OF_LIST(), 68685fdd74fSHavard Skinnemoen }, 68785fdd74fSHavard Skinnemoen }; 68885fdd74fSHavard Skinnemoen 68985fdd74fSHavard Skinnemoen static void npcm7xx_timer_class_init(ObjectClass *klass, void *data) 69085fdd74fSHavard Skinnemoen { 69185fdd74fSHavard Skinnemoen ResettableClass *rc = RESETTABLE_CLASS(klass); 69285fdd74fSHavard Skinnemoen DeviceClass *dc = DEVICE_CLASS(klass); 69385fdd74fSHavard Skinnemoen 69485fdd74fSHavard Skinnemoen QEMU_BUILD_BUG_ON(NPCM7XX_TIMER_REGS_END > NPCM7XX_TIMER_NR_REGS); 69585fdd74fSHavard Skinnemoen 69685fdd74fSHavard Skinnemoen dc->desc = "NPCM7xx Timer Controller"; 69785fdd74fSHavard Skinnemoen dc->vmsd = &vmstate_npcm7xx_timer_ctrl; 69885fdd74fSHavard Skinnemoen rc->phases.enter = npcm7xx_timer_enter_reset; 69985fdd74fSHavard Skinnemoen rc->phases.hold = npcm7xx_timer_hold_reset; 70085fdd74fSHavard Skinnemoen } 70185fdd74fSHavard Skinnemoen 70285fdd74fSHavard Skinnemoen static const TypeInfo npcm7xx_timer_info = { 70385fdd74fSHavard Skinnemoen .name = TYPE_NPCM7XX_TIMER, 70485fdd74fSHavard Skinnemoen .parent = TYPE_SYS_BUS_DEVICE, 70585fdd74fSHavard Skinnemoen .instance_size = sizeof(NPCM7xxTimerCtrlState), 70685fdd74fSHavard Skinnemoen .class_init = npcm7xx_timer_class_init, 707*0be12dc7SHao Wu .instance_init = npcm7xx_timer_init, 70885fdd74fSHavard Skinnemoen }; 70985fdd74fSHavard Skinnemoen 71085fdd74fSHavard Skinnemoen static void npcm7xx_timer_register_type(void) 71185fdd74fSHavard Skinnemoen { 71285fdd74fSHavard Skinnemoen type_register_static(&npcm7xx_timer_info); 71385fdd74fSHavard Skinnemoen } 71485fdd74fSHavard Skinnemoen type_init(npcm7xx_timer_register_type); 715