xref: /qemu/hw/timer/sh_timer.c (revision 22138965) 
1 /*
2  * SuperH Timer modules.
3  *
4  * Copyright (c) 2007 Magnus Damm
5  * Based on arm_timer.c by Paul Brook
6  * Copyright (c) 2005-2006 CodeSourcery.
7  *
8  * This code is licensed under the GPL.
9  */
10 
11 #include "qemu/osdep.h"
12 #include "exec/memory.h"
13 #include "hw/hw.h"
14 #include "hw/irq.h"
15 #include "hw/sh4/sh.h"
16 #include "hw/timer/tmu012.h"
17 #include "hw/ptimer.h"
18 
19 //#define DEBUG_TIMER
20 
21 #define TIMER_TCR_TPSC          (7 << 0)
22 #define TIMER_TCR_CKEG          (3 << 3)
23 #define TIMER_TCR_UNIE          (1 << 5)
24 #define TIMER_TCR_ICPE          (3 << 6)
25 #define TIMER_TCR_UNF           (1 << 8)
26 #define TIMER_TCR_ICPF          (1 << 9)
27 #define TIMER_TCR_RESERVED      (0x3f << 10)
28 
29 #define TIMER_FEAT_CAPT   (1 << 0)
30 #define TIMER_FEAT_EXTCLK (1 << 1)
31 
32 #define OFFSET_TCOR   0
33 #define OFFSET_TCNT   1
34 #define OFFSET_TCR    2
35 #define OFFSET_TCPR   3
36 
37 typedef struct {
38     ptimer_state *timer;
39     uint32_t tcnt;
40     uint32_t tcor;
41     uint32_t tcr;
42     uint32_t tcpr;
43     int freq;
44     int int_level;
45     int old_level;
46     int feat;
47     int enabled;
48     qemu_irq irq;
49 } sh_timer_state;
50 
51 /* Check all active timers, and schedule the next timer interrupt. */
52 
53 static void sh_timer_update(sh_timer_state *s)
54 {
55     int new_level = s->int_level && (s->tcr & TIMER_TCR_UNIE);
56 
57     if (new_level != s->old_level)
58       qemu_set_irq (s->irq, new_level);
59 
60     s->old_level = s->int_level;
61     s->int_level = new_level;
62 }
63 
64 static uint32_t sh_timer_read(void *opaque, hwaddr offset)
65 {
66     sh_timer_state *s = (sh_timer_state *)opaque;
67 
68     switch (offset >> 2) {
69     case OFFSET_TCOR:
70         return s->tcor;
71     case OFFSET_TCNT:
72         return ptimer_get_count(s->timer);
73     case OFFSET_TCR:
74         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
75     case OFFSET_TCPR:
76         if (s->feat & TIMER_FEAT_CAPT)
77             return s->tcpr;
78         /* fall through */
79     default:
80         hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
81         return 0;
82     }
83 }
84 
85 static void sh_timer_write(void *opaque, hwaddr offset,
86                             uint32_t value)
87 {
88     sh_timer_state *s = (sh_timer_state *)opaque;
89     int freq;
90 
91     switch (offset >> 2) {
92     case OFFSET_TCOR:
93         s->tcor = value;
94         ptimer_transaction_begin(s->timer);
95         ptimer_set_limit(s->timer, s->tcor, 0);
96         ptimer_transaction_commit(s->timer);
97         break;
98     case OFFSET_TCNT:
99         s->tcnt = value;
100         ptimer_transaction_begin(s->timer);
101         ptimer_set_count(s->timer, s->tcnt);
102         ptimer_transaction_commit(s->timer);
103         break;
104     case OFFSET_TCR:
105         ptimer_transaction_begin(s->timer);
106         if (s->enabled) {
107             /*
108              * Pause the timer if it is running. This may cause some inaccuracy
109              * dure to rounding, but avoids a whole lot of other messyness
110              */
111             ptimer_stop(s->timer);
112         }
113         freq = s->freq;
114         /* ??? Need to recalculate expiry time after changing divisor.  */
115         switch (value & TIMER_TCR_TPSC) {
116         case 0: freq >>= 2; break;
117         case 1: freq >>= 4; break;
118         case 2: freq >>= 6; break;
119         case 3: freq >>= 8; break;
120         case 4: freq >>= 10; break;
121         case 6:
122         case 7:
123             if (s->feat & TIMER_FEAT_EXTCLK) {
124                 break;
125             }
126             /* fallthrough */
127         default:
128             hw_error("sh_timer_write: Reserved TPSC value\n");
129         }
130         switch ((value & TIMER_TCR_CKEG) >> 3) {
131         case 0:
132             break;
133         case 1:
134         case 2:
135         case 3:
136             if (s->feat & TIMER_FEAT_EXTCLK) {
137                 break;
138             }
139             /* fallthrough */
140         default:
141             hw_error("sh_timer_write: Reserved CKEG value\n");
142         }
143         switch ((value & TIMER_TCR_ICPE) >> 6) {
144         case 0:
145             break;
146         case 2:
147         case 3:
148             if (s->feat & TIMER_FEAT_CAPT) {
149                 break;
150             }
151             /* fallthrough */
152         default:
153             hw_error("sh_timer_write: Reserved ICPE value\n");
154         }
155         if ((value & TIMER_TCR_UNF) == 0) {
156             s->int_level = 0;
157         }
158 
159         value &= ~TIMER_TCR_UNF;
160 
161         if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT))) {
162             hw_error("sh_timer_write: Reserved ICPF value\n");
163         }
164 
165         value &= ~TIMER_TCR_ICPF; /* capture not supported */
166 
167         if (value & TIMER_TCR_RESERVED) {
168             hw_error("sh_timer_write: Reserved TCR bits set\n");
169         }
170         s->tcr = value;
171         ptimer_set_limit(s->timer, s->tcor, 0);
172         ptimer_set_freq(s->timer, freq);
173         if (s->enabled) {
174             /* Restart the timer if still enabled.  */
175             ptimer_run(s->timer, 0);
176         }
177         ptimer_transaction_commit(s->timer);
178         break;
179     case OFFSET_TCPR:
180         if (s->feat & TIMER_FEAT_CAPT) {
181             s->tcpr = value;
182             break;
183         }
184         /* fallthrough */
185     default:
186         hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
187     }
188     sh_timer_update(s);
189 }
190 
191 static void sh_timer_start_stop(void *opaque, int enable)
192 {
193     sh_timer_state *s = (sh_timer_state *)opaque;
194 
195 #ifdef DEBUG_TIMER
196     printf("sh_timer_start_stop %d (%d)\n", enable, s->enabled);
197 #endif
198 
199     ptimer_transaction_begin(s->timer);
200     if (s->enabled && !enable) {
201         ptimer_stop(s->timer);
202     }
203     if (!s->enabled && enable) {
204         ptimer_run(s->timer, 0);
205     }
206     ptimer_transaction_commit(s->timer);
207     s->enabled = !!enable;
208 
209 #ifdef DEBUG_TIMER
210     printf("sh_timer_start_stop done %d\n", s->enabled);
211 #endif
212 }
213 
214 static void sh_timer_tick(void *opaque)
215 {
216     sh_timer_state *s = (sh_timer_state *)opaque;
217     s->int_level = s->enabled;
218     sh_timer_update(s);
219 }
220 
221 static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
222 {
223     sh_timer_state *s;
224 
225     s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
226     s->freq = freq;
227     s->feat = feat;
228     s->tcor = 0xffffffff;
229     s->tcnt = 0xffffffff;
230     s->tcpr = 0xdeadbeef;
231     s->tcr = 0;
232     s->enabled = 0;
233     s->irq = irq;
234 
235     s->timer = ptimer_init(sh_timer_tick, s, PTIMER_POLICY_DEFAULT);
236 
237     sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
238     sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
239     sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
240     sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
241     /* ??? Save/restore.  */
242     return s;
243 }
244 
245 typedef struct {
246     MemoryRegion iomem;
247     MemoryRegion iomem_p4;
248     MemoryRegion iomem_a7;
249     void *timer[3];
250     int level[3];
251     uint32_t tocr;
252     uint32_t tstr;
253     int feat;
254 } tmu012_state;
255 
256 static uint64_t tmu012_read(void *opaque, hwaddr offset,
257                             unsigned size)
258 {
259     tmu012_state *s = (tmu012_state *)opaque;
260 
261 #ifdef DEBUG_TIMER
262     printf("tmu012_read 0x%lx\n", (unsigned long) offset);
263 #endif
264 
265     if (offset >= 0x20) {
266         if (!(s->feat & TMU012_FEAT_3CHAN)) {
267             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
268         }
269         return sh_timer_read(s->timer[2], offset - 0x20);
270     }
271 
272     if (offset >= 0x14)
273         return sh_timer_read(s->timer[1], offset - 0x14);
274 
275     if (offset >= 0x08)
276         return sh_timer_read(s->timer[0], offset - 0x08);
277 
278     if (offset == 4)
279         return s->tstr;
280 
281     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
282         return s->tocr;
283 
284     hw_error("tmu012_write: Bad offset %x\n", (int)offset);
285     return 0;
286 }
287 
288 static void tmu012_write(void *opaque, hwaddr offset,
289                         uint64_t value, unsigned size)
290 {
291     tmu012_state *s = (tmu012_state *)opaque;
292 
293 #ifdef DEBUG_TIMER
294     printf("tmu012_write 0x%lx 0x%08x\n", (unsigned long) offset, value);
295 #endif
296 
297     if (offset >= 0x20) {
298         if (!(s->feat & TMU012_FEAT_3CHAN)) {
299             hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
300         }
301         sh_timer_write(s->timer[2], offset - 0x20, value);
302         return;
303     }
304 
305     if (offset >= 0x14) {
306         sh_timer_write(s->timer[1], offset - 0x14, value);
307         return;
308     }
309 
310     if (offset >= 0x08) {
311         sh_timer_write(s->timer[0], offset - 0x08, value);
312         return;
313     }
314 
315     if (offset == 4) {
316         sh_timer_start_stop(s->timer[0], value & (1 << 0));
317         sh_timer_start_stop(s->timer[1], value & (1 << 1));
318         if (s->feat & TMU012_FEAT_3CHAN) {
319             sh_timer_start_stop(s->timer[2], value & (1 << 2));
320         } else {
321             if (value & (1 << 2)) {
322                 hw_error("tmu012_write: Bad channel\n");
323             }
324         }
325 
326         s->tstr = value;
327         return;
328     }
329 
330     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0) {
331         s->tocr = value & (1 << 0);
332     }
333 }
334 
335 static const MemoryRegionOps tmu012_ops = {
336     .read = tmu012_read,
337     .write = tmu012_write,
338     .endianness = DEVICE_NATIVE_ENDIAN,
339 };
340 
341 void tmu012_init(MemoryRegion *sysmem, hwaddr base,
342                  int feat, uint32_t freq,
343                  qemu_irq ch0_irq, qemu_irq ch1_irq,
344                  qemu_irq ch2_irq0, qemu_irq ch2_irq1)
345 {
346     tmu012_state *s;
347     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
348 
349     s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
350     s->feat = feat;
351     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
352     s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
353     if (feat & TMU012_FEAT_3CHAN) {
354         s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
355                                     ch2_irq0); /* ch2_irq1 not supported */
356     }
357 
358     memory_region_init_io(&s->iomem, NULL, &tmu012_ops, s,
359                           "timer", 0x100000000ULL);
360 
361     memory_region_init_alias(&s->iomem_p4, NULL, "timer-p4",
362                              &s->iomem, 0, 0x1000);
363     memory_region_add_subregion(sysmem, P4ADDR(base), &s->iomem_p4);
364 
365     memory_region_init_alias(&s->iomem_a7, NULL, "timer-a7",
366                              &s->iomem, 0, 0x1000);
367     memory_region_add_subregion(sysmem, A7ADDR(base), &s->iomem_a7);
368     /* ??? Save/restore.  */
369 }
370