1 /* 2 * STM32F2XX Timer 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/timer/stm32f2xx_timer.h" 27 28 #ifndef STM_TIMER_ERR_DEBUG 29 #define STM_TIMER_ERR_DEBUG 0 30 #endif 31 32 #define DB_PRINT_L(lvl, fmt, args...) do { \ 33 if (STM_TIMER_ERR_DEBUG >= lvl) { \ 34 qemu_log("%s: " fmt, __func__, ## args); \ 35 } \ 36 } while (0); 37 38 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 39 40 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now); 41 42 static void stm32f2xx_timer_interrupt(void *opaque) 43 { 44 STM32F2XXTimerState *s = opaque; 45 46 DB_PRINT("Interrupt\n"); 47 48 if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { 49 s->tim_sr |= 1; 50 qemu_irq_pulse(s->irq); 51 stm32f2xx_timer_set_alarm(s, s->hit_time); 52 } 53 } 54 55 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t) 56 { 57 return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); 58 } 59 60 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now) 61 { 62 uint64_t ticks; 63 int64_t now_ticks; 64 65 if (s->tim_arr == 0) { 66 return; 67 } 68 69 DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1); 70 71 now_ticks = stm32f2xx_ns_to_ticks(s, now); 72 ticks = s->tim_arr - (now_ticks - s->tick_offset); 73 74 DB_PRINT("Alarm set in %d ticks\n", (int) ticks); 75 76 s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1), 77 1000000000ULL, s->freq_hz); 78 79 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time); 80 DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time); 81 } 82 83 static void stm32f2xx_timer_reset(DeviceState *dev) 84 { 85 STM32F2XXTimerState *s = STM32F2XXTIMER(dev); 86 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 87 88 s->tim_cr1 = 0; 89 s->tim_cr2 = 0; 90 s->tim_smcr = 0; 91 s->tim_dier = 0; 92 s->tim_sr = 0; 93 s->tim_egr = 0; 94 s->tim_ccmr1 = 0; 95 s->tim_ccmr2 = 0; 96 s->tim_ccer = 0; 97 s->tim_psc = 0; 98 s->tim_arr = 0; 99 s->tim_ccr1 = 0; 100 s->tim_ccr2 = 0; 101 s->tim_ccr3 = 0; 102 s->tim_ccr4 = 0; 103 s->tim_dcr = 0; 104 s->tim_dmar = 0; 105 s->tim_or = 0; 106 107 s->tick_offset = stm32f2xx_ns_to_ticks(s, now); 108 } 109 110 static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset, 111 unsigned size) 112 { 113 STM32F2XXTimerState *s = opaque; 114 115 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); 116 117 switch (offset) { 118 case TIM_CR1: 119 return s->tim_cr1; 120 case TIM_CR2: 121 return s->tim_cr2; 122 case TIM_SMCR: 123 return s->tim_smcr; 124 case TIM_DIER: 125 return s->tim_dier; 126 case TIM_SR: 127 return s->tim_sr; 128 case TIM_EGR: 129 return s->tim_egr; 130 case TIM_CCMR1: 131 return s->tim_ccmr1; 132 case TIM_CCMR2: 133 return s->tim_ccmr2; 134 case TIM_CCER: 135 return s->tim_ccer; 136 case TIM_CNT: 137 return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) - 138 s->tick_offset; 139 case TIM_PSC: 140 return s->tim_psc; 141 case TIM_ARR: 142 return s->tim_arr; 143 case TIM_CCR1: 144 return s->tim_ccr1; 145 case TIM_CCR2: 146 return s->tim_ccr2; 147 case TIM_CCR3: 148 return s->tim_ccr3; 149 case TIM_CCR4: 150 return s->tim_ccr4; 151 case TIM_DCR: 152 return s->tim_dcr; 153 case TIM_DMAR: 154 return s->tim_dmar; 155 case TIM_OR: 156 return s->tim_or; 157 default: 158 qemu_log_mask(LOG_GUEST_ERROR, 159 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 160 } 161 162 return 0; 163 } 164 165 static void stm32f2xx_timer_write(void *opaque, hwaddr offset, 166 uint64_t val64, unsigned size) 167 { 168 STM32F2XXTimerState *s = opaque; 169 uint32_t value = val64; 170 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 171 uint32_t timer_val = 0; 172 173 DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); 174 175 switch (offset) { 176 case TIM_CR1: 177 s->tim_cr1 = value; 178 return; 179 case TIM_CR2: 180 s->tim_cr2 = value; 181 return; 182 case TIM_SMCR: 183 s->tim_smcr = value; 184 return; 185 case TIM_DIER: 186 s->tim_dier = value; 187 return; 188 case TIM_SR: 189 /* This is set by hardware and cleared by software */ 190 s->tim_sr &= value; 191 return; 192 case TIM_EGR: 193 s->tim_egr = value; 194 if (s->tim_egr & TIM_EGR_UG) { 195 timer_val = 0; 196 break; 197 } 198 return; 199 case TIM_CCMR1: 200 s->tim_ccmr1 = value; 201 return; 202 case TIM_CCMR2: 203 s->tim_ccmr2 = value; 204 return; 205 case TIM_CCER: 206 s->tim_ccer = value; 207 return; 208 case TIM_PSC: 209 timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset; 210 s->tim_psc = value; 211 value = timer_val; 212 break; 213 case TIM_CNT: 214 timer_val = value; 215 break; 216 case TIM_ARR: 217 s->tim_arr = value; 218 stm32f2xx_timer_set_alarm(s, now); 219 return; 220 case TIM_CCR1: 221 s->tim_ccr1 = value; 222 return; 223 case TIM_CCR2: 224 s->tim_ccr2 = value; 225 return; 226 case TIM_CCR3: 227 s->tim_ccr3 = value; 228 return; 229 case TIM_CCR4: 230 s->tim_ccr4 = value; 231 return; 232 case TIM_DCR: 233 s->tim_dcr = value; 234 return; 235 case TIM_DMAR: 236 s->tim_dmar = value; 237 return; 238 case TIM_OR: 239 s->tim_or = value; 240 return; 241 default: 242 qemu_log_mask(LOG_GUEST_ERROR, 243 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 244 return; 245 } 246 247 /* This means that a register write has affected the timer in a way that 248 * requires a refresh of both tick_offset and the alarm. 249 */ 250 s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; 251 stm32f2xx_timer_set_alarm(s, now); 252 } 253 254 static const MemoryRegionOps stm32f2xx_timer_ops = { 255 .read = stm32f2xx_timer_read, 256 .write = stm32f2xx_timer_write, 257 .endianness = DEVICE_NATIVE_ENDIAN, 258 }; 259 260 static const VMStateDescription vmstate_stm32f2xx_timer = { 261 .name = TYPE_STM32F2XX_TIMER, 262 .version_id = 1, 263 .minimum_version_id = 1, 264 .fields = (VMStateField[]) { 265 VMSTATE_INT64(tick_offset, STM32F2XXTimerState), 266 VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), 267 VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), 268 VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), 269 VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), 270 VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), 271 VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), 272 VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), 273 VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), 274 VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), 275 VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), 276 VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), 277 VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), 278 VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), 279 VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), 280 VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState), 281 VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState), 282 VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState), 283 VMSTATE_UINT32(tim_or, STM32F2XXTimerState), 284 VMSTATE_END_OF_LIST() 285 } 286 }; 287 288 static Property stm32f2xx_timer_properties[] = { 289 DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState, 290 freq_hz, 1000000000), 291 DEFINE_PROP_END_OF_LIST(), 292 }; 293 294 static void stm32f2xx_timer_init(Object *obj) 295 { 296 STM32F2XXTimerState *s = STM32F2XXTIMER(obj); 297 298 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 299 300 memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, 301 "stm32f2xx_timer", 0x4000); 302 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 303 304 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); 305 } 306 307 static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) 308 { 309 DeviceClass *dc = DEVICE_CLASS(klass); 310 311 dc->reset = stm32f2xx_timer_reset; 312 dc->props = stm32f2xx_timer_properties; 313 dc->vmsd = &vmstate_stm32f2xx_timer; 314 } 315 316 static const TypeInfo stm32f2xx_timer_info = { 317 .name = TYPE_STM32F2XX_TIMER, 318 .parent = TYPE_SYS_BUS_DEVICE, 319 .instance_size = sizeof(STM32F2XXTimerState), 320 .instance_init = stm32f2xx_timer_init, 321 .class_init = stm32f2xx_timer_class_init, 322 }; 323 324 static void stm32f2xx_timer_register_types(void) 325 { 326 type_register_static(&stm32f2xx_timer_info); 327 } 328 329 type_init(stm32f2xx_timer_register_types) 330