1 /* 2 * STM32F2XX Timer 3 * 4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "hw/timer/stm32f2xx_timer.h" 27 #include "qemu/log.h" 28 29 #ifndef STM_TIMER_ERR_DEBUG 30 #define STM_TIMER_ERR_DEBUG 0 31 #endif 32 33 #define DB_PRINT_L(lvl, fmt, args...) do { \ 34 if (STM_TIMER_ERR_DEBUG >= lvl) { \ 35 qemu_log("%s: " fmt, __func__, ## args); \ 36 } \ 37 } while (0); 38 39 #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) 40 41 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now); 42 43 static void stm32f2xx_timer_interrupt(void *opaque) 44 { 45 STM32F2XXTimerState *s = opaque; 46 47 DB_PRINT("Interrupt\n"); 48 49 if (s->tim_dier & TIM_DIER_UIE && s->tim_cr1 & TIM_CR1_CEN) { 50 s->tim_sr |= 1; 51 qemu_irq_pulse(s->irq); 52 stm32f2xx_timer_set_alarm(s, s->hit_time); 53 } 54 } 55 56 static inline int64_t stm32f2xx_ns_to_ticks(STM32F2XXTimerState *s, int64_t t) 57 { 58 return muldiv64(t, s->freq_hz, 1000000000ULL) / (s->tim_psc + 1); 59 } 60 61 static void stm32f2xx_timer_set_alarm(STM32F2XXTimerState *s, int64_t now) 62 { 63 uint64_t ticks; 64 int64_t now_ticks; 65 66 if (s->tim_arr == 0) { 67 return; 68 } 69 70 DB_PRINT("Alarm set at: 0x%x\n", s->tim_cr1); 71 72 now_ticks = stm32f2xx_ns_to_ticks(s, now); 73 ticks = s->tim_arr - (now_ticks - s->tick_offset); 74 75 DB_PRINT("Alarm set in %d ticks\n", (int) ticks); 76 77 s->hit_time = muldiv64((ticks + (uint64_t) now_ticks) * (s->tim_psc + 1), 78 1000000000ULL, s->freq_hz); 79 80 timer_mod(s->timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + s->hit_time); 81 DB_PRINT("Wait Time: %" PRId64 " ticks\n", s->hit_time); 82 } 83 84 static void stm32f2xx_timer_reset(DeviceState *dev) 85 { 86 STM32F2XXTimerState *s = STM32F2XXTIMER(dev); 87 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 88 89 s->tim_cr1 = 0; 90 s->tim_cr2 = 0; 91 s->tim_smcr = 0; 92 s->tim_dier = 0; 93 s->tim_sr = 0; 94 s->tim_egr = 0; 95 s->tim_ccmr1 = 0; 96 s->tim_ccmr2 = 0; 97 s->tim_ccer = 0; 98 s->tim_psc = 0; 99 s->tim_arr = 0; 100 s->tim_ccr1 = 0; 101 s->tim_ccr2 = 0; 102 s->tim_ccr3 = 0; 103 s->tim_ccr4 = 0; 104 s->tim_dcr = 0; 105 s->tim_dmar = 0; 106 s->tim_or = 0; 107 108 s->tick_offset = stm32f2xx_ns_to_ticks(s, now); 109 } 110 111 static uint64_t stm32f2xx_timer_read(void *opaque, hwaddr offset, 112 unsigned size) 113 { 114 STM32F2XXTimerState *s = opaque; 115 116 DB_PRINT("Read 0x%"HWADDR_PRIx"\n", offset); 117 118 switch (offset) { 119 case TIM_CR1: 120 return s->tim_cr1; 121 case TIM_CR2: 122 return s->tim_cr2; 123 case TIM_SMCR: 124 return s->tim_smcr; 125 case TIM_DIER: 126 return s->tim_dier; 127 case TIM_SR: 128 return s->tim_sr; 129 case TIM_EGR: 130 return s->tim_egr; 131 case TIM_CCMR1: 132 return s->tim_ccmr1; 133 case TIM_CCMR2: 134 return s->tim_ccmr2; 135 case TIM_CCER: 136 return s->tim_ccer; 137 case TIM_CNT: 138 return stm32f2xx_ns_to_ticks(s, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)) - 139 s->tick_offset; 140 case TIM_PSC: 141 return s->tim_psc; 142 case TIM_ARR: 143 return s->tim_arr; 144 case TIM_CCR1: 145 return s->tim_ccr1; 146 case TIM_CCR2: 147 return s->tim_ccr2; 148 case TIM_CCR3: 149 return s->tim_ccr3; 150 case TIM_CCR4: 151 return s->tim_ccr4; 152 case TIM_DCR: 153 return s->tim_dcr; 154 case TIM_DMAR: 155 return s->tim_dmar; 156 case TIM_OR: 157 return s->tim_or; 158 default: 159 qemu_log_mask(LOG_GUEST_ERROR, 160 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 161 } 162 163 return 0; 164 } 165 166 static void stm32f2xx_timer_write(void *opaque, hwaddr offset, 167 uint64_t val64, unsigned size) 168 { 169 STM32F2XXTimerState *s = opaque; 170 uint32_t value = val64; 171 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 172 uint32_t timer_val = 0; 173 174 DB_PRINT("Write 0x%x, 0x%"HWADDR_PRIx"\n", value, offset); 175 176 switch (offset) { 177 case TIM_CR1: 178 s->tim_cr1 = value; 179 return; 180 case TIM_CR2: 181 s->tim_cr2 = value; 182 return; 183 case TIM_SMCR: 184 s->tim_smcr = value; 185 return; 186 case TIM_DIER: 187 s->tim_dier = value; 188 return; 189 case TIM_SR: 190 /* This is set by hardware and cleared by software */ 191 s->tim_sr &= value; 192 return; 193 case TIM_EGR: 194 s->tim_egr = value; 195 if (s->tim_egr & TIM_EGR_UG) { 196 timer_val = 0; 197 break; 198 } 199 return; 200 case TIM_CCMR1: 201 s->tim_ccmr1 = value; 202 return; 203 case TIM_CCMR2: 204 s->tim_ccmr2 = value; 205 return; 206 case TIM_CCER: 207 s->tim_ccer = value; 208 return; 209 case TIM_PSC: 210 timer_val = stm32f2xx_ns_to_ticks(s, now) - s->tick_offset; 211 s->tim_psc = value; 212 value = timer_val; 213 break; 214 case TIM_CNT: 215 timer_val = value; 216 break; 217 case TIM_ARR: 218 s->tim_arr = value; 219 stm32f2xx_timer_set_alarm(s, now); 220 return; 221 case TIM_CCR1: 222 s->tim_ccr1 = value; 223 return; 224 case TIM_CCR2: 225 s->tim_ccr2 = value; 226 return; 227 case TIM_CCR3: 228 s->tim_ccr3 = value; 229 return; 230 case TIM_CCR4: 231 s->tim_ccr4 = value; 232 return; 233 case TIM_DCR: 234 s->tim_dcr = value; 235 return; 236 case TIM_DMAR: 237 s->tim_dmar = value; 238 return; 239 case TIM_OR: 240 s->tim_or = value; 241 return; 242 default: 243 qemu_log_mask(LOG_GUEST_ERROR, 244 "%s: Bad offset 0x%"HWADDR_PRIx"\n", __func__, offset); 245 return; 246 } 247 248 /* This means that a register write has affected the timer in a way that 249 * requires a refresh of both tick_offset and the alarm. 250 */ 251 s->tick_offset = stm32f2xx_ns_to_ticks(s, now) - timer_val; 252 stm32f2xx_timer_set_alarm(s, now); 253 } 254 255 static const MemoryRegionOps stm32f2xx_timer_ops = { 256 .read = stm32f2xx_timer_read, 257 .write = stm32f2xx_timer_write, 258 .endianness = DEVICE_NATIVE_ENDIAN, 259 }; 260 261 static const VMStateDescription vmstate_stm32f2xx_timer = { 262 .name = TYPE_STM32F2XX_TIMER, 263 .version_id = 1, 264 .minimum_version_id = 1, 265 .fields = (VMStateField[]) { 266 VMSTATE_INT64(tick_offset, STM32F2XXTimerState), 267 VMSTATE_UINT32(tim_cr1, STM32F2XXTimerState), 268 VMSTATE_UINT32(tim_cr2, STM32F2XXTimerState), 269 VMSTATE_UINT32(tim_smcr, STM32F2XXTimerState), 270 VMSTATE_UINT32(tim_dier, STM32F2XXTimerState), 271 VMSTATE_UINT32(tim_sr, STM32F2XXTimerState), 272 VMSTATE_UINT32(tim_egr, STM32F2XXTimerState), 273 VMSTATE_UINT32(tim_ccmr1, STM32F2XXTimerState), 274 VMSTATE_UINT32(tim_ccmr2, STM32F2XXTimerState), 275 VMSTATE_UINT32(tim_ccer, STM32F2XXTimerState), 276 VMSTATE_UINT32(tim_psc, STM32F2XXTimerState), 277 VMSTATE_UINT32(tim_arr, STM32F2XXTimerState), 278 VMSTATE_UINT32(tim_ccr1, STM32F2XXTimerState), 279 VMSTATE_UINT32(tim_ccr2, STM32F2XXTimerState), 280 VMSTATE_UINT32(tim_ccr3, STM32F2XXTimerState), 281 VMSTATE_UINT32(tim_ccr4, STM32F2XXTimerState), 282 VMSTATE_UINT32(tim_dcr, STM32F2XXTimerState), 283 VMSTATE_UINT32(tim_dmar, STM32F2XXTimerState), 284 VMSTATE_UINT32(tim_or, STM32F2XXTimerState), 285 VMSTATE_END_OF_LIST() 286 } 287 }; 288 289 static Property stm32f2xx_timer_properties[] = { 290 DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState, 291 freq_hz, 1000000000), 292 DEFINE_PROP_END_OF_LIST(), 293 }; 294 295 static void stm32f2xx_timer_init(Object *obj) 296 { 297 STM32F2XXTimerState *s = STM32F2XXTIMER(obj); 298 299 sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); 300 301 memory_region_init_io(&s->iomem, obj, &stm32f2xx_timer_ops, s, 302 "stm32f2xx_timer", 0x4000); 303 sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); 304 305 s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, stm32f2xx_timer_interrupt, s); 306 } 307 308 static void stm32f2xx_timer_class_init(ObjectClass *klass, void *data) 309 { 310 DeviceClass *dc = DEVICE_CLASS(klass); 311 312 dc->reset = stm32f2xx_timer_reset; 313 dc->props = stm32f2xx_timer_properties; 314 dc->vmsd = &vmstate_stm32f2xx_timer; 315 } 316 317 static const TypeInfo stm32f2xx_timer_info = { 318 .name = TYPE_STM32F2XX_TIMER, 319 .parent = TYPE_SYS_BUS_DEVICE, 320 .instance_size = sizeof(STM32F2XXTimerState), 321 .instance_init = stm32f2xx_timer_init, 322 .class_init = stm32f2xx_timer_class_init, 323 }; 324 325 static void stm32f2xx_timer_register_types(void) 326 { 327 type_register_static(&stm32f2xx_timer_info); 328 } 329 330 type_init(stm32f2xx_timer_register_types) 331