1 /* 2 * QEMU USB OHCI Emulation 3 * Copyright (c) 2004 Gianni Tedesco 4 * Copyright (c) 2006 CodeSourcery 5 * Copyright (c) 2006 Openedhand Ltd. 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 * 20 * TODO: 21 * o Isochronous transfers 22 * o Allocate bandwidth in frames properly 23 * o Disable timers when nothing needs to be done, or remove timer usage 24 * all together. 25 * o BIOS work to boot from USB storage 26 */ 27 28 #include "qemu/osdep.h" 29 #include "hw/hw.h" 30 #include "qapi/error.h" 31 #include "qemu/module.h" 32 #include "qemu/timer.h" 33 #include "hw/usb.h" 34 #include "hw/sysbus.h" 35 #include "hw/qdev-dma.h" 36 #include "trace.h" 37 #include "hcd-ohci.h" 38 39 /* This causes frames to occur 1000x slower */ 40 //#define OHCI_TIME_WARP 1 41 42 #define ED_LINK_LIMIT 32 43 44 static int64_t usb_frame_time; 45 static int64_t usb_bit_time; 46 47 /* Host Controller Communications Area */ 48 struct ohci_hcca { 49 uint32_t intr[32]; 50 uint16_t frame, pad; 51 uint32_t done; 52 }; 53 #define HCCA_WRITEBACK_OFFSET offsetof(struct ohci_hcca, frame) 54 #define HCCA_WRITEBACK_SIZE 8 /* frame, pad, done */ 55 56 #define ED_WBACK_OFFSET offsetof(struct ohci_ed, head) 57 #define ED_WBACK_SIZE 4 58 59 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev); 60 61 /* Bitfields for the first word of an Endpoint Desciptor. */ 62 #define OHCI_ED_FA_SHIFT 0 63 #define OHCI_ED_FA_MASK (0x7f<<OHCI_ED_FA_SHIFT) 64 #define OHCI_ED_EN_SHIFT 7 65 #define OHCI_ED_EN_MASK (0xf<<OHCI_ED_EN_SHIFT) 66 #define OHCI_ED_D_SHIFT 11 67 #define OHCI_ED_D_MASK (3<<OHCI_ED_D_SHIFT) 68 #define OHCI_ED_S (1<<13) 69 #define OHCI_ED_K (1<<14) 70 #define OHCI_ED_F (1<<15) 71 #define OHCI_ED_MPS_SHIFT 16 72 #define OHCI_ED_MPS_MASK (0x7ff<<OHCI_ED_MPS_SHIFT) 73 74 /* Flags in the head field of an Endpoint Desciptor. */ 75 #define OHCI_ED_H 1 76 #define OHCI_ED_C 2 77 78 /* Bitfields for the first word of a Transfer Desciptor. */ 79 #define OHCI_TD_R (1<<18) 80 #define OHCI_TD_DP_SHIFT 19 81 #define OHCI_TD_DP_MASK (3<<OHCI_TD_DP_SHIFT) 82 #define OHCI_TD_DI_SHIFT 21 83 #define OHCI_TD_DI_MASK (7<<OHCI_TD_DI_SHIFT) 84 #define OHCI_TD_T0 (1<<24) 85 #define OHCI_TD_T1 (1<<25) 86 #define OHCI_TD_EC_SHIFT 26 87 #define OHCI_TD_EC_MASK (3<<OHCI_TD_EC_SHIFT) 88 #define OHCI_TD_CC_SHIFT 28 89 #define OHCI_TD_CC_MASK (0xf<<OHCI_TD_CC_SHIFT) 90 91 /* Bitfields for the first word of an Isochronous Transfer Desciptor. */ 92 /* CC & DI - same as in the General Transfer Desciptor */ 93 #define OHCI_TD_SF_SHIFT 0 94 #define OHCI_TD_SF_MASK (0xffff<<OHCI_TD_SF_SHIFT) 95 #define OHCI_TD_FC_SHIFT 24 96 #define OHCI_TD_FC_MASK (7<<OHCI_TD_FC_SHIFT) 97 98 /* Isochronous Transfer Desciptor - Offset / PacketStatusWord */ 99 #define OHCI_TD_PSW_CC_SHIFT 12 100 #define OHCI_TD_PSW_CC_MASK (0xf<<OHCI_TD_PSW_CC_SHIFT) 101 #define OHCI_TD_PSW_SIZE_SHIFT 0 102 #define OHCI_TD_PSW_SIZE_MASK (0xfff<<OHCI_TD_PSW_SIZE_SHIFT) 103 104 #define OHCI_PAGE_MASK 0xfffff000 105 #define OHCI_OFFSET_MASK 0xfff 106 107 #define OHCI_DPTR_MASK 0xfffffff0 108 109 #define OHCI_BM(val, field) \ 110 (((val) & OHCI_##field##_MASK) >> OHCI_##field##_SHIFT) 111 112 #define OHCI_SET_BM(val, field, newval) do { \ 113 val &= ~OHCI_##field##_MASK; \ 114 val |= ((newval) << OHCI_##field##_SHIFT) & OHCI_##field##_MASK; \ 115 } while(0) 116 117 /* endpoint descriptor */ 118 struct ohci_ed { 119 uint32_t flags; 120 uint32_t tail; 121 uint32_t head; 122 uint32_t next; 123 }; 124 125 /* General transfer descriptor */ 126 struct ohci_td { 127 uint32_t flags; 128 uint32_t cbp; 129 uint32_t next; 130 uint32_t be; 131 }; 132 133 /* Isochronous transfer descriptor */ 134 struct ohci_iso_td { 135 uint32_t flags; 136 uint32_t bp; 137 uint32_t next; 138 uint32_t be; 139 uint16_t offset[8]; 140 }; 141 142 #define USB_HZ 12000000 143 144 /* OHCI Local stuff */ 145 #define OHCI_CTL_CBSR ((1<<0)|(1<<1)) 146 #define OHCI_CTL_PLE (1<<2) 147 #define OHCI_CTL_IE (1<<3) 148 #define OHCI_CTL_CLE (1<<4) 149 #define OHCI_CTL_BLE (1<<5) 150 #define OHCI_CTL_HCFS ((1<<6)|(1<<7)) 151 #define OHCI_USB_RESET 0x00 152 #define OHCI_USB_RESUME 0x40 153 #define OHCI_USB_OPERATIONAL 0x80 154 #define OHCI_USB_SUSPEND 0xc0 155 #define OHCI_CTL_IR (1<<8) 156 #define OHCI_CTL_RWC (1<<9) 157 #define OHCI_CTL_RWE (1<<10) 158 159 #define OHCI_STATUS_HCR (1<<0) 160 #define OHCI_STATUS_CLF (1<<1) 161 #define OHCI_STATUS_BLF (1<<2) 162 #define OHCI_STATUS_OCR (1<<3) 163 #define OHCI_STATUS_SOC ((1<<6)|(1<<7)) 164 165 #define OHCI_INTR_SO (1U<<0) /* Scheduling overrun */ 166 #define OHCI_INTR_WD (1U<<1) /* HcDoneHead writeback */ 167 #define OHCI_INTR_SF (1U<<2) /* Start of frame */ 168 #define OHCI_INTR_RD (1U<<3) /* Resume detect */ 169 #define OHCI_INTR_UE (1U<<4) /* Unrecoverable error */ 170 #define OHCI_INTR_FNO (1U<<5) /* Frame number overflow */ 171 #define OHCI_INTR_RHSC (1U<<6) /* Root hub status change */ 172 #define OHCI_INTR_OC (1U<<30) /* Ownership change */ 173 #define OHCI_INTR_MIE (1U<<31) /* Master Interrupt Enable */ 174 175 #define OHCI_HCCA_SIZE 0x100 176 #define OHCI_HCCA_MASK 0xffffff00 177 178 #define OHCI_EDPTR_MASK 0xfffffff0 179 180 #define OHCI_FMI_FI 0x00003fff 181 #define OHCI_FMI_FSMPS 0xffff0000 182 #define OHCI_FMI_FIT 0x80000000 183 184 #define OHCI_FR_RT (1U<<31) 185 186 #define OHCI_LS_THRESH 0x628 187 188 #define OHCI_RHA_RW_MASK 0x00000000 /* Mask of supported features. */ 189 #define OHCI_RHA_PSM (1<<8) 190 #define OHCI_RHA_NPS (1<<9) 191 #define OHCI_RHA_DT (1<<10) 192 #define OHCI_RHA_OCPM (1<<11) 193 #define OHCI_RHA_NOCP (1<<12) 194 #define OHCI_RHA_POTPGT_MASK 0xff000000 195 196 #define OHCI_RHS_LPS (1U<<0) 197 #define OHCI_RHS_OCI (1U<<1) 198 #define OHCI_RHS_DRWE (1U<<15) 199 #define OHCI_RHS_LPSC (1U<<16) 200 #define OHCI_RHS_OCIC (1U<<17) 201 #define OHCI_RHS_CRWE (1U<<31) 202 203 #define OHCI_PORT_CCS (1<<0) 204 #define OHCI_PORT_PES (1<<1) 205 #define OHCI_PORT_PSS (1<<2) 206 #define OHCI_PORT_POCI (1<<3) 207 #define OHCI_PORT_PRS (1<<4) 208 #define OHCI_PORT_PPS (1<<8) 209 #define OHCI_PORT_LSDA (1<<9) 210 #define OHCI_PORT_CSC (1<<16) 211 #define OHCI_PORT_PESC (1<<17) 212 #define OHCI_PORT_PSSC (1<<18) 213 #define OHCI_PORT_OCIC (1<<19) 214 #define OHCI_PORT_PRSC (1<<20) 215 #define OHCI_PORT_WTC (OHCI_PORT_CSC|OHCI_PORT_PESC|OHCI_PORT_PSSC \ 216 |OHCI_PORT_OCIC|OHCI_PORT_PRSC) 217 218 #define OHCI_TD_DIR_SETUP 0x0 219 #define OHCI_TD_DIR_OUT 0x1 220 #define OHCI_TD_DIR_IN 0x2 221 #define OHCI_TD_DIR_RESERVED 0x3 222 223 #define OHCI_CC_NOERROR 0x0 224 #define OHCI_CC_CRC 0x1 225 #define OHCI_CC_BITSTUFFING 0x2 226 #define OHCI_CC_DATATOGGLEMISMATCH 0x3 227 #define OHCI_CC_STALL 0x4 228 #define OHCI_CC_DEVICENOTRESPONDING 0x5 229 #define OHCI_CC_PIDCHECKFAILURE 0x6 230 #define OHCI_CC_UNDEXPETEDPID 0x7 231 #define OHCI_CC_DATAOVERRUN 0x8 232 #define OHCI_CC_DATAUNDERRUN 0x9 233 #define OHCI_CC_BUFFEROVERRUN 0xc 234 #define OHCI_CC_BUFFERUNDERRUN 0xd 235 236 #define OHCI_HRESET_FSBIR (1 << 0) 237 238 static void ohci_die(OHCIState *ohci) 239 { 240 ohci->ohci_die(ohci); 241 } 242 243 /* Update IRQ levels */ 244 static inline void ohci_intr_update(OHCIState *ohci) 245 { 246 int level = 0; 247 248 if ((ohci->intr & OHCI_INTR_MIE) && 249 (ohci->intr_status & ohci->intr)) 250 level = 1; 251 252 qemu_set_irq(ohci->irq, level); 253 } 254 255 /* Set an interrupt */ 256 static inline void ohci_set_interrupt(OHCIState *ohci, uint32_t intr) 257 { 258 ohci->intr_status |= intr; 259 ohci_intr_update(ohci); 260 } 261 262 /* Attach or detach a device on a root hub port. */ 263 static void ohci_attach(USBPort *port1) 264 { 265 OHCIState *s = port1->opaque; 266 OHCIPort *port = &s->rhport[port1->index]; 267 uint32_t old_state = port->ctrl; 268 269 /* set connect status */ 270 port->ctrl |= OHCI_PORT_CCS | OHCI_PORT_CSC; 271 272 /* update speed */ 273 if (port->port.dev->speed == USB_SPEED_LOW) { 274 port->ctrl |= OHCI_PORT_LSDA; 275 } else { 276 port->ctrl &= ~OHCI_PORT_LSDA; 277 } 278 279 /* notify of remote-wakeup */ 280 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 281 ohci_set_interrupt(s, OHCI_INTR_RD); 282 } 283 284 trace_usb_ohci_port_attach(port1->index); 285 286 if (old_state != port->ctrl) { 287 ohci_set_interrupt(s, OHCI_INTR_RHSC); 288 } 289 } 290 291 static void ohci_detach(USBPort *port1) 292 { 293 OHCIState *s = port1->opaque; 294 OHCIPort *port = &s->rhport[port1->index]; 295 uint32_t old_state = port->ctrl; 296 297 ohci_async_cancel_device(s, port1->dev); 298 299 /* set connect status */ 300 if (port->ctrl & OHCI_PORT_CCS) { 301 port->ctrl &= ~OHCI_PORT_CCS; 302 port->ctrl |= OHCI_PORT_CSC; 303 } 304 /* disable port */ 305 if (port->ctrl & OHCI_PORT_PES) { 306 port->ctrl &= ~OHCI_PORT_PES; 307 port->ctrl |= OHCI_PORT_PESC; 308 } 309 trace_usb_ohci_port_detach(port1->index); 310 311 if (old_state != port->ctrl) { 312 ohci_set_interrupt(s, OHCI_INTR_RHSC); 313 } 314 } 315 316 static void ohci_wakeup(USBPort *port1) 317 { 318 OHCIState *s = port1->opaque; 319 OHCIPort *port = &s->rhport[port1->index]; 320 uint32_t intr = 0; 321 if (port->ctrl & OHCI_PORT_PSS) { 322 trace_usb_ohci_port_wakeup(port1->index); 323 port->ctrl |= OHCI_PORT_PSSC; 324 port->ctrl &= ~OHCI_PORT_PSS; 325 intr = OHCI_INTR_RHSC; 326 } 327 /* Note that the controller can be suspended even if this port is not */ 328 if ((s->ctl & OHCI_CTL_HCFS) == OHCI_USB_SUSPEND) { 329 trace_usb_ohci_remote_wakeup(s->name); 330 /* This is the one state transition the controller can do by itself */ 331 s->ctl &= ~OHCI_CTL_HCFS; 332 s->ctl |= OHCI_USB_RESUME; 333 /* In suspend mode only ResumeDetected is possible, not RHSC: 334 * see the OHCI spec 5.1.2.3. 335 */ 336 intr = OHCI_INTR_RD; 337 } 338 ohci_set_interrupt(s, intr); 339 } 340 341 static void ohci_child_detach(USBPort *port1, USBDevice *child) 342 { 343 OHCIState *s = port1->opaque; 344 345 ohci_async_cancel_device(s, child); 346 } 347 348 static USBDevice *ohci_find_device(OHCIState *ohci, uint8_t addr) 349 { 350 USBDevice *dev; 351 int i; 352 353 for (i = 0; i < ohci->num_ports; i++) { 354 if ((ohci->rhport[i].ctrl & OHCI_PORT_PES) == 0) { 355 continue; 356 } 357 dev = usb_find_device(&ohci->rhport[i].port, addr); 358 if (dev != NULL) { 359 return dev; 360 } 361 } 362 return NULL; 363 } 364 365 void ohci_stop_endpoints(OHCIState *ohci) 366 { 367 USBDevice *dev; 368 int i, j; 369 370 for (i = 0; i < ohci->num_ports; i++) { 371 dev = ohci->rhport[i].port.dev; 372 if (dev && dev->attached) { 373 usb_device_ep_stopped(dev, &dev->ep_ctl); 374 for (j = 0; j < USB_MAX_ENDPOINTS; j++) { 375 usb_device_ep_stopped(dev, &dev->ep_in[j]); 376 usb_device_ep_stopped(dev, &dev->ep_out[j]); 377 } 378 } 379 } 380 } 381 382 static void ohci_roothub_reset(OHCIState *ohci) 383 { 384 OHCIPort *port; 385 int i; 386 387 ohci_bus_stop(ohci); 388 ohci->rhdesc_a = OHCI_RHA_NPS | ohci->num_ports; 389 ohci->rhdesc_b = 0x0; /* Impl. specific */ 390 ohci->rhstatus = 0; 391 392 for (i = 0; i < ohci->num_ports; i++) { 393 port = &ohci->rhport[i]; 394 port->ctrl = 0; 395 if (port->port.dev && port->port.dev->attached) { 396 usb_port_reset(&port->port); 397 } 398 } 399 if (ohci->async_td) { 400 usb_cancel_packet(&ohci->usb_packet); 401 ohci->async_td = 0; 402 } 403 ohci_stop_endpoints(ohci); 404 } 405 406 /* Reset the controller */ 407 static void ohci_soft_reset(OHCIState *ohci) 408 { 409 trace_usb_ohci_reset(ohci->name); 410 411 ohci_bus_stop(ohci); 412 ohci->ctl = (ohci->ctl & OHCI_CTL_IR) | OHCI_USB_SUSPEND; 413 ohci->old_ctl = 0; 414 ohci->status = 0; 415 ohci->intr_status = 0; 416 ohci->intr = OHCI_INTR_MIE; 417 418 ohci->hcca = 0; 419 ohci->ctrl_head = ohci->ctrl_cur = 0; 420 ohci->bulk_head = ohci->bulk_cur = 0; 421 ohci->per_cur = 0; 422 ohci->done = 0; 423 ohci->done_count = 7; 424 425 /* FSMPS is marked TBD in OCHI 1.0, what gives ffs? 426 * I took the value linux sets ... 427 */ 428 ohci->fsmps = 0x2778; 429 ohci->fi = 0x2edf; 430 ohci->fit = 0; 431 ohci->frt = 0; 432 ohci->frame_number = 0; 433 ohci->pstart = 0; 434 ohci->lst = OHCI_LS_THRESH; 435 } 436 437 void ohci_hard_reset(OHCIState *ohci) 438 { 439 ohci_soft_reset(ohci); 440 ohci->ctl = 0; 441 ohci_roothub_reset(ohci); 442 } 443 444 /* Get an array of dwords from main memory */ 445 static inline int get_dwords(OHCIState *ohci, 446 dma_addr_t addr, uint32_t *buf, int num) 447 { 448 int i; 449 450 addr += ohci->localmem_base; 451 452 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 453 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 454 return -1; 455 } 456 *buf = le32_to_cpu(*buf); 457 } 458 459 return 0; 460 } 461 462 /* Put an array of dwords in to main memory */ 463 static inline int put_dwords(OHCIState *ohci, 464 dma_addr_t addr, uint32_t *buf, int num) 465 { 466 int i; 467 468 addr += ohci->localmem_base; 469 470 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 471 uint32_t tmp = cpu_to_le32(*buf); 472 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 473 return -1; 474 } 475 } 476 477 return 0; 478 } 479 480 /* Get an array of words from main memory */ 481 static inline int get_words(OHCIState *ohci, 482 dma_addr_t addr, uint16_t *buf, int num) 483 { 484 int i; 485 486 addr += ohci->localmem_base; 487 488 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 489 if (dma_memory_read(ohci->as, addr, buf, sizeof(*buf))) { 490 return -1; 491 } 492 *buf = le16_to_cpu(*buf); 493 } 494 495 return 0; 496 } 497 498 /* Put an array of words in to main memory */ 499 static inline int put_words(OHCIState *ohci, 500 dma_addr_t addr, uint16_t *buf, int num) 501 { 502 int i; 503 504 addr += ohci->localmem_base; 505 506 for (i = 0; i < num; i++, buf++, addr += sizeof(*buf)) { 507 uint16_t tmp = cpu_to_le16(*buf); 508 if (dma_memory_write(ohci->as, addr, &tmp, sizeof(tmp))) { 509 return -1; 510 } 511 } 512 513 return 0; 514 } 515 516 static inline int ohci_read_ed(OHCIState *ohci, 517 dma_addr_t addr, struct ohci_ed *ed) 518 { 519 return get_dwords(ohci, addr, (uint32_t *)ed, sizeof(*ed) >> 2); 520 } 521 522 static inline int ohci_read_td(OHCIState *ohci, 523 dma_addr_t addr, struct ohci_td *td) 524 { 525 return get_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 526 } 527 528 static inline int ohci_read_iso_td(OHCIState *ohci, 529 dma_addr_t addr, struct ohci_iso_td *td) 530 { 531 return get_dwords(ohci, addr, (uint32_t *)td, 4) || 532 get_words(ohci, addr + 16, td->offset, 8); 533 } 534 535 static inline int ohci_read_hcca(OHCIState *ohci, 536 dma_addr_t addr, struct ohci_hcca *hcca) 537 { 538 return dma_memory_read(ohci->as, addr + ohci->localmem_base, 539 hcca, sizeof(*hcca)); 540 } 541 542 static inline int ohci_put_ed(OHCIState *ohci, 543 dma_addr_t addr, struct ohci_ed *ed) 544 { 545 /* ed->tail is under control of the HCD. 546 * Since just ed->head is changed by HC, just write back this 547 */ 548 549 return put_dwords(ohci, addr + ED_WBACK_OFFSET, 550 (uint32_t *)((char *)ed + ED_WBACK_OFFSET), 551 ED_WBACK_SIZE >> 2); 552 } 553 554 static inline int ohci_put_td(OHCIState *ohci, 555 dma_addr_t addr, struct ohci_td *td) 556 { 557 return put_dwords(ohci, addr, (uint32_t *)td, sizeof(*td) >> 2); 558 } 559 560 static inline int ohci_put_iso_td(OHCIState *ohci, 561 dma_addr_t addr, struct ohci_iso_td *td) 562 { 563 return put_dwords(ohci, addr, (uint32_t *)td, 4) || 564 put_words(ohci, addr + 16, td->offset, 8); 565 } 566 567 static inline int ohci_put_hcca(OHCIState *ohci, 568 dma_addr_t addr, struct ohci_hcca *hcca) 569 { 570 return dma_memory_write(ohci->as, 571 addr + ohci->localmem_base + HCCA_WRITEBACK_OFFSET, 572 (char *)hcca + HCCA_WRITEBACK_OFFSET, 573 HCCA_WRITEBACK_SIZE); 574 } 575 576 /* Read/Write the contents of a TD from/to main memory. */ 577 static int ohci_copy_td(OHCIState *ohci, struct ohci_td *td, 578 uint8_t *buf, int len, DMADirection dir) 579 { 580 dma_addr_t ptr, n; 581 582 ptr = td->cbp; 583 n = 0x1000 - (ptr & 0xfff); 584 if (n > len) 585 n = len; 586 587 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { 588 return -1; 589 } 590 if (n == len) { 591 return 0; 592 } 593 ptr = td->be & ~0xfffu; 594 buf += n; 595 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 596 len - n, dir)) { 597 return -1; 598 } 599 return 0; 600 } 601 602 /* Read/Write the contents of an ISO TD from/to main memory. */ 603 static int ohci_copy_iso_td(OHCIState *ohci, 604 uint32_t start_addr, uint32_t end_addr, 605 uint8_t *buf, int len, DMADirection dir) 606 { 607 dma_addr_t ptr, n; 608 609 ptr = start_addr; 610 n = 0x1000 - (ptr & 0xfff); 611 if (n > len) 612 n = len; 613 614 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, n, dir)) { 615 return -1; 616 } 617 if (n == len) { 618 return 0; 619 } 620 ptr = end_addr & ~0xfffu; 621 buf += n; 622 if (dma_memory_rw(ohci->as, ptr + ohci->localmem_base, buf, 623 len - n, dir)) { 624 return -1; 625 } 626 return 0; 627 } 628 629 static void ohci_process_lists(OHCIState *ohci, int completion); 630 631 static void ohci_async_complete_packet(USBPort *port, USBPacket *packet) 632 { 633 OHCIState *ohci = container_of(packet, OHCIState, usb_packet); 634 635 trace_usb_ohci_async_complete(); 636 ohci->async_complete = true; 637 ohci_process_lists(ohci, 1); 638 } 639 640 #define USUB(a, b) ((int16_t)((uint16_t)(a) - (uint16_t)(b))) 641 642 static int ohci_service_iso_td(OHCIState *ohci, struct ohci_ed *ed, 643 int completion) 644 { 645 int dir; 646 size_t len = 0; 647 const char *str = NULL; 648 int pid; 649 int ret; 650 int i; 651 USBDevice *dev; 652 USBEndpoint *ep; 653 struct ohci_iso_td iso_td; 654 uint32_t addr; 655 uint16_t starting_frame; 656 int16_t relative_frame_number; 657 int frame_count; 658 uint32_t start_offset, next_offset, end_offset = 0; 659 uint32_t start_addr, end_addr; 660 661 addr = ed->head & OHCI_DPTR_MASK; 662 663 if (ohci_read_iso_td(ohci, addr, &iso_td)) { 664 trace_usb_ohci_iso_td_read_failed(addr); 665 ohci_die(ohci); 666 return 1; 667 } 668 669 starting_frame = OHCI_BM(iso_td.flags, TD_SF); 670 frame_count = OHCI_BM(iso_td.flags, TD_FC); 671 relative_frame_number = USUB(ohci->frame_number, starting_frame); 672 673 trace_usb_ohci_iso_td_head( 674 ed->head & OHCI_DPTR_MASK, ed->tail & OHCI_DPTR_MASK, 675 iso_td.flags, iso_td.bp, iso_td.next, iso_td.be, 676 ohci->frame_number, starting_frame, 677 frame_count, relative_frame_number); 678 trace_usb_ohci_iso_td_head_offset( 679 iso_td.offset[0], iso_td.offset[1], 680 iso_td.offset[2], iso_td.offset[3], 681 iso_td.offset[4], iso_td.offset[5], 682 iso_td.offset[6], iso_td.offset[7]); 683 684 if (relative_frame_number < 0) { 685 trace_usb_ohci_iso_td_relative_frame_number_neg(relative_frame_number); 686 return 1; 687 } else if (relative_frame_number > frame_count) { 688 /* ISO TD expired - retire the TD to the Done Queue and continue with 689 the next ISO TD of the same ED */ 690 trace_usb_ohci_iso_td_relative_frame_number_big(relative_frame_number, 691 frame_count); 692 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 693 ed->head &= ~OHCI_DPTR_MASK; 694 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 695 iso_td.next = ohci->done; 696 ohci->done = addr; 697 i = OHCI_BM(iso_td.flags, TD_DI); 698 if (i < ohci->done_count) 699 ohci->done_count = i; 700 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 701 ohci_die(ohci); 702 return 1; 703 } 704 return 0; 705 } 706 707 dir = OHCI_BM(ed->flags, ED_D); 708 switch (dir) { 709 case OHCI_TD_DIR_IN: 710 str = "in"; 711 pid = USB_TOKEN_IN; 712 break; 713 case OHCI_TD_DIR_OUT: 714 str = "out"; 715 pid = USB_TOKEN_OUT; 716 break; 717 case OHCI_TD_DIR_SETUP: 718 str = "setup"; 719 pid = USB_TOKEN_SETUP; 720 break; 721 default: 722 trace_usb_ohci_iso_td_bad_direction(dir); 723 return 1; 724 } 725 726 if (!iso_td.bp || !iso_td.be) { 727 trace_usb_ohci_iso_td_bad_bp_be(iso_td.bp, iso_td.be); 728 return 1; 729 } 730 731 start_offset = iso_td.offset[relative_frame_number]; 732 next_offset = iso_td.offset[relative_frame_number + 1]; 733 734 if (!(OHCI_BM(start_offset, TD_PSW_CC) & 0xe) || 735 ((relative_frame_number < frame_count) && 736 !(OHCI_BM(next_offset, TD_PSW_CC) & 0xe))) { 737 trace_usb_ohci_iso_td_bad_cc_not_accessed(start_offset, next_offset); 738 return 1; 739 } 740 741 if ((relative_frame_number < frame_count) && (start_offset > next_offset)) { 742 trace_usb_ohci_iso_td_bad_cc_overrun(start_offset, next_offset); 743 return 1; 744 } 745 746 if ((start_offset & 0x1000) == 0) { 747 start_addr = (iso_td.bp & OHCI_PAGE_MASK) | 748 (start_offset & OHCI_OFFSET_MASK); 749 } else { 750 start_addr = (iso_td.be & OHCI_PAGE_MASK) | 751 (start_offset & OHCI_OFFSET_MASK); 752 } 753 754 if (relative_frame_number < frame_count) { 755 end_offset = next_offset - 1; 756 if ((end_offset & 0x1000) == 0) { 757 end_addr = (iso_td.bp & OHCI_PAGE_MASK) | 758 (end_offset & OHCI_OFFSET_MASK); 759 } else { 760 end_addr = (iso_td.be & OHCI_PAGE_MASK) | 761 (end_offset & OHCI_OFFSET_MASK); 762 } 763 } else { 764 /* Last packet in the ISO TD */ 765 end_addr = iso_td.be; 766 } 767 768 if ((start_addr & OHCI_PAGE_MASK) != (end_addr & OHCI_PAGE_MASK)) { 769 len = (end_addr & OHCI_OFFSET_MASK) + 0x1001 770 - (start_addr & OHCI_OFFSET_MASK); 771 } else { 772 len = end_addr - start_addr + 1; 773 } 774 775 if (len && dir != OHCI_TD_DIR_IN) { 776 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, len, 777 DMA_DIRECTION_TO_DEVICE)) { 778 ohci_die(ohci); 779 return 1; 780 } 781 } 782 783 if (!completion) { 784 bool int_req = relative_frame_number == frame_count && 785 OHCI_BM(iso_td.flags, TD_DI) == 0; 786 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 787 if (dev == NULL) { 788 trace_usb_ohci_td_dev_error(); 789 return 1; 790 } 791 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 792 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, false, int_req); 793 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, len); 794 usb_handle_packet(dev, &ohci->usb_packet); 795 if (ohci->usb_packet.status == USB_RET_ASYNC) { 796 usb_device_flush_ep_queue(dev, ep); 797 return 1; 798 } 799 } 800 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 801 ret = ohci->usb_packet.actual_length; 802 } else { 803 ret = ohci->usb_packet.status; 804 } 805 806 trace_usb_ohci_iso_td_so(start_offset, end_offset, start_addr, end_addr, 807 str, len, ret); 808 809 /* Writeback */ 810 if (dir == OHCI_TD_DIR_IN && ret >= 0 && ret <= len) { 811 /* IN transfer succeeded */ 812 if (ohci_copy_iso_td(ohci, start_addr, end_addr, ohci->usb_buf, ret, 813 DMA_DIRECTION_FROM_DEVICE)) { 814 ohci_die(ohci); 815 return 1; 816 } 817 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 818 OHCI_CC_NOERROR); 819 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, ret); 820 } else if (dir == OHCI_TD_DIR_OUT && ret == len) { 821 /* OUT transfer succeeded */ 822 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 823 OHCI_CC_NOERROR); 824 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 0); 825 } else { 826 if (ret > (ssize_t) len) { 827 trace_usb_ohci_iso_td_data_overrun(ret, len); 828 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 829 OHCI_CC_DATAOVERRUN); 830 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 831 len); 832 } else if (ret >= 0) { 833 trace_usb_ohci_iso_td_data_underrun(ret); 834 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 835 OHCI_CC_DATAUNDERRUN); 836 } else { 837 switch (ret) { 838 case USB_RET_IOERROR: 839 case USB_RET_NODEV: 840 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 841 OHCI_CC_DEVICENOTRESPONDING); 842 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 843 0); 844 break; 845 case USB_RET_NAK: 846 case USB_RET_STALL: 847 trace_usb_ohci_iso_td_nak(ret); 848 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 849 OHCI_CC_STALL); 850 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_SIZE, 851 0); 852 break; 853 default: 854 trace_usb_ohci_iso_td_bad_response(ret); 855 OHCI_SET_BM(iso_td.offset[relative_frame_number], TD_PSW_CC, 856 OHCI_CC_UNDEXPETEDPID); 857 break; 858 } 859 } 860 } 861 862 if (relative_frame_number == frame_count) { 863 /* Last data packet of ISO TD - retire the TD to the Done Queue */ 864 OHCI_SET_BM(iso_td.flags, TD_CC, OHCI_CC_NOERROR); 865 ed->head &= ~OHCI_DPTR_MASK; 866 ed->head |= (iso_td.next & OHCI_DPTR_MASK); 867 iso_td.next = ohci->done; 868 ohci->done = addr; 869 i = OHCI_BM(iso_td.flags, TD_DI); 870 if (i < ohci->done_count) 871 ohci->done_count = i; 872 } 873 if (ohci_put_iso_td(ohci, addr, &iso_td)) { 874 ohci_die(ohci); 875 } 876 return 1; 877 } 878 879 static void ohci_td_pkt(const char *msg, const uint8_t *buf, size_t len) 880 { 881 bool print16; 882 bool printall; 883 const int width = 16; 884 int i; 885 char tmp[3 * width + 1]; 886 char *p = tmp; 887 888 print16 = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_SHORT); 889 printall = !!trace_event_get_state_backends(TRACE_USB_OHCI_TD_PKT_FULL); 890 891 if (!printall && !print16) { 892 return; 893 } 894 895 for (i = 0; ; i++) { 896 if (i && (!(i % width) || (i == len))) { 897 if (!printall) { 898 trace_usb_ohci_td_pkt_short(msg, tmp); 899 break; 900 } 901 trace_usb_ohci_td_pkt_full(msg, tmp); 902 p = tmp; 903 *p = 0; 904 } 905 if (i == len) { 906 break; 907 } 908 909 p += sprintf(p, " %.2x", buf[i]); 910 } 911 } 912 913 /* Service a transport descriptor. 914 Returns nonzero to terminate processing of this endpoint. */ 915 916 static int ohci_service_td(OHCIState *ohci, struct ohci_ed *ed) 917 { 918 int dir; 919 size_t len = 0, pktlen = 0; 920 const char *str = NULL; 921 int pid; 922 int ret; 923 int i; 924 USBDevice *dev; 925 USBEndpoint *ep; 926 struct ohci_td td; 927 uint32_t addr; 928 int flag_r; 929 int completion; 930 931 addr = ed->head & OHCI_DPTR_MASK; 932 /* See if this TD has already been submitted to the device. */ 933 completion = (addr == ohci->async_td); 934 if (completion && !ohci->async_complete) { 935 trace_usb_ohci_td_skip_async(); 936 return 1; 937 } 938 if (ohci_read_td(ohci, addr, &td)) { 939 trace_usb_ohci_td_read_error(addr); 940 ohci_die(ohci); 941 return 1; 942 } 943 944 dir = OHCI_BM(ed->flags, ED_D); 945 switch (dir) { 946 case OHCI_TD_DIR_OUT: 947 case OHCI_TD_DIR_IN: 948 /* Same value. */ 949 break; 950 default: 951 dir = OHCI_BM(td.flags, TD_DP); 952 break; 953 } 954 955 switch (dir) { 956 case OHCI_TD_DIR_IN: 957 str = "in"; 958 pid = USB_TOKEN_IN; 959 break; 960 case OHCI_TD_DIR_OUT: 961 str = "out"; 962 pid = USB_TOKEN_OUT; 963 break; 964 case OHCI_TD_DIR_SETUP: 965 str = "setup"; 966 pid = USB_TOKEN_SETUP; 967 break; 968 default: 969 trace_usb_ohci_td_bad_direction(dir); 970 return 1; 971 } 972 if (td.cbp && td.be) { 973 if ((td.cbp & 0xfffff000) != (td.be & 0xfffff000)) { 974 len = (td.be & 0xfff) + 0x1001 - (td.cbp & 0xfff); 975 } else { 976 len = (td.be - td.cbp) + 1; 977 } 978 979 pktlen = len; 980 if (len && dir != OHCI_TD_DIR_IN) { 981 /* The endpoint may not allow us to transfer it all now */ 982 pktlen = (ed->flags & OHCI_ED_MPS_MASK) >> OHCI_ED_MPS_SHIFT; 983 if (pktlen > len) { 984 pktlen = len; 985 } 986 if (!completion) { 987 if (ohci_copy_td(ohci, &td, ohci->usb_buf, pktlen, 988 DMA_DIRECTION_TO_DEVICE)) { 989 ohci_die(ohci); 990 } 991 } 992 } 993 } 994 995 flag_r = (td.flags & OHCI_TD_R) != 0; 996 trace_usb_ohci_td_pkt_hdr(addr, (int64_t)pktlen, (int64_t)len, str, 997 flag_r, td.cbp, td.be); 998 ohci_td_pkt("OUT", ohci->usb_buf, pktlen); 999 1000 if (completion) { 1001 ohci->async_td = 0; 1002 ohci->async_complete = false; 1003 } else { 1004 if (ohci->async_td) { 1005 /* ??? The hardware should allow one active packet per 1006 endpoint. We only allow one active packet per controller. 1007 This should be sufficient as long as devices respond in a 1008 timely manner. 1009 */ 1010 trace_usb_ohci_td_too_many_pending(); 1011 return 1; 1012 } 1013 dev = ohci_find_device(ohci, OHCI_BM(ed->flags, ED_FA)); 1014 if (dev == NULL) { 1015 trace_usb_ohci_td_dev_error(); 1016 return 1; 1017 } 1018 ep = usb_ep_get(dev, pid, OHCI_BM(ed->flags, ED_EN)); 1019 usb_packet_setup(&ohci->usb_packet, pid, ep, 0, addr, !flag_r, 1020 OHCI_BM(td.flags, TD_DI) == 0); 1021 usb_packet_addbuf(&ohci->usb_packet, ohci->usb_buf, pktlen); 1022 usb_handle_packet(dev, &ohci->usb_packet); 1023 trace_usb_ohci_td_packet_status(ohci->usb_packet.status); 1024 1025 if (ohci->usb_packet.status == USB_RET_ASYNC) { 1026 usb_device_flush_ep_queue(dev, ep); 1027 ohci->async_td = addr; 1028 return 1; 1029 } 1030 } 1031 if (ohci->usb_packet.status == USB_RET_SUCCESS) { 1032 ret = ohci->usb_packet.actual_length; 1033 } else { 1034 ret = ohci->usb_packet.status; 1035 } 1036 1037 if (ret >= 0) { 1038 if (dir == OHCI_TD_DIR_IN) { 1039 if (ohci_copy_td(ohci, &td, ohci->usb_buf, ret, 1040 DMA_DIRECTION_FROM_DEVICE)) { 1041 ohci_die(ohci); 1042 } 1043 ohci_td_pkt("IN", ohci->usb_buf, pktlen); 1044 } else { 1045 ret = pktlen; 1046 } 1047 } 1048 1049 /* Writeback */ 1050 if (ret == pktlen || (dir == OHCI_TD_DIR_IN && ret >= 0 && flag_r)) { 1051 /* Transmission succeeded. */ 1052 if (ret == len) { 1053 td.cbp = 0; 1054 } else { 1055 if ((td.cbp & 0xfff) + ret > 0xfff) { 1056 td.cbp = (td.be & ~0xfff) + ((td.cbp + ret) & 0xfff); 1057 } else { 1058 td.cbp += ret; 1059 } 1060 } 1061 td.flags |= OHCI_TD_T1; 1062 td.flags ^= OHCI_TD_T0; 1063 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_NOERROR); 1064 OHCI_SET_BM(td.flags, TD_EC, 0); 1065 1066 if ((dir != OHCI_TD_DIR_IN) && (ret != len)) { 1067 /* Partial packet transfer: TD not ready to retire yet */ 1068 goto exit_no_retire; 1069 } 1070 1071 /* Setting ED_C is part of the TD retirement process */ 1072 ed->head &= ~OHCI_ED_C; 1073 if (td.flags & OHCI_TD_T0) 1074 ed->head |= OHCI_ED_C; 1075 } else { 1076 if (ret >= 0) { 1077 trace_usb_ohci_td_underrun(); 1078 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAUNDERRUN); 1079 } else { 1080 switch (ret) { 1081 case USB_RET_IOERROR: 1082 case USB_RET_NODEV: 1083 trace_usb_ohci_td_dev_error(); 1084 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DEVICENOTRESPONDING); 1085 break; 1086 case USB_RET_NAK: 1087 trace_usb_ohci_td_nak(); 1088 return 1; 1089 case USB_RET_STALL: 1090 trace_usb_ohci_td_stall(); 1091 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_STALL); 1092 break; 1093 case USB_RET_BABBLE: 1094 trace_usb_ohci_td_babble(); 1095 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_DATAOVERRUN); 1096 break; 1097 default: 1098 trace_usb_ohci_td_bad_device_response(ret); 1099 OHCI_SET_BM(td.flags, TD_CC, OHCI_CC_UNDEXPETEDPID); 1100 OHCI_SET_BM(td.flags, TD_EC, 3); 1101 break; 1102 } 1103 /* An error occured so we have to clear the interrupt counter. See 1104 * spec at 6.4.4 on page 104 */ 1105 ohci->done_count = 0; 1106 } 1107 ed->head |= OHCI_ED_H; 1108 } 1109 1110 /* Retire this TD */ 1111 ed->head &= ~OHCI_DPTR_MASK; 1112 ed->head |= td.next & OHCI_DPTR_MASK; 1113 td.next = ohci->done; 1114 ohci->done = addr; 1115 i = OHCI_BM(td.flags, TD_DI); 1116 if (i < ohci->done_count) 1117 ohci->done_count = i; 1118 exit_no_retire: 1119 if (ohci_put_td(ohci, addr, &td)) { 1120 ohci_die(ohci); 1121 return 1; 1122 } 1123 return OHCI_BM(td.flags, TD_CC) != OHCI_CC_NOERROR; 1124 } 1125 1126 /* Service an endpoint list. Returns nonzero if active TD were found. */ 1127 static int ohci_service_ed_list(OHCIState *ohci, uint32_t head, int completion) 1128 { 1129 struct ohci_ed ed; 1130 uint32_t next_ed; 1131 uint32_t cur; 1132 int active; 1133 uint32_t link_cnt = 0; 1134 active = 0; 1135 1136 if (head == 0) 1137 return 0; 1138 1139 for (cur = head; cur && link_cnt++ < ED_LINK_LIMIT; cur = next_ed) { 1140 if (ohci_read_ed(ohci, cur, &ed)) { 1141 trace_usb_ohci_ed_read_error(cur); 1142 ohci_die(ohci); 1143 return 0; 1144 } 1145 1146 next_ed = ed.next & OHCI_DPTR_MASK; 1147 1148 if ((ed.head & OHCI_ED_H) || (ed.flags & OHCI_ED_K)) { 1149 uint32_t addr; 1150 /* Cancel pending packets for ED that have been paused. */ 1151 addr = ed.head & OHCI_DPTR_MASK; 1152 if (ohci->async_td && addr == ohci->async_td) { 1153 usb_cancel_packet(&ohci->usb_packet); 1154 ohci->async_td = 0; 1155 usb_device_ep_stopped(ohci->usb_packet.ep->dev, 1156 ohci->usb_packet.ep); 1157 } 1158 continue; 1159 } 1160 1161 while ((ed.head & OHCI_DPTR_MASK) != ed.tail) { 1162 trace_usb_ohci_ed_pkt(cur, (ed.head & OHCI_ED_H) != 0, 1163 (ed.head & OHCI_ED_C) != 0, ed.head & OHCI_DPTR_MASK, 1164 ed.tail & OHCI_DPTR_MASK, ed.next & OHCI_DPTR_MASK); 1165 trace_usb_ohci_ed_pkt_flags( 1166 OHCI_BM(ed.flags, ED_FA), OHCI_BM(ed.flags, ED_EN), 1167 OHCI_BM(ed.flags, ED_D), (ed.flags & OHCI_ED_S)!= 0, 1168 (ed.flags & OHCI_ED_K) != 0, (ed.flags & OHCI_ED_F) != 0, 1169 OHCI_BM(ed.flags, ED_MPS)); 1170 1171 active = 1; 1172 1173 if ((ed.flags & OHCI_ED_F) == 0) { 1174 if (ohci_service_td(ohci, &ed)) 1175 break; 1176 } else { 1177 /* Handle isochronous endpoints */ 1178 if (ohci_service_iso_td(ohci, &ed, completion)) 1179 break; 1180 } 1181 } 1182 1183 if (ohci_put_ed(ohci, cur, &ed)) { 1184 ohci_die(ohci); 1185 return 0; 1186 } 1187 } 1188 1189 return active; 1190 } 1191 1192 /* set a timer for EOF */ 1193 static void ohci_eof_timer(OHCIState *ohci) 1194 { 1195 timer_mod(ohci->eof_timer, ohci->sof_time + usb_frame_time); 1196 } 1197 /* Set a timer for EOF and generate a SOF event */ 1198 static void ohci_sof(OHCIState *ohci) 1199 { 1200 ohci->sof_time += usb_frame_time; 1201 ohci_eof_timer(ohci); 1202 ohci_set_interrupt(ohci, OHCI_INTR_SF); 1203 } 1204 1205 /* Process Control and Bulk lists. */ 1206 static void ohci_process_lists(OHCIState *ohci, int completion) 1207 { 1208 if ((ohci->ctl & OHCI_CTL_CLE) && (ohci->status & OHCI_STATUS_CLF)) { 1209 if (ohci->ctrl_cur && ohci->ctrl_cur != ohci->ctrl_head) { 1210 trace_usb_ohci_process_lists(ohci->ctrl_head, ohci->ctrl_cur); 1211 } 1212 if (!ohci_service_ed_list(ohci, ohci->ctrl_head, completion)) { 1213 ohci->ctrl_cur = 0; 1214 ohci->status &= ~OHCI_STATUS_CLF; 1215 } 1216 } 1217 1218 if ((ohci->ctl & OHCI_CTL_BLE) && (ohci->status & OHCI_STATUS_BLF)) { 1219 if (!ohci_service_ed_list(ohci, ohci->bulk_head, completion)) { 1220 ohci->bulk_cur = 0; 1221 ohci->status &= ~OHCI_STATUS_BLF; 1222 } 1223 } 1224 } 1225 1226 /* Do frame processing on frame boundary */ 1227 static void ohci_frame_boundary(void *opaque) 1228 { 1229 OHCIState *ohci = opaque; 1230 struct ohci_hcca hcca; 1231 1232 if (ohci_read_hcca(ohci, ohci->hcca, &hcca)) { 1233 trace_usb_ohci_hcca_read_error(ohci->hcca); 1234 ohci_die(ohci); 1235 return; 1236 } 1237 1238 /* Process all the lists at the end of the frame */ 1239 if (ohci->ctl & OHCI_CTL_PLE) { 1240 int n; 1241 1242 n = ohci->frame_number & 0x1f; 1243 ohci_service_ed_list(ohci, le32_to_cpu(hcca.intr[n]), 0); 1244 } 1245 1246 /* Cancel all pending packets if either of the lists has been disabled. */ 1247 if (ohci->old_ctl & (~ohci->ctl) & (OHCI_CTL_BLE | OHCI_CTL_CLE)) { 1248 if (ohci->async_td) { 1249 usb_cancel_packet(&ohci->usb_packet); 1250 ohci->async_td = 0; 1251 } 1252 ohci_stop_endpoints(ohci); 1253 } 1254 ohci->old_ctl = ohci->ctl; 1255 ohci_process_lists(ohci, 0); 1256 1257 /* Stop if UnrecoverableError happened or ohci_sof will crash */ 1258 if (ohci->intr_status & OHCI_INTR_UE) { 1259 return; 1260 } 1261 1262 /* Frame boundary, so do EOF stuf here */ 1263 ohci->frt = ohci->fit; 1264 1265 /* Increment frame number and take care of endianness. */ 1266 ohci->frame_number = (ohci->frame_number + 1) & 0xffff; 1267 hcca.frame = cpu_to_le16(ohci->frame_number); 1268 1269 if (ohci->done_count == 0 && !(ohci->intr_status & OHCI_INTR_WD)) { 1270 if (!ohci->done) 1271 abort(); 1272 if (ohci->intr & ohci->intr_status) 1273 ohci->done |= 1; 1274 hcca.done = cpu_to_le32(ohci->done); 1275 ohci->done = 0; 1276 ohci->done_count = 7; 1277 ohci_set_interrupt(ohci, OHCI_INTR_WD); 1278 } 1279 1280 if (ohci->done_count != 7 && ohci->done_count != 0) 1281 ohci->done_count--; 1282 1283 /* Do SOF stuff here */ 1284 ohci_sof(ohci); 1285 1286 /* Writeback HCCA */ 1287 if (ohci_put_hcca(ohci, ohci->hcca, &hcca)) { 1288 ohci_die(ohci); 1289 } 1290 } 1291 1292 /* Start sending SOF tokens across the USB bus, lists are processed in 1293 * next frame 1294 */ 1295 static int ohci_bus_start(OHCIState *ohci) 1296 { 1297 trace_usb_ohci_start(ohci->name); 1298 1299 /* Delay the first SOF event by one frame time as 1300 * linux driver is not ready to receive it and 1301 * can meet some race conditions 1302 */ 1303 1304 ohci->sof_time = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1305 ohci_eof_timer(ohci); 1306 1307 return 1; 1308 } 1309 1310 /* Stop sending SOF tokens on the bus */ 1311 void ohci_bus_stop(OHCIState *ohci) 1312 { 1313 trace_usb_ohci_stop(ohci->name); 1314 timer_del(ohci->eof_timer); 1315 } 1316 1317 /* Sets a flag in a port status register but only set it if the port is 1318 * connected, if not set ConnectStatusChange flag. If flag is enabled 1319 * return 1. 1320 */ 1321 static int ohci_port_set_if_connected(OHCIState *ohci, int i, uint32_t val) 1322 { 1323 int ret = 1; 1324 1325 /* writing a 0 has no effect */ 1326 if (val == 0) 1327 return 0; 1328 1329 /* If CurrentConnectStatus is cleared we set 1330 * ConnectStatusChange 1331 */ 1332 if (!(ohci->rhport[i].ctrl & OHCI_PORT_CCS)) { 1333 ohci->rhport[i].ctrl |= OHCI_PORT_CSC; 1334 if (ohci->rhstatus & OHCI_RHS_DRWE) { 1335 /* TODO: CSC is a wakeup event */ 1336 } 1337 return 0; 1338 } 1339 1340 if (ohci->rhport[i].ctrl & val) 1341 ret = 0; 1342 1343 /* set the bit */ 1344 ohci->rhport[i].ctrl |= val; 1345 1346 return ret; 1347 } 1348 1349 /* Set the frame interval - frame interval toggle is manipulated by the hcd only */ 1350 static void ohci_set_frame_interval(OHCIState *ohci, uint16_t val) 1351 { 1352 val &= OHCI_FMI_FI; 1353 1354 if (val != ohci->fi) { 1355 trace_usb_ohci_set_frame_interval(ohci->name, ohci->fi, ohci->fi); 1356 } 1357 1358 ohci->fi = val; 1359 } 1360 1361 static void ohci_port_power(OHCIState *ohci, int i, int p) 1362 { 1363 if (p) { 1364 ohci->rhport[i].ctrl |= OHCI_PORT_PPS; 1365 } else { 1366 ohci->rhport[i].ctrl &= ~(OHCI_PORT_PPS| 1367 OHCI_PORT_CCS| 1368 OHCI_PORT_PSS| 1369 OHCI_PORT_PRS); 1370 } 1371 } 1372 1373 /* Set HcControlRegister */ 1374 static void ohci_set_ctl(OHCIState *ohci, uint32_t val) 1375 { 1376 uint32_t old_state; 1377 uint32_t new_state; 1378 1379 old_state = ohci->ctl & OHCI_CTL_HCFS; 1380 ohci->ctl = val; 1381 new_state = ohci->ctl & OHCI_CTL_HCFS; 1382 1383 /* no state change */ 1384 if (old_state == new_state) 1385 return; 1386 1387 trace_usb_ohci_set_ctl(ohci->name, new_state); 1388 switch (new_state) { 1389 case OHCI_USB_OPERATIONAL: 1390 ohci_bus_start(ohci); 1391 break; 1392 case OHCI_USB_SUSPEND: 1393 ohci_bus_stop(ohci); 1394 /* clear pending SF otherwise linux driver loops in ohci_irq() */ 1395 ohci->intr_status &= ~OHCI_INTR_SF; 1396 ohci_intr_update(ohci); 1397 break; 1398 case OHCI_USB_RESUME: 1399 trace_usb_ohci_resume(ohci->name); 1400 break; 1401 case OHCI_USB_RESET: 1402 ohci_roothub_reset(ohci); 1403 break; 1404 } 1405 } 1406 1407 static uint32_t ohci_get_frame_remaining(OHCIState *ohci) 1408 { 1409 uint16_t fr; 1410 int64_t tks; 1411 1412 if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) 1413 return (ohci->frt << 31); 1414 1415 /* Being in USB operational state guarnatees sof_time was 1416 * set already. 1417 */ 1418 tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; 1419 if (tks < 0) { 1420 tks = 0; 1421 } 1422 1423 /* avoid muldiv if possible */ 1424 if (tks >= usb_frame_time) 1425 return (ohci->frt << 31); 1426 1427 tks = tks / usb_bit_time; 1428 fr = (uint16_t)(ohci->fi - tks); 1429 1430 return (ohci->frt << 31) | fr; 1431 } 1432 1433 1434 /* Set root hub status */ 1435 static void ohci_set_hub_status(OHCIState *ohci, uint32_t val) 1436 { 1437 uint32_t old_state; 1438 1439 old_state = ohci->rhstatus; 1440 1441 /* write 1 to clear OCIC */ 1442 if (val & OHCI_RHS_OCIC) 1443 ohci->rhstatus &= ~OHCI_RHS_OCIC; 1444 1445 if (val & OHCI_RHS_LPS) { 1446 int i; 1447 1448 for (i = 0; i < ohci->num_ports; i++) 1449 ohci_port_power(ohci, i, 0); 1450 trace_usb_ohci_hub_power_down(); 1451 } 1452 1453 if (val & OHCI_RHS_LPSC) { 1454 int i; 1455 1456 for (i = 0; i < ohci->num_ports; i++) 1457 ohci_port_power(ohci, i, 1); 1458 trace_usb_ohci_hub_power_up(); 1459 } 1460 1461 if (val & OHCI_RHS_DRWE) 1462 ohci->rhstatus |= OHCI_RHS_DRWE; 1463 1464 if (val & OHCI_RHS_CRWE) 1465 ohci->rhstatus &= ~OHCI_RHS_DRWE; 1466 1467 if (old_state != ohci->rhstatus) 1468 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1469 } 1470 1471 /* Set root hub port status */ 1472 static void ohci_port_set_status(OHCIState *ohci, int portnum, uint32_t val) 1473 { 1474 uint32_t old_state; 1475 OHCIPort *port; 1476 1477 port = &ohci->rhport[portnum]; 1478 old_state = port->ctrl; 1479 1480 /* Write to clear CSC, PESC, PSSC, OCIC, PRSC */ 1481 if (val & OHCI_PORT_WTC) 1482 port->ctrl &= ~(val & OHCI_PORT_WTC); 1483 1484 if (val & OHCI_PORT_CCS) 1485 port->ctrl &= ~OHCI_PORT_PES; 1486 1487 ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PES); 1488 1489 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PSS)) { 1490 trace_usb_ohci_port_suspend(portnum); 1491 } 1492 1493 if (ohci_port_set_if_connected(ohci, portnum, val & OHCI_PORT_PRS)) { 1494 trace_usb_ohci_port_reset(portnum); 1495 usb_device_reset(port->port.dev); 1496 port->ctrl &= ~OHCI_PORT_PRS; 1497 /* ??? Should this also set OHCI_PORT_PESC. */ 1498 port->ctrl |= OHCI_PORT_PES | OHCI_PORT_PRSC; 1499 } 1500 1501 /* Invert order here to ensure in ambiguous case, device is 1502 * powered up... 1503 */ 1504 if (val & OHCI_PORT_LSDA) 1505 ohci_port_power(ohci, portnum, 0); 1506 if (val & OHCI_PORT_PPS) 1507 ohci_port_power(ohci, portnum, 1); 1508 1509 if (old_state != port->ctrl) 1510 ohci_set_interrupt(ohci, OHCI_INTR_RHSC); 1511 } 1512 1513 static uint64_t ohci_mem_read(void *opaque, 1514 hwaddr addr, 1515 unsigned size) 1516 { 1517 OHCIState *ohci = opaque; 1518 uint32_t retval; 1519 1520 /* Only aligned reads are allowed on OHCI */ 1521 if (addr & 3) { 1522 trace_usb_ohci_mem_read_unaligned(addr); 1523 return 0xffffffff; 1524 } else if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1525 /* HcRhPortStatus */ 1526 retval = ohci->rhport[(addr - 0x54) >> 2].ctrl | OHCI_PORT_PPS; 1527 } else { 1528 switch (addr >> 2) { 1529 case 0: /* HcRevision */ 1530 retval = 0x10; 1531 break; 1532 1533 case 1: /* HcControl */ 1534 retval = ohci->ctl; 1535 break; 1536 1537 case 2: /* HcCommandStatus */ 1538 retval = ohci->status; 1539 break; 1540 1541 case 3: /* HcInterruptStatus */ 1542 retval = ohci->intr_status; 1543 break; 1544 1545 case 4: /* HcInterruptEnable */ 1546 case 5: /* HcInterruptDisable */ 1547 retval = ohci->intr; 1548 break; 1549 1550 case 6: /* HcHCCA */ 1551 retval = ohci->hcca; 1552 break; 1553 1554 case 7: /* HcPeriodCurrentED */ 1555 retval = ohci->per_cur; 1556 break; 1557 1558 case 8: /* HcControlHeadED */ 1559 retval = ohci->ctrl_head; 1560 break; 1561 1562 case 9: /* HcControlCurrentED */ 1563 retval = ohci->ctrl_cur; 1564 break; 1565 1566 case 10: /* HcBulkHeadED */ 1567 retval = ohci->bulk_head; 1568 break; 1569 1570 case 11: /* HcBulkCurrentED */ 1571 retval = ohci->bulk_cur; 1572 break; 1573 1574 case 12: /* HcDoneHead */ 1575 retval = ohci->done; 1576 break; 1577 1578 case 13: /* HcFmInterretval */ 1579 retval = (ohci->fit << 31) | (ohci->fsmps << 16) | (ohci->fi); 1580 break; 1581 1582 case 14: /* HcFmRemaining */ 1583 retval = ohci_get_frame_remaining(ohci); 1584 break; 1585 1586 case 15: /* HcFmNumber */ 1587 retval = ohci->frame_number; 1588 break; 1589 1590 case 16: /* HcPeriodicStart */ 1591 retval = ohci->pstart; 1592 break; 1593 1594 case 17: /* HcLSThreshold */ 1595 retval = ohci->lst; 1596 break; 1597 1598 case 18: /* HcRhDescriptorA */ 1599 retval = ohci->rhdesc_a; 1600 break; 1601 1602 case 19: /* HcRhDescriptorB */ 1603 retval = ohci->rhdesc_b; 1604 break; 1605 1606 case 20: /* HcRhStatus */ 1607 retval = ohci->rhstatus; 1608 break; 1609 1610 /* PXA27x specific registers */ 1611 case 24: /* HcStatus */ 1612 retval = ohci->hstatus & ohci->hmask; 1613 break; 1614 1615 case 25: /* HcHReset */ 1616 retval = ohci->hreset; 1617 break; 1618 1619 case 26: /* HcHInterruptEnable */ 1620 retval = ohci->hmask; 1621 break; 1622 1623 case 27: /* HcHInterruptTest */ 1624 retval = ohci->htest; 1625 break; 1626 1627 default: 1628 trace_usb_ohci_mem_read_bad_offset(addr); 1629 retval = 0xffffffff; 1630 } 1631 } 1632 1633 return retval; 1634 } 1635 1636 static void ohci_mem_write(void *opaque, 1637 hwaddr addr, 1638 uint64_t val, 1639 unsigned size) 1640 { 1641 OHCIState *ohci = opaque; 1642 1643 /* Only aligned reads are allowed on OHCI */ 1644 if (addr & 3) { 1645 trace_usb_ohci_mem_write_unaligned(addr); 1646 return; 1647 } 1648 1649 if (addr >= 0x54 && addr < 0x54 + ohci->num_ports * 4) { 1650 /* HcRhPortStatus */ 1651 ohci_port_set_status(ohci, (addr - 0x54) >> 2, val); 1652 return; 1653 } 1654 1655 switch (addr >> 2) { 1656 case 1: /* HcControl */ 1657 ohci_set_ctl(ohci, val); 1658 break; 1659 1660 case 2: /* HcCommandStatus */ 1661 /* SOC is read-only */ 1662 val = (val & ~OHCI_STATUS_SOC); 1663 1664 /* Bits written as '0' remain unchanged in the register */ 1665 ohci->status |= val; 1666 1667 if (ohci->status & OHCI_STATUS_HCR) 1668 ohci_soft_reset(ohci); 1669 break; 1670 1671 case 3: /* HcInterruptStatus */ 1672 ohci->intr_status &= ~val; 1673 ohci_intr_update(ohci); 1674 break; 1675 1676 case 4: /* HcInterruptEnable */ 1677 ohci->intr |= val; 1678 ohci_intr_update(ohci); 1679 break; 1680 1681 case 5: /* HcInterruptDisable */ 1682 ohci->intr &= ~val; 1683 ohci_intr_update(ohci); 1684 break; 1685 1686 case 6: /* HcHCCA */ 1687 ohci->hcca = val & OHCI_HCCA_MASK; 1688 break; 1689 1690 case 7: /* HcPeriodCurrentED */ 1691 /* Ignore writes to this read-only register, Linux does them */ 1692 break; 1693 1694 case 8: /* HcControlHeadED */ 1695 ohci->ctrl_head = val & OHCI_EDPTR_MASK; 1696 break; 1697 1698 case 9: /* HcControlCurrentED */ 1699 ohci->ctrl_cur = val & OHCI_EDPTR_MASK; 1700 break; 1701 1702 case 10: /* HcBulkHeadED */ 1703 ohci->bulk_head = val & OHCI_EDPTR_MASK; 1704 break; 1705 1706 case 11: /* HcBulkCurrentED */ 1707 ohci->bulk_cur = val & OHCI_EDPTR_MASK; 1708 break; 1709 1710 case 13: /* HcFmInterval */ 1711 ohci->fsmps = (val & OHCI_FMI_FSMPS) >> 16; 1712 ohci->fit = (val & OHCI_FMI_FIT) >> 31; 1713 ohci_set_frame_interval(ohci, val); 1714 break; 1715 1716 case 15: /* HcFmNumber */ 1717 break; 1718 1719 case 16: /* HcPeriodicStart */ 1720 ohci->pstart = val & 0xffff; 1721 break; 1722 1723 case 17: /* HcLSThreshold */ 1724 ohci->lst = val & 0xffff; 1725 break; 1726 1727 case 18: /* HcRhDescriptorA */ 1728 ohci->rhdesc_a &= ~OHCI_RHA_RW_MASK; 1729 ohci->rhdesc_a |= val & OHCI_RHA_RW_MASK; 1730 break; 1731 1732 case 19: /* HcRhDescriptorB */ 1733 break; 1734 1735 case 20: /* HcRhStatus */ 1736 ohci_set_hub_status(ohci, val); 1737 break; 1738 1739 /* PXA27x specific registers */ 1740 case 24: /* HcStatus */ 1741 ohci->hstatus &= ~(val & ohci->hmask); 1742 break; 1743 1744 case 25: /* HcHReset */ 1745 ohci->hreset = val & ~OHCI_HRESET_FSBIR; 1746 if (val & OHCI_HRESET_FSBIR) 1747 ohci_hard_reset(ohci); 1748 break; 1749 1750 case 26: /* HcHInterruptEnable */ 1751 ohci->hmask = val; 1752 break; 1753 1754 case 27: /* HcHInterruptTest */ 1755 ohci->htest = val; 1756 break; 1757 1758 default: 1759 trace_usb_ohci_mem_write_bad_offset(addr); 1760 break; 1761 } 1762 } 1763 1764 static void ohci_async_cancel_device(OHCIState *ohci, USBDevice *dev) 1765 { 1766 if (ohci->async_td && 1767 usb_packet_is_inflight(&ohci->usb_packet) && 1768 ohci->usb_packet.ep->dev == dev) { 1769 usb_cancel_packet(&ohci->usb_packet); 1770 ohci->async_td = 0; 1771 } 1772 } 1773 1774 static const MemoryRegionOps ohci_mem_ops = { 1775 .read = ohci_mem_read, 1776 .write = ohci_mem_write, 1777 .endianness = DEVICE_LITTLE_ENDIAN, 1778 }; 1779 1780 static USBPortOps ohci_port_ops = { 1781 .attach = ohci_attach, 1782 .detach = ohci_detach, 1783 .child_detach = ohci_child_detach, 1784 .wakeup = ohci_wakeup, 1785 .complete = ohci_async_complete_packet, 1786 }; 1787 1788 static USBBusOps ohci_bus_ops = { 1789 }; 1790 1791 void usb_ohci_init(OHCIState *ohci, DeviceState *dev, uint32_t num_ports, 1792 dma_addr_t localmem_base, char *masterbus, 1793 uint32_t firstport, AddressSpace *as, 1794 void (*ohci_die_fn)(struct OHCIState *), Error **errp) 1795 { 1796 Error *err = NULL; 1797 int i; 1798 1799 ohci->as = as; 1800 ohci->ohci_die = ohci_die_fn; 1801 1802 if (num_ports > OHCI_MAX_PORTS) { 1803 error_setg(errp, "OHCI num-ports=%u is too big (limit is %u ports)", 1804 num_ports, OHCI_MAX_PORTS); 1805 return; 1806 } 1807 1808 if (usb_frame_time == 0) { 1809 #ifdef OHCI_TIME_WARP 1810 usb_frame_time = NANOSECONDS_PER_SECOND; 1811 usb_bit_time = NANOSECONDS_PER_SECOND / (USB_HZ / 1000); 1812 #else 1813 usb_frame_time = NANOSECONDS_PER_SECOND / 1000; 1814 if (NANOSECONDS_PER_SECOND >= USB_HZ) { 1815 usb_bit_time = NANOSECONDS_PER_SECOND / USB_HZ; 1816 } else { 1817 usb_bit_time = 1; 1818 } 1819 #endif 1820 trace_usb_ohci_init_time(usb_frame_time, usb_bit_time); 1821 } 1822 1823 ohci->num_ports = num_ports; 1824 if (masterbus) { 1825 USBPort *ports[OHCI_MAX_PORTS]; 1826 for(i = 0; i < num_ports; i++) { 1827 ports[i] = &ohci->rhport[i].port; 1828 } 1829 usb_register_companion(masterbus, ports, num_ports, 1830 firstport, ohci, &ohci_port_ops, 1831 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL, 1832 &err); 1833 if (err) { 1834 error_propagate(errp, err); 1835 return; 1836 } 1837 } else { 1838 usb_bus_new(&ohci->bus, sizeof(ohci->bus), &ohci_bus_ops, dev); 1839 for (i = 0; i < num_ports; i++) { 1840 usb_register_port(&ohci->bus, &ohci->rhport[i].port, 1841 ohci, i, &ohci_port_ops, 1842 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL); 1843 } 1844 } 1845 1846 memory_region_init_io(&ohci->mem, OBJECT(dev), &ohci_mem_ops, 1847 ohci, "ohci", 256); 1848 ohci->localmem_base = localmem_base; 1849 1850 ohci->name = object_get_typename(OBJECT(dev)); 1851 usb_packet_init(&ohci->usb_packet); 1852 1853 ohci->async_td = 0; 1854 1855 ohci->eof_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, 1856 ohci_frame_boundary, ohci); 1857 } 1858 1859 /** 1860 * A typical OHCI will stop operating and set itself into error state 1861 * (which can be queried by MMIO) to signal that it got an error. 1862 */ 1863 void ohci_sysbus_die(struct OHCIState *ohci) 1864 { 1865 trace_usb_ohci_die(); 1866 1867 ohci_set_interrupt(ohci, OHCI_INTR_UE); 1868 ohci_bus_stop(ohci); 1869 } 1870 1871 #define TYPE_SYSBUS_OHCI "sysbus-ohci" 1872 #define SYSBUS_OHCI(obj) OBJECT_CHECK(OHCISysBusState, (obj), TYPE_SYSBUS_OHCI) 1873 1874 typedef struct { 1875 /*< private >*/ 1876 SysBusDevice parent_obj; 1877 /*< public >*/ 1878 1879 OHCIState ohci; 1880 char *masterbus; 1881 uint32_t num_ports; 1882 uint32_t firstport; 1883 dma_addr_t dma_offset; 1884 } OHCISysBusState; 1885 1886 static void ohci_realize_pxa(DeviceState *dev, Error **errp) 1887 { 1888 OHCISysBusState *s = SYSBUS_OHCI(dev); 1889 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 1890 Error *err = NULL; 1891 1892 usb_ohci_init(&s->ohci, dev, s->num_ports, s->dma_offset, 1893 s->masterbus, s->firstport, 1894 &address_space_memory, ohci_sysbus_die, &err); 1895 if (err) { 1896 error_propagate(errp, err); 1897 return; 1898 } 1899 sysbus_init_irq(sbd, &s->ohci.irq); 1900 sysbus_init_mmio(sbd, &s->ohci.mem); 1901 } 1902 1903 static void usb_ohci_reset_sysbus(DeviceState *dev) 1904 { 1905 OHCISysBusState *s = SYSBUS_OHCI(dev); 1906 OHCIState *ohci = &s->ohci; 1907 1908 ohci_hard_reset(ohci); 1909 } 1910 1911 static const VMStateDescription vmstate_ohci_state_port = { 1912 .name = "ohci-core/port", 1913 .version_id = 1, 1914 .minimum_version_id = 1, 1915 .fields = (VMStateField[]) { 1916 VMSTATE_UINT32(ctrl, OHCIPort), 1917 VMSTATE_END_OF_LIST() 1918 }, 1919 }; 1920 1921 static bool ohci_eof_timer_needed(void *opaque) 1922 { 1923 OHCIState *ohci = opaque; 1924 1925 return timer_pending(ohci->eof_timer); 1926 } 1927 1928 static const VMStateDescription vmstate_ohci_eof_timer = { 1929 .name = "ohci-core/eof-timer", 1930 .version_id = 1, 1931 .minimum_version_id = 1, 1932 .needed = ohci_eof_timer_needed, 1933 .fields = (VMStateField[]) { 1934 VMSTATE_TIMER_PTR(eof_timer, OHCIState), 1935 VMSTATE_END_OF_LIST() 1936 }, 1937 }; 1938 1939 const VMStateDescription vmstate_ohci_state = { 1940 .name = "ohci-core", 1941 .version_id = 1, 1942 .minimum_version_id = 1, 1943 .fields = (VMStateField[]) { 1944 VMSTATE_INT64(sof_time, OHCIState), 1945 VMSTATE_UINT32(ctl, OHCIState), 1946 VMSTATE_UINT32(status, OHCIState), 1947 VMSTATE_UINT32(intr_status, OHCIState), 1948 VMSTATE_UINT32(intr, OHCIState), 1949 VMSTATE_UINT32(hcca, OHCIState), 1950 VMSTATE_UINT32(ctrl_head, OHCIState), 1951 VMSTATE_UINT32(ctrl_cur, OHCIState), 1952 VMSTATE_UINT32(bulk_head, OHCIState), 1953 VMSTATE_UINT32(bulk_cur, OHCIState), 1954 VMSTATE_UINT32(per_cur, OHCIState), 1955 VMSTATE_UINT32(done, OHCIState), 1956 VMSTATE_INT32(done_count, OHCIState), 1957 VMSTATE_UINT16(fsmps, OHCIState), 1958 VMSTATE_UINT8(fit, OHCIState), 1959 VMSTATE_UINT16(fi, OHCIState), 1960 VMSTATE_UINT8(frt, OHCIState), 1961 VMSTATE_UINT16(frame_number, OHCIState), 1962 VMSTATE_UINT16(padding, OHCIState), 1963 VMSTATE_UINT32(pstart, OHCIState), 1964 VMSTATE_UINT32(lst, OHCIState), 1965 VMSTATE_UINT32(rhdesc_a, OHCIState), 1966 VMSTATE_UINT32(rhdesc_b, OHCIState), 1967 VMSTATE_UINT32(rhstatus, OHCIState), 1968 VMSTATE_STRUCT_ARRAY(rhport, OHCIState, OHCI_MAX_PORTS, 0, 1969 vmstate_ohci_state_port, OHCIPort), 1970 VMSTATE_UINT32(hstatus, OHCIState), 1971 VMSTATE_UINT32(hmask, OHCIState), 1972 VMSTATE_UINT32(hreset, OHCIState), 1973 VMSTATE_UINT32(htest, OHCIState), 1974 VMSTATE_UINT32(old_ctl, OHCIState), 1975 VMSTATE_UINT8_ARRAY(usb_buf, OHCIState, 8192), 1976 VMSTATE_UINT32(async_td, OHCIState), 1977 VMSTATE_BOOL(async_complete, OHCIState), 1978 VMSTATE_END_OF_LIST() 1979 }, 1980 .subsections = (const VMStateDescription*[]) { 1981 &vmstate_ohci_eof_timer, 1982 NULL 1983 } 1984 }; 1985 1986 static Property ohci_sysbus_properties[] = { 1987 DEFINE_PROP_STRING("masterbus", OHCISysBusState, masterbus), 1988 DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), 1989 DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0), 1990 DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0), 1991 DEFINE_PROP_END_OF_LIST(), 1992 }; 1993 1994 static void ohci_sysbus_class_init(ObjectClass *klass, void *data) 1995 { 1996 DeviceClass *dc = DEVICE_CLASS(klass); 1997 1998 dc->realize = ohci_realize_pxa; 1999 set_bit(DEVICE_CATEGORY_USB, dc->categories); 2000 dc->desc = "OHCI USB Controller"; 2001 dc->props = ohci_sysbus_properties; 2002 dc->reset = usb_ohci_reset_sysbus; 2003 } 2004 2005 static const TypeInfo ohci_sysbus_info = { 2006 .name = TYPE_SYSBUS_OHCI, 2007 .parent = TYPE_SYS_BUS_DEVICE, 2008 .instance_size = sizeof(OHCISysBusState), 2009 .class_init = ohci_sysbus_class_init, 2010 }; 2011 2012 static void ohci_register_types(void) 2013 { 2014 type_register_static(&ohci_sysbus_info); 2015 } 2016 2017 type_init(ohci_register_types) 2018