1 /* 2 * USB xHCI controller emulation 3 * 4 * Copyright (c) 2011 Securiforest 5 * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> 6 * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 7 * 8 * This library is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU Lesser General Public 10 * License as published by the Free Software Foundation; either 11 * version 2 of the License, or (at your option) any later version. 12 * 13 * This library is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 16 * Lesser General Public License for more details. 17 * 18 * You should have received a copy of the GNU Lesser General Public 19 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 #include "qemu/osdep.h" 22 #include "hw/hw.h" 23 #include "qemu/timer.h" 24 #include "qemu/queue.h" 25 #include "hw/usb.h" 26 #include "hw/pci/pci.h" 27 #include "hw/pci/msi.h" 28 #include "hw/pci/msix.h" 29 #include "trace.h" 30 #include "qapi/error.h" 31 32 //#define DEBUG_XHCI 33 //#define DEBUG_DATA 34 35 #ifdef DEBUG_XHCI 36 #define DPRINTF(...) fprintf(stderr, __VA_ARGS__) 37 #else 38 #define DPRINTF(...) do {} while (0) 39 #endif 40 #define FIXME(_msg) do { fprintf(stderr, "FIXME %s:%d %s\n", \ 41 __func__, __LINE__, _msg); abort(); } while (0) 42 43 #define MAXPORTS_2 15 44 #define MAXPORTS_3 15 45 46 #define MAXPORTS (MAXPORTS_2+MAXPORTS_3) 47 #define MAXSLOTS 64 48 #define MAXINTRS 16 49 50 /* Very pessimistic, let's hope it's enough for all cases */ 51 #define EV_QUEUE (((3 * 24) + 16) * MAXSLOTS) 52 53 #define TRB_LINK_LIMIT 4 54 #define COMMAND_LIMIT 256 55 #define TRANSFER_LIMIT 256 56 57 #define LEN_CAP 0x40 58 #define LEN_OPER (0x400 + 0x10 * MAXPORTS) 59 #define LEN_RUNTIME ((MAXINTRS + 1) * 0x20) 60 #define LEN_DOORBELL ((MAXSLOTS + 1) * 0x20) 61 62 #define OFF_OPER LEN_CAP 63 #define OFF_RUNTIME 0x1000 64 #define OFF_DOORBELL 0x2000 65 #define OFF_MSIX_TABLE 0x3000 66 #define OFF_MSIX_PBA 0x3800 67 /* must be power of 2 */ 68 #define LEN_REGS 0x4000 69 70 #if (OFF_OPER + LEN_OPER) > OFF_RUNTIME 71 #error Increase OFF_RUNTIME 72 #endif 73 #if (OFF_RUNTIME + LEN_RUNTIME) > OFF_DOORBELL 74 #error Increase OFF_DOORBELL 75 #endif 76 #if (OFF_DOORBELL + LEN_DOORBELL) > LEN_REGS 77 # error Increase LEN_REGS 78 #endif 79 80 /* bit definitions */ 81 #define USBCMD_RS (1<<0) 82 #define USBCMD_HCRST (1<<1) 83 #define USBCMD_INTE (1<<2) 84 #define USBCMD_HSEE (1<<3) 85 #define USBCMD_LHCRST (1<<7) 86 #define USBCMD_CSS (1<<8) 87 #define USBCMD_CRS (1<<9) 88 #define USBCMD_EWE (1<<10) 89 #define USBCMD_EU3S (1<<11) 90 91 #define USBSTS_HCH (1<<0) 92 #define USBSTS_HSE (1<<2) 93 #define USBSTS_EINT (1<<3) 94 #define USBSTS_PCD (1<<4) 95 #define USBSTS_SSS (1<<8) 96 #define USBSTS_RSS (1<<9) 97 #define USBSTS_SRE (1<<10) 98 #define USBSTS_CNR (1<<11) 99 #define USBSTS_HCE (1<<12) 100 101 102 #define PORTSC_CCS (1<<0) 103 #define PORTSC_PED (1<<1) 104 #define PORTSC_OCA (1<<3) 105 #define PORTSC_PR (1<<4) 106 #define PORTSC_PLS_SHIFT 5 107 #define PORTSC_PLS_MASK 0xf 108 #define PORTSC_PP (1<<9) 109 #define PORTSC_SPEED_SHIFT 10 110 #define PORTSC_SPEED_MASK 0xf 111 #define PORTSC_SPEED_FULL (1<<10) 112 #define PORTSC_SPEED_LOW (2<<10) 113 #define PORTSC_SPEED_HIGH (3<<10) 114 #define PORTSC_SPEED_SUPER (4<<10) 115 #define PORTSC_PIC_SHIFT 14 116 #define PORTSC_PIC_MASK 0x3 117 #define PORTSC_LWS (1<<16) 118 #define PORTSC_CSC (1<<17) 119 #define PORTSC_PEC (1<<18) 120 #define PORTSC_WRC (1<<19) 121 #define PORTSC_OCC (1<<20) 122 #define PORTSC_PRC (1<<21) 123 #define PORTSC_PLC (1<<22) 124 #define PORTSC_CEC (1<<23) 125 #define PORTSC_CAS (1<<24) 126 #define PORTSC_WCE (1<<25) 127 #define PORTSC_WDE (1<<26) 128 #define PORTSC_WOE (1<<27) 129 #define PORTSC_DR (1<<30) 130 #define PORTSC_WPR (1<<31) 131 132 #define CRCR_RCS (1<<0) 133 #define CRCR_CS (1<<1) 134 #define CRCR_CA (1<<2) 135 #define CRCR_CRR (1<<3) 136 137 #define IMAN_IP (1<<0) 138 #define IMAN_IE (1<<1) 139 140 #define ERDP_EHB (1<<3) 141 142 #define TRB_SIZE 16 143 typedef struct XHCITRB { 144 uint64_t parameter; 145 uint32_t status; 146 uint32_t control; 147 dma_addr_t addr; 148 bool ccs; 149 } XHCITRB; 150 151 enum { 152 PLS_U0 = 0, 153 PLS_U1 = 1, 154 PLS_U2 = 2, 155 PLS_U3 = 3, 156 PLS_DISABLED = 4, 157 PLS_RX_DETECT = 5, 158 PLS_INACTIVE = 6, 159 PLS_POLLING = 7, 160 PLS_RECOVERY = 8, 161 PLS_HOT_RESET = 9, 162 PLS_COMPILANCE_MODE = 10, 163 PLS_TEST_MODE = 11, 164 PLS_RESUME = 15, 165 }; 166 167 typedef enum TRBType { 168 TRB_RESERVED = 0, 169 TR_NORMAL, 170 TR_SETUP, 171 TR_DATA, 172 TR_STATUS, 173 TR_ISOCH, 174 TR_LINK, 175 TR_EVDATA, 176 TR_NOOP, 177 CR_ENABLE_SLOT, 178 CR_DISABLE_SLOT, 179 CR_ADDRESS_DEVICE, 180 CR_CONFIGURE_ENDPOINT, 181 CR_EVALUATE_CONTEXT, 182 CR_RESET_ENDPOINT, 183 CR_STOP_ENDPOINT, 184 CR_SET_TR_DEQUEUE, 185 CR_RESET_DEVICE, 186 CR_FORCE_EVENT, 187 CR_NEGOTIATE_BW, 188 CR_SET_LATENCY_TOLERANCE, 189 CR_GET_PORT_BANDWIDTH, 190 CR_FORCE_HEADER, 191 CR_NOOP, 192 ER_TRANSFER = 32, 193 ER_COMMAND_COMPLETE, 194 ER_PORT_STATUS_CHANGE, 195 ER_BANDWIDTH_REQUEST, 196 ER_DOORBELL, 197 ER_HOST_CONTROLLER, 198 ER_DEVICE_NOTIFICATION, 199 ER_MFINDEX_WRAP, 200 /* vendor specific bits */ 201 CR_VENDOR_NEC_FIRMWARE_REVISION = 49, 202 CR_VENDOR_NEC_CHALLENGE_RESPONSE = 50, 203 } TRBType; 204 205 #define CR_LINK TR_LINK 206 207 typedef enum TRBCCode { 208 CC_INVALID = 0, 209 CC_SUCCESS, 210 CC_DATA_BUFFER_ERROR, 211 CC_BABBLE_DETECTED, 212 CC_USB_TRANSACTION_ERROR, 213 CC_TRB_ERROR, 214 CC_STALL_ERROR, 215 CC_RESOURCE_ERROR, 216 CC_BANDWIDTH_ERROR, 217 CC_NO_SLOTS_ERROR, 218 CC_INVALID_STREAM_TYPE_ERROR, 219 CC_SLOT_NOT_ENABLED_ERROR, 220 CC_EP_NOT_ENABLED_ERROR, 221 CC_SHORT_PACKET, 222 CC_RING_UNDERRUN, 223 CC_RING_OVERRUN, 224 CC_VF_ER_FULL, 225 CC_PARAMETER_ERROR, 226 CC_BANDWIDTH_OVERRUN, 227 CC_CONTEXT_STATE_ERROR, 228 CC_NO_PING_RESPONSE_ERROR, 229 CC_EVENT_RING_FULL_ERROR, 230 CC_INCOMPATIBLE_DEVICE_ERROR, 231 CC_MISSED_SERVICE_ERROR, 232 CC_COMMAND_RING_STOPPED, 233 CC_COMMAND_ABORTED, 234 CC_STOPPED, 235 CC_STOPPED_LENGTH_INVALID, 236 CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR = 29, 237 CC_ISOCH_BUFFER_OVERRUN = 31, 238 CC_EVENT_LOST_ERROR, 239 CC_UNDEFINED_ERROR, 240 CC_INVALID_STREAM_ID_ERROR, 241 CC_SECONDARY_BANDWIDTH_ERROR, 242 CC_SPLIT_TRANSACTION_ERROR 243 } TRBCCode; 244 245 #define TRB_C (1<<0) 246 #define TRB_TYPE_SHIFT 10 247 #define TRB_TYPE_MASK 0x3f 248 #define TRB_TYPE(t) (((t).control >> TRB_TYPE_SHIFT) & TRB_TYPE_MASK) 249 250 #define TRB_EV_ED (1<<2) 251 252 #define TRB_TR_ENT (1<<1) 253 #define TRB_TR_ISP (1<<2) 254 #define TRB_TR_NS (1<<3) 255 #define TRB_TR_CH (1<<4) 256 #define TRB_TR_IOC (1<<5) 257 #define TRB_TR_IDT (1<<6) 258 #define TRB_TR_TBC_SHIFT 7 259 #define TRB_TR_TBC_MASK 0x3 260 #define TRB_TR_BEI (1<<9) 261 #define TRB_TR_TLBPC_SHIFT 16 262 #define TRB_TR_TLBPC_MASK 0xf 263 #define TRB_TR_FRAMEID_SHIFT 20 264 #define TRB_TR_FRAMEID_MASK 0x7ff 265 #define TRB_TR_SIA (1<<31) 266 267 #define TRB_TR_DIR (1<<16) 268 269 #define TRB_CR_SLOTID_SHIFT 24 270 #define TRB_CR_SLOTID_MASK 0xff 271 #define TRB_CR_EPID_SHIFT 16 272 #define TRB_CR_EPID_MASK 0x1f 273 274 #define TRB_CR_BSR (1<<9) 275 #define TRB_CR_DC (1<<9) 276 277 #define TRB_LK_TC (1<<1) 278 279 #define TRB_INTR_SHIFT 22 280 #define TRB_INTR_MASK 0x3ff 281 #define TRB_INTR(t) (((t).status >> TRB_INTR_SHIFT) & TRB_INTR_MASK) 282 283 #define EP_TYPE_MASK 0x7 284 #define EP_TYPE_SHIFT 3 285 286 #define EP_STATE_MASK 0x7 287 #define EP_DISABLED (0<<0) 288 #define EP_RUNNING (1<<0) 289 #define EP_HALTED (2<<0) 290 #define EP_STOPPED (3<<0) 291 #define EP_ERROR (4<<0) 292 293 #define SLOT_STATE_MASK 0x1f 294 #define SLOT_STATE_SHIFT 27 295 #define SLOT_STATE(s) (((s)>>SLOT_STATE_SHIFT)&SLOT_STATE_MASK) 296 #define SLOT_ENABLED 0 297 #define SLOT_DEFAULT 1 298 #define SLOT_ADDRESSED 2 299 #define SLOT_CONFIGURED 3 300 301 #define SLOT_CONTEXT_ENTRIES_MASK 0x1f 302 #define SLOT_CONTEXT_ENTRIES_SHIFT 27 303 304 typedef struct XHCIState XHCIState; 305 typedef struct XHCIStreamContext XHCIStreamContext; 306 typedef struct XHCIEPContext XHCIEPContext; 307 308 #define get_field(data, field) \ 309 (((data) >> field##_SHIFT) & field##_MASK) 310 311 #define set_field(data, newval, field) do { \ 312 uint32_t val = *data; \ 313 val &= ~(field##_MASK << field##_SHIFT); \ 314 val |= ((newval) & field##_MASK) << field##_SHIFT; \ 315 *data = val; \ 316 } while (0) 317 318 typedef enum EPType { 319 ET_INVALID = 0, 320 ET_ISO_OUT, 321 ET_BULK_OUT, 322 ET_INTR_OUT, 323 ET_CONTROL, 324 ET_ISO_IN, 325 ET_BULK_IN, 326 ET_INTR_IN, 327 } EPType; 328 329 typedef struct XHCIRing { 330 dma_addr_t dequeue; 331 bool ccs; 332 } XHCIRing; 333 334 typedef struct XHCIPort { 335 XHCIState *xhci; 336 uint32_t portsc; 337 uint32_t portnr; 338 USBPort *uport; 339 uint32_t speedmask; 340 char name[16]; 341 MemoryRegion mem; 342 } XHCIPort; 343 344 typedef struct XHCITransfer { 345 XHCIEPContext *epctx; 346 USBPacket packet; 347 QEMUSGList sgl; 348 bool running_async; 349 bool running_retry; 350 bool complete; 351 bool int_req; 352 unsigned int iso_pkts; 353 unsigned int streamid; 354 bool in_xfer; 355 bool iso_xfer; 356 bool timed_xfer; 357 358 unsigned int trb_count; 359 XHCITRB *trbs; 360 361 TRBCCode status; 362 363 unsigned int pkts; 364 unsigned int pktsize; 365 unsigned int cur_pkt; 366 367 uint64_t mfindex_kick; 368 369 QTAILQ_ENTRY(XHCITransfer) next; 370 } XHCITransfer; 371 372 struct XHCIStreamContext { 373 dma_addr_t pctx; 374 unsigned int sct; 375 XHCIRing ring; 376 }; 377 378 struct XHCIEPContext { 379 XHCIState *xhci; 380 unsigned int slotid; 381 unsigned int epid; 382 383 XHCIRing ring; 384 uint32_t xfer_count; 385 QTAILQ_HEAD(, XHCITransfer) transfers; 386 XHCITransfer *retry; 387 EPType type; 388 dma_addr_t pctx; 389 unsigned int max_psize; 390 uint32_t state; 391 uint32_t kick_active; 392 393 /* streams */ 394 unsigned int max_pstreams; 395 bool lsa; 396 unsigned int nr_pstreams; 397 XHCIStreamContext *pstreams; 398 399 /* iso xfer scheduling */ 400 unsigned int interval; 401 int64_t mfindex_last; 402 QEMUTimer *kick_timer; 403 }; 404 405 typedef struct XHCISlot { 406 bool enabled; 407 bool addressed; 408 dma_addr_t ctx; 409 USBPort *uport; 410 XHCIEPContext * eps[31]; 411 } XHCISlot; 412 413 typedef struct XHCIEvent { 414 TRBType type; 415 TRBCCode ccode; 416 uint64_t ptr; 417 uint32_t length; 418 uint32_t flags; 419 uint8_t slotid; 420 uint8_t epid; 421 } XHCIEvent; 422 423 typedef struct XHCIInterrupter { 424 uint32_t iman; 425 uint32_t imod; 426 uint32_t erstsz; 427 uint32_t erstba_low; 428 uint32_t erstba_high; 429 uint32_t erdp_low; 430 uint32_t erdp_high; 431 432 bool msix_used, er_pcs; 433 434 dma_addr_t er_start; 435 uint32_t er_size; 436 unsigned int er_ep_idx; 437 438 /* kept for live migration compat only */ 439 bool er_full_unused; 440 XHCIEvent ev_buffer[EV_QUEUE]; 441 unsigned int ev_buffer_put; 442 unsigned int ev_buffer_get; 443 444 } XHCIInterrupter; 445 446 struct XHCIState { 447 /*< private >*/ 448 PCIDevice parent_obj; 449 /*< public >*/ 450 451 USBBus bus; 452 MemoryRegion mem; 453 MemoryRegion mem_cap; 454 MemoryRegion mem_oper; 455 MemoryRegion mem_runtime; 456 MemoryRegion mem_doorbell; 457 458 /* properties */ 459 uint32_t numports_2; 460 uint32_t numports_3; 461 uint32_t numintrs; 462 uint32_t numslots; 463 uint32_t flags; 464 uint32_t max_pstreams_mask; 465 OnOffAuto msi; 466 OnOffAuto msix; 467 468 /* Operational Registers */ 469 uint32_t usbcmd; 470 uint32_t usbsts; 471 uint32_t dnctrl; 472 uint32_t crcr_low; 473 uint32_t crcr_high; 474 uint32_t dcbaap_low; 475 uint32_t dcbaap_high; 476 uint32_t config; 477 478 USBPort uports[MAX(MAXPORTS_2, MAXPORTS_3)]; 479 XHCIPort ports[MAXPORTS]; 480 XHCISlot slots[MAXSLOTS]; 481 uint32_t numports; 482 483 /* Runtime Registers */ 484 int64_t mfindex_start; 485 QEMUTimer *mfwrap_timer; 486 XHCIInterrupter intr[MAXINTRS]; 487 488 XHCIRing cmd_ring; 489 490 bool nec_quirks; 491 }; 492 493 #define TYPE_XHCI "base-xhci" 494 #define TYPE_NEC_XHCI "nec-usb-xhci" 495 #define TYPE_QEMU_XHCI "qemu-xhci" 496 497 #define XHCI(obj) \ 498 OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI) 499 500 typedef struct XHCIEvRingSeg { 501 uint32_t addr_low; 502 uint32_t addr_high; 503 uint32_t size; 504 uint32_t rsvd; 505 } XHCIEvRingSeg; 506 507 enum xhci_flags { 508 XHCI_FLAG_SS_FIRST = 1, 509 XHCI_FLAG_FORCE_PCIE_ENDCAP, 510 XHCI_FLAG_ENABLE_STREAMS, 511 }; 512 513 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 514 unsigned int epid, unsigned int streamid); 515 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid); 516 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 517 unsigned int epid); 518 static void xhci_xfer_report(XHCITransfer *xfer); 519 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v); 520 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v); 521 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx); 522 523 static const char *TRBType_names[] = { 524 [TRB_RESERVED] = "TRB_RESERVED", 525 [TR_NORMAL] = "TR_NORMAL", 526 [TR_SETUP] = "TR_SETUP", 527 [TR_DATA] = "TR_DATA", 528 [TR_STATUS] = "TR_STATUS", 529 [TR_ISOCH] = "TR_ISOCH", 530 [TR_LINK] = "TR_LINK", 531 [TR_EVDATA] = "TR_EVDATA", 532 [TR_NOOP] = "TR_NOOP", 533 [CR_ENABLE_SLOT] = "CR_ENABLE_SLOT", 534 [CR_DISABLE_SLOT] = "CR_DISABLE_SLOT", 535 [CR_ADDRESS_DEVICE] = "CR_ADDRESS_DEVICE", 536 [CR_CONFIGURE_ENDPOINT] = "CR_CONFIGURE_ENDPOINT", 537 [CR_EVALUATE_CONTEXT] = "CR_EVALUATE_CONTEXT", 538 [CR_RESET_ENDPOINT] = "CR_RESET_ENDPOINT", 539 [CR_STOP_ENDPOINT] = "CR_STOP_ENDPOINT", 540 [CR_SET_TR_DEQUEUE] = "CR_SET_TR_DEQUEUE", 541 [CR_RESET_DEVICE] = "CR_RESET_DEVICE", 542 [CR_FORCE_EVENT] = "CR_FORCE_EVENT", 543 [CR_NEGOTIATE_BW] = "CR_NEGOTIATE_BW", 544 [CR_SET_LATENCY_TOLERANCE] = "CR_SET_LATENCY_TOLERANCE", 545 [CR_GET_PORT_BANDWIDTH] = "CR_GET_PORT_BANDWIDTH", 546 [CR_FORCE_HEADER] = "CR_FORCE_HEADER", 547 [CR_NOOP] = "CR_NOOP", 548 [ER_TRANSFER] = "ER_TRANSFER", 549 [ER_COMMAND_COMPLETE] = "ER_COMMAND_COMPLETE", 550 [ER_PORT_STATUS_CHANGE] = "ER_PORT_STATUS_CHANGE", 551 [ER_BANDWIDTH_REQUEST] = "ER_BANDWIDTH_REQUEST", 552 [ER_DOORBELL] = "ER_DOORBELL", 553 [ER_HOST_CONTROLLER] = "ER_HOST_CONTROLLER", 554 [ER_DEVICE_NOTIFICATION] = "ER_DEVICE_NOTIFICATION", 555 [ER_MFINDEX_WRAP] = "ER_MFINDEX_WRAP", 556 [CR_VENDOR_NEC_FIRMWARE_REVISION] = "CR_VENDOR_NEC_FIRMWARE_REVISION", 557 [CR_VENDOR_NEC_CHALLENGE_RESPONSE] = "CR_VENDOR_NEC_CHALLENGE_RESPONSE", 558 }; 559 560 static const char *TRBCCode_names[] = { 561 [CC_INVALID] = "CC_INVALID", 562 [CC_SUCCESS] = "CC_SUCCESS", 563 [CC_DATA_BUFFER_ERROR] = "CC_DATA_BUFFER_ERROR", 564 [CC_BABBLE_DETECTED] = "CC_BABBLE_DETECTED", 565 [CC_USB_TRANSACTION_ERROR] = "CC_USB_TRANSACTION_ERROR", 566 [CC_TRB_ERROR] = "CC_TRB_ERROR", 567 [CC_STALL_ERROR] = "CC_STALL_ERROR", 568 [CC_RESOURCE_ERROR] = "CC_RESOURCE_ERROR", 569 [CC_BANDWIDTH_ERROR] = "CC_BANDWIDTH_ERROR", 570 [CC_NO_SLOTS_ERROR] = "CC_NO_SLOTS_ERROR", 571 [CC_INVALID_STREAM_TYPE_ERROR] = "CC_INVALID_STREAM_TYPE_ERROR", 572 [CC_SLOT_NOT_ENABLED_ERROR] = "CC_SLOT_NOT_ENABLED_ERROR", 573 [CC_EP_NOT_ENABLED_ERROR] = "CC_EP_NOT_ENABLED_ERROR", 574 [CC_SHORT_PACKET] = "CC_SHORT_PACKET", 575 [CC_RING_UNDERRUN] = "CC_RING_UNDERRUN", 576 [CC_RING_OVERRUN] = "CC_RING_OVERRUN", 577 [CC_VF_ER_FULL] = "CC_VF_ER_FULL", 578 [CC_PARAMETER_ERROR] = "CC_PARAMETER_ERROR", 579 [CC_BANDWIDTH_OVERRUN] = "CC_BANDWIDTH_OVERRUN", 580 [CC_CONTEXT_STATE_ERROR] = "CC_CONTEXT_STATE_ERROR", 581 [CC_NO_PING_RESPONSE_ERROR] = "CC_NO_PING_RESPONSE_ERROR", 582 [CC_EVENT_RING_FULL_ERROR] = "CC_EVENT_RING_FULL_ERROR", 583 [CC_INCOMPATIBLE_DEVICE_ERROR] = "CC_INCOMPATIBLE_DEVICE_ERROR", 584 [CC_MISSED_SERVICE_ERROR] = "CC_MISSED_SERVICE_ERROR", 585 [CC_COMMAND_RING_STOPPED] = "CC_COMMAND_RING_STOPPED", 586 [CC_COMMAND_ABORTED] = "CC_COMMAND_ABORTED", 587 [CC_STOPPED] = "CC_STOPPED", 588 [CC_STOPPED_LENGTH_INVALID] = "CC_STOPPED_LENGTH_INVALID", 589 [CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR] 590 = "CC_MAX_EXIT_LATENCY_TOO_LARGE_ERROR", 591 [CC_ISOCH_BUFFER_OVERRUN] = "CC_ISOCH_BUFFER_OVERRUN", 592 [CC_EVENT_LOST_ERROR] = "CC_EVENT_LOST_ERROR", 593 [CC_UNDEFINED_ERROR] = "CC_UNDEFINED_ERROR", 594 [CC_INVALID_STREAM_ID_ERROR] = "CC_INVALID_STREAM_ID_ERROR", 595 [CC_SECONDARY_BANDWIDTH_ERROR] = "CC_SECONDARY_BANDWIDTH_ERROR", 596 [CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR", 597 }; 598 599 static const char *ep_state_names[] = { 600 [EP_DISABLED] = "disabled", 601 [EP_RUNNING] = "running", 602 [EP_HALTED] = "halted", 603 [EP_STOPPED] = "stopped", 604 [EP_ERROR] = "error", 605 }; 606 607 static const char *lookup_name(uint32_t index, const char **list, uint32_t llen) 608 { 609 if (index >= llen || list[index] == NULL) { 610 return "???"; 611 } 612 return list[index]; 613 } 614 615 static const char *trb_name(XHCITRB *trb) 616 { 617 return lookup_name(TRB_TYPE(*trb), TRBType_names, 618 ARRAY_SIZE(TRBType_names)); 619 } 620 621 static const char *event_name(XHCIEvent *event) 622 { 623 return lookup_name(event->ccode, TRBCCode_names, 624 ARRAY_SIZE(TRBCCode_names)); 625 } 626 627 static const char *ep_state_name(uint32_t state) 628 { 629 return lookup_name(state, ep_state_names, 630 ARRAY_SIZE(ep_state_names)); 631 } 632 633 static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) 634 { 635 return xhci->flags & (1 << bit); 636 } 637 638 static uint64_t xhci_mfindex_get(XHCIState *xhci) 639 { 640 int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 641 return (now - xhci->mfindex_start) / 125000; 642 } 643 644 static void xhci_mfwrap_update(XHCIState *xhci) 645 { 646 const uint32_t bits = USBCMD_RS | USBCMD_EWE; 647 uint32_t mfindex, left; 648 int64_t now; 649 650 if ((xhci->usbcmd & bits) == bits) { 651 now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 652 mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff; 653 left = 0x4000 - mfindex; 654 timer_mod(xhci->mfwrap_timer, now + left * 125000); 655 } else { 656 timer_del(xhci->mfwrap_timer); 657 } 658 } 659 660 static void xhci_mfwrap_timer(void *opaque) 661 { 662 XHCIState *xhci = opaque; 663 XHCIEvent wrap = { ER_MFINDEX_WRAP, CC_SUCCESS }; 664 665 xhci_event(xhci, &wrap, 0); 666 xhci_mfwrap_update(xhci); 667 } 668 669 static inline dma_addr_t xhci_addr64(uint32_t low, uint32_t high) 670 { 671 if (sizeof(dma_addr_t) == 4) { 672 return low; 673 } else { 674 return low | (((dma_addr_t)high << 16) << 16); 675 } 676 } 677 678 static inline dma_addr_t xhci_mask64(uint64_t addr) 679 { 680 if (sizeof(dma_addr_t) == 4) { 681 return addr & 0xffffffff; 682 } else { 683 return addr; 684 } 685 } 686 687 static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, 688 uint32_t *buf, size_t len) 689 { 690 int i; 691 692 assert((len % sizeof(uint32_t)) == 0); 693 694 pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); 695 696 for (i = 0; i < (len / sizeof(uint32_t)); i++) { 697 buf[i] = le32_to_cpu(buf[i]); 698 } 699 } 700 701 static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, 702 uint32_t *buf, size_t len) 703 { 704 int i; 705 uint32_t tmp[5]; 706 uint32_t n = len / sizeof(uint32_t); 707 708 assert((len % sizeof(uint32_t)) == 0); 709 assert(n <= ARRAY_SIZE(tmp)); 710 711 for (i = 0; i < n; i++) { 712 tmp[i] = cpu_to_le32(buf[i]); 713 } 714 pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); 715 } 716 717 static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) 718 { 719 int index; 720 721 if (!uport->dev) { 722 return NULL; 723 } 724 switch (uport->dev->speed) { 725 case USB_SPEED_LOW: 726 case USB_SPEED_FULL: 727 case USB_SPEED_HIGH: 728 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 729 index = uport->index + xhci->numports_3; 730 } else { 731 index = uport->index; 732 } 733 break; 734 case USB_SPEED_SUPER: 735 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 736 index = uport->index; 737 } else { 738 index = uport->index + xhci->numports_2; 739 } 740 break; 741 default: 742 return NULL; 743 } 744 return &xhci->ports[index]; 745 } 746 747 static void xhci_intx_update(XHCIState *xhci) 748 { 749 PCIDevice *pci_dev = PCI_DEVICE(xhci); 750 int level = 0; 751 752 if (msix_enabled(pci_dev) || 753 msi_enabled(pci_dev)) { 754 return; 755 } 756 757 if (xhci->intr[0].iman & IMAN_IP && 758 xhci->intr[0].iman & IMAN_IE && 759 xhci->usbcmd & USBCMD_INTE) { 760 level = 1; 761 } 762 763 trace_usb_xhci_irq_intx(level); 764 pci_set_irq(pci_dev, level); 765 } 766 767 static void xhci_msix_update(XHCIState *xhci, int v) 768 { 769 PCIDevice *pci_dev = PCI_DEVICE(xhci); 770 bool enabled; 771 772 if (!msix_enabled(pci_dev)) { 773 return; 774 } 775 776 enabled = xhci->intr[v].iman & IMAN_IE; 777 if (enabled == xhci->intr[v].msix_used) { 778 return; 779 } 780 781 if (enabled) { 782 trace_usb_xhci_irq_msix_use(v); 783 msix_vector_use(pci_dev, v); 784 xhci->intr[v].msix_used = true; 785 } else { 786 trace_usb_xhci_irq_msix_unuse(v); 787 msix_vector_unuse(pci_dev, v); 788 xhci->intr[v].msix_used = false; 789 } 790 } 791 792 static void xhci_intr_raise(XHCIState *xhci, int v) 793 { 794 PCIDevice *pci_dev = PCI_DEVICE(xhci); 795 bool pending = (xhci->intr[v].erdp_low & ERDP_EHB); 796 797 xhci->intr[v].erdp_low |= ERDP_EHB; 798 xhci->intr[v].iman |= IMAN_IP; 799 xhci->usbsts |= USBSTS_EINT; 800 801 if (pending) { 802 return; 803 } 804 if (!(xhci->intr[v].iman & IMAN_IE)) { 805 return; 806 } 807 808 if (!(xhci->usbcmd & USBCMD_INTE)) { 809 return; 810 } 811 812 if (msix_enabled(pci_dev)) { 813 trace_usb_xhci_irq_msix(v); 814 msix_notify(pci_dev, v); 815 return; 816 } 817 818 if (msi_enabled(pci_dev)) { 819 trace_usb_xhci_irq_msi(v); 820 msi_notify(pci_dev, v); 821 return; 822 } 823 824 if (v == 0) { 825 trace_usb_xhci_irq_intx(1); 826 pci_irq_assert(pci_dev); 827 } 828 } 829 830 static inline int xhci_running(XHCIState *xhci) 831 { 832 return !(xhci->usbsts & USBSTS_HCH); 833 } 834 835 static void xhci_die(XHCIState *xhci) 836 { 837 xhci->usbsts |= USBSTS_HCE; 838 DPRINTF("xhci: asserted controller error\n"); 839 } 840 841 static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) 842 { 843 PCIDevice *pci_dev = PCI_DEVICE(xhci); 844 XHCIInterrupter *intr = &xhci->intr[v]; 845 XHCITRB ev_trb; 846 dma_addr_t addr; 847 848 ev_trb.parameter = cpu_to_le64(event->ptr); 849 ev_trb.status = cpu_to_le32(event->length | (event->ccode << 24)); 850 ev_trb.control = (event->slotid << 24) | (event->epid << 16) | 851 event->flags | (event->type << TRB_TYPE_SHIFT); 852 if (intr->er_pcs) { 853 ev_trb.control |= TRB_C; 854 } 855 ev_trb.control = cpu_to_le32(ev_trb.control); 856 857 trace_usb_xhci_queue_event(v, intr->er_ep_idx, trb_name(&ev_trb), 858 event_name(event), ev_trb.parameter, 859 ev_trb.status, ev_trb.control); 860 861 addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; 862 pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); 863 864 intr->er_ep_idx++; 865 if (intr->er_ep_idx >= intr->er_size) { 866 intr->er_ep_idx = 0; 867 intr->er_pcs = !intr->er_pcs; 868 } 869 } 870 871 static void xhci_event(XHCIState *xhci, XHCIEvent *event, int v) 872 { 873 XHCIInterrupter *intr; 874 dma_addr_t erdp; 875 unsigned int dp_idx; 876 877 if (v >= xhci->numintrs) { 878 DPRINTF("intr nr out of range (%d >= %d)\n", v, xhci->numintrs); 879 return; 880 } 881 intr = &xhci->intr[v]; 882 883 erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 884 if (erdp < intr->er_start || 885 erdp >= (intr->er_start + TRB_SIZE*intr->er_size)) { 886 DPRINTF("xhci: ERDP out of bounds: "DMA_ADDR_FMT"\n", erdp); 887 DPRINTF("xhci: ER[%d] at "DMA_ADDR_FMT" len %d\n", 888 v, intr->er_start, intr->er_size); 889 xhci_die(xhci); 890 return; 891 } 892 893 dp_idx = (erdp - intr->er_start) / TRB_SIZE; 894 assert(dp_idx < intr->er_size); 895 896 if ((intr->er_ep_idx + 2) % intr->er_size == dp_idx) { 897 DPRINTF("xhci: ER %d full, send ring full error\n", v); 898 XHCIEvent full = {ER_HOST_CONTROLLER, CC_EVENT_RING_FULL_ERROR}; 899 xhci_write_event(xhci, &full, v); 900 } else if ((intr->er_ep_idx + 1) % intr->er_size == dp_idx) { 901 DPRINTF("xhci: ER %d full, drop event\n", v); 902 } else { 903 xhci_write_event(xhci, event, v); 904 } 905 906 xhci_intr_raise(xhci, v); 907 } 908 909 static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, 910 dma_addr_t base) 911 { 912 ring->dequeue = base; 913 ring->ccs = 1; 914 } 915 916 static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, 917 dma_addr_t *addr) 918 { 919 PCIDevice *pci_dev = PCI_DEVICE(xhci); 920 uint32_t link_cnt = 0; 921 922 while (1) { 923 TRBType type; 924 pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); 925 trb->addr = ring->dequeue; 926 trb->ccs = ring->ccs; 927 le64_to_cpus(&trb->parameter); 928 le32_to_cpus(&trb->status); 929 le32_to_cpus(&trb->control); 930 931 trace_usb_xhci_fetch_trb(ring->dequeue, trb_name(trb), 932 trb->parameter, trb->status, trb->control); 933 934 if ((trb->control & TRB_C) != ring->ccs) { 935 return 0; 936 } 937 938 type = TRB_TYPE(*trb); 939 940 if (type != TR_LINK) { 941 if (addr) { 942 *addr = ring->dequeue; 943 } 944 ring->dequeue += TRB_SIZE; 945 return type; 946 } else { 947 if (++link_cnt > TRB_LINK_LIMIT) { 948 trace_usb_xhci_enforced_limit("trb-link"); 949 return 0; 950 } 951 ring->dequeue = xhci_mask64(trb->parameter); 952 if (trb->control & TRB_LK_TC) { 953 ring->ccs = !ring->ccs; 954 } 955 } 956 } 957 } 958 959 static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) 960 { 961 PCIDevice *pci_dev = PCI_DEVICE(xhci); 962 XHCITRB trb; 963 int length = 0; 964 dma_addr_t dequeue = ring->dequeue; 965 bool ccs = ring->ccs; 966 /* hack to bundle together the two/three TDs that make a setup transfer */ 967 bool control_td_set = 0; 968 uint32_t link_cnt = 0; 969 970 while (1) { 971 TRBType type; 972 pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); 973 le64_to_cpus(&trb.parameter); 974 le32_to_cpus(&trb.status); 975 le32_to_cpus(&trb.control); 976 977 if ((trb.control & TRB_C) != ccs) { 978 return -length; 979 } 980 981 type = TRB_TYPE(trb); 982 983 if (type == TR_LINK) { 984 if (++link_cnt > TRB_LINK_LIMIT) { 985 return -length; 986 } 987 dequeue = xhci_mask64(trb.parameter); 988 if (trb.control & TRB_LK_TC) { 989 ccs = !ccs; 990 } 991 continue; 992 } 993 994 length += 1; 995 dequeue += TRB_SIZE; 996 997 if (type == TR_SETUP) { 998 control_td_set = 1; 999 } else if (type == TR_STATUS) { 1000 control_td_set = 0; 1001 } 1002 1003 if (!control_td_set && !(trb.control & TRB_TR_CH)) { 1004 return length; 1005 } 1006 } 1007 } 1008 1009 static void xhci_er_reset(XHCIState *xhci, int v) 1010 { 1011 XHCIInterrupter *intr = &xhci->intr[v]; 1012 XHCIEvRingSeg seg; 1013 1014 if (intr->erstsz == 0) { 1015 /* disabled */ 1016 intr->er_start = 0; 1017 intr->er_size = 0; 1018 return; 1019 } 1020 /* cache the (sole) event ring segment location */ 1021 if (intr->erstsz != 1) { 1022 DPRINTF("xhci: invalid value for ERSTSZ: %d\n", intr->erstsz); 1023 xhci_die(xhci); 1024 return; 1025 } 1026 dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high); 1027 pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); 1028 le32_to_cpus(&seg.addr_low); 1029 le32_to_cpus(&seg.addr_high); 1030 le32_to_cpus(&seg.size); 1031 if (seg.size < 16 || seg.size > 4096) { 1032 DPRINTF("xhci: invalid value for segment size: %d\n", seg.size); 1033 xhci_die(xhci); 1034 return; 1035 } 1036 intr->er_start = xhci_addr64(seg.addr_low, seg.addr_high); 1037 intr->er_size = seg.size; 1038 1039 intr->er_ep_idx = 0; 1040 intr->er_pcs = 1; 1041 1042 DPRINTF("xhci: event ring[%d]:" DMA_ADDR_FMT " [%d]\n", 1043 v, intr->er_start, intr->er_size); 1044 } 1045 1046 static void xhci_run(XHCIState *xhci) 1047 { 1048 trace_usb_xhci_run(); 1049 xhci->usbsts &= ~USBSTS_HCH; 1050 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 1051 } 1052 1053 static void xhci_stop(XHCIState *xhci) 1054 { 1055 trace_usb_xhci_stop(); 1056 xhci->usbsts |= USBSTS_HCH; 1057 xhci->crcr_low &= ~CRCR_CRR; 1058 } 1059 1060 static XHCIStreamContext *xhci_alloc_stream_contexts(unsigned count, 1061 dma_addr_t base) 1062 { 1063 XHCIStreamContext *stctx; 1064 unsigned int i; 1065 1066 stctx = g_new0(XHCIStreamContext, count); 1067 for (i = 0; i < count; i++) { 1068 stctx[i].pctx = base + i * 16; 1069 stctx[i].sct = -1; 1070 } 1071 return stctx; 1072 } 1073 1074 static void xhci_reset_streams(XHCIEPContext *epctx) 1075 { 1076 unsigned int i; 1077 1078 for (i = 0; i < epctx->nr_pstreams; i++) { 1079 epctx->pstreams[i].sct = -1; 1080 } 1081 } 1082 1083 static void xhci_alloc_streams(XHCIEPContext *epctx, dma_addr_t base) 1084 { 1085 assert(epctx->pstreams == NULL); 1086 epctx->nr_pstreams = 2 << epctx->max_pstreams; 1087 epctx->pstreams = xhci_alloc_stream_contexts(epctx->nr_pstreams, base); 1088 } 1089 1090 static void xhci_free_streams(XHCIEPContext *epctx) 1091 { 1092 assert(epctx->pstreams != NULL); 1093 1094 g_free(epctx->pstreams); 1095 epctx->pstreams = NULL; 1096 epctx->nr_pstreams = 0; 1097 } 1098 1099 static int xhci_epmask_to_eps_with_streams(XHCIState *xhci, 1100 unsigned int slotid, 1101 uint32_t epmask, 1102 XHCIEPContext **epctxs, 1103 USBEndpoint **eps) 1104 { 1105 XHCISlot *slot; 1106 XHCIEPContext *epctx; 1107 USBEndpoint *ep; 1108 int i, j; 1109 1110 assert(slotid >= 1 && slotid <= xhci->numslots); 1111 1112 slot = &xhci->slots[slotid - 1]; 1113 1114 for (i = 2, j = 0; i <= 31; i++) { 1115 if (!(epmask & (1u << i))) { 1116 continue; 1117 } 1118 1119 epctx = slot->eps[i - 1]; 1120 ep = xhci_epid_to_usbep(epctx); 1121 if (!epctx || !epctx->nr_pstreams || !ep) { 1122 continue; 1123 } 1124 1125 if (epctxs) { 1126 epctxs[j] = epctx; 1127 } 1128 eps[j++] = ep; 1129 } 1130 return j; 1131 } 1132 1133 static void xhci_free_device_streams(XHCIState *xhci, unsigned int slotid, 1134 uint32_t epmask) 1135 { 1136 USBEndpoint *eps[30]; 1137 int nr_eps; 1138 1139 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, NULL, eps); 1140 if (nr_eps) { 1141 usb_device_free_streams(eps[0]->dev, eps, nr_eps); 1142 } 1143 } 1144 1145 static TRBCCode xhci_alloc_device_streams(XHCIState *xhci, unsigned int slotid, 1146 uint32_t epmask) 1147 { 1148 XHCIEPContext *epctxs[30]; 1149 USBEndpoint *eps[30]; 1150 int i, r, nr_eps, req_nr_streams, dev_max_streams; 1151 1152 nr_eps = xhci_epmask_to_eps_with_streams(xhci, slotid, epmask, epctxs, 1153 eps); 1154 if (nr_eps == 0) { 1155 return CC_SUCCESS; 1156 } 1157 1158 req_nr_streams = epctxs[0]->nr_pstreams; 1159 dev_max_streams = eps[0]->max_streams; 1160 1161 for (i = 1; i < nr_eps; i++) { 1162 /* 1163 * HdG: I don't expect these to ever trigger, but if they do we need 1164 * to come up with another solution, ie group identical endpoints 1165 * together and make an usb_device_alloc_streams call per group. 1166 */ 1167 if (epctxs[i]->nr_pstreams != req_nr_streams) { 1168 FIXME("guest streams config not identical for all eps"); 1169 return CC_RESOURCE_ERROR; 1170 } 1171 if (eps[i]->max_streams != dev_max_streams) { 1172 FIXME("device streams config not identical for all eps"); 1173 return CC_RESOURCE_ERROR; 1174 } 1175 } 1176 1177 /* 1178 * max-streams in both the device descriptor and in the controller is a 1179 * power of 2. But stream id 0 is reserved, so if a device can do up to 4 1180 * streams the guest will ask for 5 rounded up to the next power of 2 which 1181 * becomes 8. For emulated devices usb_device_alloc_streams is a nop. 1182 * 1183 * For redirected devices however this is an issue, as there we must ask 1184 * the real xhci controller to alloc streams, and the host driver for the 1185 * real xhci controller will likely disallow allocating more streams then 1186 * the device can handle. 1187 * 1188 * So we limit the requested nr_streams to the maximum number the device 1189 * can handle. 1190 */ 1191 if (req_nr_streams > dev_max_streams) { 1192 req_nr_streams = dev_max_streams; 1193 } 1194 1195 r = usb_device_alloc_streams(eps[0]->dev, eps, nr_eps, req_nr_streams); 1196 if (r != 0) { 1197 DPRINTF("xhci: alloc streams failed\n"); 1198 return CC_RESOURCE_ERROR; 1199 } 1200 1201 return CC_SUCCESS; 1202 } 1203 1204 static XHCIStreamContext *xhci_find_stream(XHCIEPContext *epctx, 1205 unsigned int streamid, 1206 uint32_t *cc_error) 1207 { 1208 XHCIStreamContext *sctx; 1209 dma_addr_t base; 1210 uint32_t ctx[2], sct; 1211 1212 assert(streamid != 0); 1213 if (epctx->lsa) { 1214 if (streamid >= epctx->nr_pstreams) { 1215 *cc_error = CC_INVALID_STREAM_ID_ERROR; 1216 return NULL; 1217 } 1218 sctx = epctx->pstreams + streamid; 1219 } else { 1220 FIXME("secondary streams not implemented yet"); 1221 } 1222 1223 if (sctx->sct == -1) { 1224 xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx)); 1225 sct = (ctx[0] >> 1) & 0x07; 1226 if (epctx->lsa && sct != 1) { 1227 *cc_error = CC_INVALID_STREAM_TYPE_ERROR; 1228 return NULL; 1229 } 1230 sctx->sct = sct; 1231 base = xhci_addr64(ctx[0] & ~0xf, ctx[1]); 1232 xhci_ring_init(epctx->xhci, &sctx->ring, base); 1233 } 1234 return sctx; 1235 } 1236 1237 static void xhci_set_ep_state(XHCIState *xhci, XHCIEPContext *epctx, 1238 XHCIStreamContext *sctx, uint32_t state) 1239 { 1240 XHCIRing *ring = NULL; 1241 uint32_t ctx[5]; 1242 uint32_t ctx2[2]; 1243 1244 xhci_dma_read_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1245 ctx[0] &= ~EP_STATE_MASK; 1246 ctx[0] |= state; 1247 1248 /* update ring dequeue ptr */ 1249 if (epctx->nr_pstreams) { 1250 if (sctx != NULL) { 1251 ring = &sctx->ring; 1252 xhci_dma_read_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1253 ctx2[0] &= 0xe; 1254 ctx2[0] |= sctx->ring.dequeue | sctx->ring.ccs; 1255 ctx2[1] = (sctx->ring.dequeue >> 16) >> 16; 1256 xhci_dma_write_u32s(xhci, sctx->pctx, ctx2, sizeof(ctx2)); 1257 } 1258 } else { 1259 ring = &epctx->ring; 1260 } 1261 if (ring) { 1262 ctx[2] = ring->dequeue | ring->ccs; 1263 ctx[3] = (ring->dequeue >> 16) >> 16; 1264 1265 DPRINTF("xhci: set epctx: " DMA_ADDR_FMT " state=%d dequeue=%08x%08x\n", 1266 epctx->pctx, state, ctx[3], ctx[2]); 1267 } 1268 1269 xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx)); 1270 if (epctx->state != state) { 1271 trace_usb_xhci_ep_state(epctx->slotid, epctx->epid, 1272 ep_state_name(epctx->state), 1273 ep_state_name(state)); 1274 } 1275 epctx->state = state; 1276 } 1277 1278 static void xhci_ep_kick_timer(void *opaque) 1279 { 1280 XHCIEPContext *epctx = opaque; 1281 xhci_kick_epctx(epctx, 0); 1282 } 1283 1284 static XHCIEPContext *xhci_alloc_epctx(XHCIState *xhci, 1285 unsigned int slotid, 1286 unsigned int epid) 1287 { 1288 XHCIEPContext *epctx; 1289 1290 epctx = g_new0(XHCIEPContext, 1); 1291 epctx->xhci = xhci; 1292 epctx->slotid = slotid; 1293 epctx->epid = epid; 1294 1295 QTAILQ_INIT(&epctx->transfers); 1296 epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx); 1297 1298 return epctx; 1299 } 1300 1301 static void xhci_init_epctx(XHCIEPContext *epctx, 1302 dma_addr_t pctx, uint32_t *ctx) 1303 { 1304 dma_addr_t dequeue; 1305 1306 dequeue = xhci_addr64(ctx[2] & ~0xf, ctx[3]); 1307 1308 epctx->type = (ctx[1] >> EP_TYPE_SHIFT) & EP_TYPE_MASK; 1309 epctx->pctx = pctx; 1310 epctx->max_psize = ctx[1]>>16; 1311 epctx->max_psize *= 1+((ctx[1]>>8)&0xff); 1312 epctx->max_pstreams = (ctx[0] >> 10) & epctx->xhci->max_pstreams_mask; 1313 epctx->lsa = (ctx[0] >> 15) & 1; 1314 if (epctx->max_pstreams) { 1315 xhci_alloc_streams(epctx, dequeue); 1316 } else { 1317 xhci_ring_init(epctx->xhci, &epctx->ring, dequeue); 1318 epctx->ring.ccs = ctx[2] & 1; 1319 } 1320 1321 epctx->interval = 1 << ((ctx[0] >> 16) & 0xff); 1322 } 1323 1324 static TRBCCode xhci_enable_ep(XHCIState *xhci, unsigned int slotid, 1325 unsigned int epid, dma_addr_t pctx, 1326 uint32_t *ctx) 1327 { 1328 XHCISlot *slot; 1329 XHCIEPContext *epctx; 1330 1331 trace_usb_xhci_ep_enable(slotid, epid); 1332 assert(slotid >= 1 && slotid <= xhci->numslots); 1333 assert(epid >= 1 && epid <= 31); 1334 1335 slot = &xhci->slots[slotid-1]; 1336 if (slot->eps[epid-1]) { 1337 xhci_disable_ep(xhci, slotid, epid); 1338 } 1339 1340 epctx = xhci_alloc_epctx(xhci, slotid, epid); 1341 slot->eps[epid-1] = epctx; 1342 xhci_init_epctx(epctx, pctx, ctx); 1343 1344 DPRINTF("xhci: endpoint %d.%d type is %d, max transaction (burst) " 1345 "size is %d\n", epid/2, epid%2, epctx->type, epctx->max_psize); 1346 1347 epctx->mfindex_last = 0; 1348 1349 epctx->state = EP_RUNNING; 1350 ctx[0] &= ~EP_STATE_MASK; 1351 ctx[0] |= EP_RUNNING; 1352 1353 return CC_SUCCESS; 1354 } 1355 1356 static XHCITransfer *xhci_ep_alloc_xfer(XHCIEPContext *epctx, 1357 uint32_t length) 1358 { 1359 uint32_t limit = epctx->nr_pstreams + 16; 1360 XHCITransfer *xfer; 1361 1362 if (epctx->xfer_count >= limit) { 1363 return NULL; 1364 } 1365 1366 xfer = g_new0(XHCITransfer, 1); 1367 xfer->epctx = epctx; 1368 xfer->trbs = g_new(XHCITRB, length); 1369 xfer->trb_count = length; 1370 usb_packet_init(&xfer->packet); 1371 1372 QTAILQ_INSERT_TAIL(&epctx->transfers, xfer, next); 1373 epctx->xfer_count++; 1374 1375 return xfer; 1376 } 1377 1378 static void xhci_ep_free_xfer(XHCITransfer *xfer) 1379 { 1380 QTAILQ_REMOVE(&xfer->epctx->transfers, xfer, next); 1381 xfer->epctx->xfer_count--; 1382 1383 usb_packet_cleanup(&xfer->packet); 1384 g_free(xfer->trbs); 1385 g_free(xfer); 1386 } 1387 1388 static int xhci_ep_nuke_one_xfer(XHCITransfer *t, TRBCCode report) 1389 { 1390 int killed = 0; 1391 1392 if (report && (t->running_async || t->running_retry)) { 1393 t->status = report; 1394 xhci_xfer_report(t); 1395 } 1396 1397 if (t->running_async) { 1398 usb_cancel_packet(&t->packet); 1399 t->running_async = 0; 1400 killed = 1; 1401 } 1402 if (t->running_retry) { 1403 if (t->epctx) { 1404 t->epctx->retry = NULL; 1405 timer_del(t->epctx->kick_timer); 1406 } 1407 t->running_retry = 0; 1408 killed = 1; 1409 } 1410 g_free(t->trbs); 1411 1412 t->trbs = NULL; 1413 t->trb_count = 0; 1414 1415 return killed; 1416 } 1417 1418 static int xhci_ep_nuke_xfers(XHCIState *xhci, unsigned int slotid, 1419 unsigned int epid, TRBCCode report) 1420 { 1421 XHCISlot *slot; 1422 XHCIEPContext *epctx; 1423 XHCITransfer *xfer; 1424 int killed = 0; 1425 USBEndpoint *ep = NULL; 1426 assert(slotid >= 1 && slotid <= xhci->numslots); 1427 assert(epid >= 1 && epid <= 31); 1428 1429 DPRINTF("xhci_ep_nuke_xfers(%d, %d)\n", slotid, epid); 1430 1431 slot = &xhci->slots[slotid-1]; 1432 1433 if (!slot->eps[epid-1]) { 1434 return 0; 1435 } 1436 1437 epctx = slot->eps[epid-1]; 1438 1439 for (;;) { 1440 xfer = QTAILQ_FIRST(&epctx->transfers); 1441 if (xfer == NULL) { 1442 break; 1443 } 1444 killed += xhci_ep_nuke_one_xfer(xfer, report); 1445 if (killed) { 1446 report = 0; /* Only report once */ 1447 } 1448 xhci_ep_free_xfer(xfer); 1449 } 1450 1451 ep = xhci_epid_to_usbep(epctx); 1452 if (ep) { 1453 usb_device_ep_stopped(ep->dev, ep); 1454 } 1455 return killed; 1456 } 1457 1458 static TRBCCode xhci_disable_ep(XHCIState *xhci, unsigned int slotid, 1459 unsigned int epid) 1460 { 1461 XHCISlot *slot; 1462 XHCIEPContext *epctx; 1463 1464 trace_usb_xhci_ep_disable(slotid, epid); 1465 assert(slotid >= 1 && slotid <= xhci->numslots); 1466 assert(epid >= 1 && epid <= 31); 1467 1468 slot = &xhci->slots[slotid-1]; 1469 1470 if (!slot->eps[epid-1]) { 1471 DPRINTF("xhci: slot %d ep %d already disabled\n", slotid, epid); 1472 return CC_SUCCESS; 1473 } 1474 1475 xhci_ep_nuke_xfers(xhci, slotid, epid, 0); 1476 1477 epctx = slot->eps[epid-1]; 1478 1479 if (epctx->nr_pstreams) { 1480 xhci_free_streams(epctx); 1481 } 1482 1483 /* only touch guest RAM if we're not resetting the HC */ 1484 if (xhci->dcbaap_low || xhci->dcbaap_high) { 1485 xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED); 1486 } 1487 1488 timer_free(epctx->kick_timer); 1489 g_free(epctx); 1490 slot->eps[epid-1] = NULL; 1491 1492 return CC_SUCCESS; 1493 } 1494 1495 static TRBCCode xhci_stop_ep(XHCIState *xhci, unsigned int slotid, 1496 unsigned int epid) 1497 { 1498 XHCISlot *slot; 1499 XHCIEPContext *epctx; 1500 1501 trace_usb_xhci_ep_stop(slotid, epid); 1502 assert(slotid >= 1 && slotid <= xhci->numslots); 1503 1504 if (epid < 1 || epid > 31) { 1505 DPRINTF("xhci: bad ep %d\n", epid); 1506 return CC_TRB_ERROR; 1507 } 1508 1509 slot = &xhci->slots[slotid-1]; 1510 1511 if (!slot->eps[epid-1]) { 1512 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1513 return CC_EP_NOT_ENABLED_ERROR; 1514 } 1515 1516 if (xhci_ep_nuke_xfers(xhci, slotid, epid, CC_STOPPED) > 0) { 1517 DPRINTF("xhci: FIXME: endpoint stopped w/ xfers running, " 1518 "data might be lost\n"); 1519 } 1520 1521 epctx = slot->eps[epid-1]; 1522 1523 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1524 1525 if (epctx->nr_pstreams) { 1526 xhci_reset_streams(epctx); 1527 } 1528 1529 return CC_SUCCESS; 1530 } 1531 1532 static TRBCCode xhci_reset_ep(XHCIState *xhci, unsigned int slotid, 1533 unsigned int epid) 1534 { 1535 XHCISlot *slot; 1536 XHCIEPContext *epctx; 1537 1538 trace_usb_xhci_ep_reset(slotid, epid); 1539 assert(slotid >= 1 && slotid <= xhci->numslots); 1540 1541 if (epid < 1 || epid > 31) { 1542 DPRINTF("xhci: bad ep %d\n", epid); 1543 return CC_TRB_ERROR; 1544 } 1545 1546 slot = &xhci->slots[slotid-1]; 1547 1548 if (!slot->eps[epid-1]) { 1549 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1550 return CC_EP_NOT_ENABLED_ERROR; 1551 } 1552 1553 epctx = slot->eps[epid-1]; 1554 1555 if (epctx->state != EP_HALTED) { 1556 DPRINTF("xhci: reset EP while EP %d not halted (%d)\n", 1557 epid, epctx->state); 1558 return CC_CONTEXT_STATE_ERROR; 1559 } 1560 1561 if (xhci_ep_nuke_xfers(xhci, slotid, epid, 0) > 0) { 1562 DPRINTF("xhci: FIXME: endpoint reset w/ xfers running, " 1563 "data might be lost\n"); 1564 } 1565 1566 if (!xhci->slots[slotid-1].uport || 1567 !xhci->slots[slotid-1].uport->dev || 1568 !xhci->slots[slotid-1].uport->dev->attached) { 1569 return CC_USB_TRANSACTION_ERROR; 1570 } 1571 1572 xhci_set_ep_state(xhci, epctx, NULL, EP_STOPPED); 1573 1574 if (epctx->nr_pstreams) { 1575 xhci_reset_streams(epctx); 1576 } 1577 1578 return CC_SUCCESS; 1579 } 1580 1581 static TRBCCode xhci_set_ep_dequeue(XHCIState *xhci, unsigned int slotid, 1582 unsigned int epid, unsigned int streamid, 1583 uint64_t pdequeue) 1584 { 1585 XHCISlot *slot; 1586 XHCIEPContext *epctx; 1587 XHCIStreamContext *sctx; 1588 dma_addr_t dequeue; 1589 1590 assert(slotid >= 1 && slotid <= xhci->numslots); 1591 1592 if (epid < 1 || epid > 31) { 1593 DPRINTF("xhci: bad ep %d\n", epid); 1594 return CC_TRB_ERROR; 1595 } 1596 1597 trace_usb_xhci_ep_set_dequeue(slotid, epid, streamid, pdequeue); 1598 dequeue = xhci_mask64(pdequeue); 1599 1600 slot = &xhci->slots[slotid-1]; 1601 1602 if (!slot->eps[epid-1]) { 1603 DPRINTF("xhci: slot %d ep %d not enabled\n", slotid, epid); 1604 return CC_EP_NOT_ENABLED_ERROR; 1605 } 1606 1607 epctx = slot->eps[epid-1]; 1608 1609 if (epctx->state != EP_STOPPED) { 1610 DPRINTF("xhci: set EP dequeue pointer while EP %d not stopped\n", epid); 1611 return CC_CONTEXT_STATE_ERROR; 1612 } 1613 1614 if (epctx->nr_pstreams) { 1615 uint32_t err; 1616 sctx = xhci_find_stream(epctx, streamid, &err); 1617 if (sctx == NULL) { 1618 return err; 1619 } 1620 xhci_ring_init(xhci, &sctx->ring, dequeue & ~0xf); 1621 sctx->ring.ccs = dequeue & 1; 1622 } else { 1623 sctx = NULL; 1624 xhci_ring_init(xhci, &epctx->ring, dequeue & ~0xF); 1625 epctx->ring.ccs = dequeue & 1; 1626 } 1627 1628 xhci_set_ep_state(xhci, epctx, sctx, EP_STOPPED); 1629 1630 return CC_SUCCESS; 1631 } 1632 1633 static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) 1634 { 1635 XHCIState *xhci = xfer->epctx->xhci; 1636 int i; 1637 1638 xfer->int_req = false; 1639 pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); 1640 for (i = 0; i < xfer->trb_count; i++) { 1641 XHCITRB *trb = &xfer->trbs[i]; 1642 dma_addr_t addr; 1643 unsigned int chunk = 0; 1644 1645 if (trb->control & TRB_TR_IOC) { 1646 xfer->int_req = true; 1647 } 1648 1649 switch (TRB_TYPE(*trb)) { 1650 case TR_DATA: 1651 if ((!(trb->control & TRB_TR_DIR)) != (!in_xfer)) { 1652 DPRINTF("xhci: data direction mismatch for TR_DATA\n"); 1653 goto err; 1654 } 1655 /* fallthrough */ 1656 case TR_NORMAL: 1657 case TR_ISOCH: 1658 addr = xhci_mask64(trb->parameter); 1659 chunk = trb->status & 0x1ffff; 1660 if (trb->control & TRB_TR_IDT) { 1661 if (chunk > 8 || in_xfer) { 1662 DPRINTF("xhci: invalid immediate data TRB\n"); 1663 goto err; 1664 } 1665 qemu_sglist_add(&xfer->sgl, trb->addr, chunk); 1666 } else { 1667 qemu_sglist_add(&xfer->sgl, addr, chunk); 1668 } 1669 break; 1670 } 1671 } 1672 1673 return 0; 1674 1675 err: 1676 qemu_sglist_destroy(&xfer->sgl); 1677 xhci_die(xhci); 1678 return -1; 1679 } 1680 1681 static void xhci_xfer_unmap(XHCITransfer *xfer) 1682 { 1683 usb_packet_unmap(&xfer->packet, &xfer->sgl); 1684 qemu_sglist_destroy(&xfer->sgl); 1685 } 1686 1687 static void xhci_xfer_report(XHCITransfer *xfer) 1688 { 1689 uint32_t edtla = 0; 1690 unsigned int left; 1691 bool reported = 0; 1692 bool shortpkt = 0; 1693 XHCIEvent event = {ER_TRANSFER, CC_SUCCESS}; 1694 XHCIState *xhci = xfer->epctx->xhci; 1695 int i; 1696 1697 left = xfer->packet.actual_length; 1698 1699 for (i = 0; i < xfer->trb_count; i++) { 1700 XHCITRB *trb = &xfer->trbs[i]; 1701 unsigned int chunk = 0; 1702 1703 switch (TRB_TYPE(*trb)) { 1704 case TR_SETUP: 1705 chunk = trb->status & 0x1ffff; 1706 if (chunk > 8) { 1707 chunk = 8; 1708 } 1709 break; 1710 case TR_DATA: 1711 case TR_NORMAL: 1712 case TR_ISOCH: 1713 chunk = trb->status & 0x1ffff; 1714 if (chunk > left) { 1715 chunk = left; 1716 if (xfer->status == CC_SUCCESS) { 1717 shortpkt = 1; 1718 } 1719 } 1720 left -= chunk; 1721 edtla += chunk; 1722 break; 1723 case TR_STATUS: 1724 reported = 0; 1725 shortpkt = 0; 1726 break; 1727 } 1728 1729 if (!reported && ((trb->control & TRB_TR_IOC) || 1730 (shortpkt && (trb->control & TRB_TR_ISP)) || 1731 (xfer->status != CC_SUCCESS && left == 0))) { 1732 event.slotid = xfer->epctx->slotid; 1733 event.epid = xfer->epctx->epid; 1734 event.length = (trb->status & 0x1ffff) - chunk; 1735 event.flags = 0; 1736 event.ptr = trb->addr; 1737 if (xfer->status == CC_SUCCESS) { 1738 event.ccode = shortpkt ? CC_SHORT_PACKET : CC_SUCCESS; 1739 } else { 1740 event.ccode = xfer->status; 1741 } 1742 if (TRB_TYPE(*trb) == TR_EVDATA) { 1743 event.ptr = trb->parameter; 1744 event.flags |= TRB_EV_ED; 1745 event.length = edtla & 0xffffff; 1746 DPRINTF("xhci_xfer_data: EDTLA=%d\n", event.length); 1747 edtla = 0; 1748 } 1749 xhci_event(xhci, &event, TRB_INTR(*trb)); 1750 reported = 1; 1751 if (xfer->status != CC_SUCCESS) { 1752 return; 1753 } 1754 } 1755 1756 switch (TRB_TYPE(*trb)) { 1757 case TR_SETUP: 1758 reported = 0; 1759 shortpkt = 0; 1760 break; 1761 } 1762 1763 } 1764 } 1765 1766 static void xhci_stall_ep(XHCITransfer *xfer) 1767 { 1768 XHCIEPContext *epctx = xfer->epctx; 1769 XHCIState *xhci = epctx->xhci; 1770 uint32_t err; 1771 XHCIStreamContext *sctx; 1772 1773 if (epctx->nr_pstreams) { 1774 sctx = xhci_find_stream(epctx, xfer->streamid, &err); 1775 if (sctx == NULL) { 1776 return; 1777 } 1778 sctx->ring.dequeue = xfer->trbs[0].addr; 1779 sctx->ring.ccs = xfer->trbs[0].ccs; 1780 xhci_set_ep_state(xhci, epctx, sctx, EP_HALTED); 1781 } else { 1782 epctx->ring.dequeue = xfer->trbs[0].addr; 1783 epctx->ring.ccs = xfer->trbs[0].ccs; 1784 xhci_set_ep_state(xhci, epctx, NULL, EP_HALTED); 1785 } 1786 } 1787 1788 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, 1789 XHCIEPContext *epctx); 1790 1791 static int xhci_setup_packet(XHCITransfer *xfer) 1792 { 1793 USBEndpoint *ep; 1794 int dir; 1795 1796 dir = xfer->in_xfer ? USB_TOKEN_IN : USB_TOKEN_OUT; 1797 1798 if (xfer->packet.ep) { 1799 ep = xfer->packet.ep; 1800 } else { 1801 ep = xhci_epid_to_usbep(xfer->epctx); 1802 if (!ep) { 1803 DPRINTF("xhci: slot %d has no device\n", 1804 xfer->slotid); 1805 return -1; 1806 } 1807 } 1808 1809 xhci_xfer_create_sgl(xfer, dir == USB_TOKEN_IN); /* Also sets int_req */ 1810 usb_packet_setup(&xfer->packet, dir, ep, xfer->streamid, 1811 xfer->trbs[0].addr, false, xfer->int_req); 1812 usb_packet_map(&xfer->packet, &xfer->sgl); 1813 DPRINTF("xhci: setup packet pid 0x%x addr %d ep %d\n", 1814 xfer->packet.pid, ep->dev->addr, ep->nr); 1815 return 0; 1816 } 1817 1818 static int xhci_try_complete_packet(XHCITransfer *xfer) 1819 { 1820 if (xfer->packet.status == USB_RET_ASYNC) { 1821 trace_usb_xhci_xfer_async(xfer); 1822 xfer->running_async = 1; 1823 xfer->running_retry = 0; 1824 xfer->complete = 0; 1825 return 0; 1826 } else if (xfer->packet.status == USB_RET_NAK) { 1827 trace_usb_xhci_xfer_nak(xfer); 1828 xfer->running_async = 0; 1829 xfer->running_retry = 1; 1830 xfer->complete = 0; 1831 return 0; 1832 } else { 1833 xfer->running_async = 0; 1834 xfer->running_retry = 0; 1835 xfer->complete = 1; 1836 xhci_xfer_unmap(xfer); 1837 } 1838 1839 if (xfer->packet.status == USB_RET_SUCCESS) { 1840 trace_usb_xhci_xfer_success(xfer, xfer->packet.actual_length); 1841 xfer->status = CC_SUCCESS; 1842 xhci_xfer_report(xfer); 1843 return 0; 1844 } 1845 1846 /* error */ 1847 trace_usb_xhci_xfer_error(xfer, xfer->packet.status); 1848 switch (xfer->packet.status) { 1849 case USB_RET_NODEV: 1850 case USB_RET_IOERROR: 1851 xfer->status = CC_USB_TRANSACTION_ERROR; 1852 xhci_xfer_report(xfer); 1853 xhci_stall_ep(xfer); 1854 break; 1855 case USB_RET_STALL: 1856 xfer->status = CC_STALL_ERROR; 1857 xhci_xfer_report(xfer); 1858 xhci_stall_ep(xfer); 1859 break; 1860 case USB_RET_BABBLE: 1861 xfer->status = CC_BABBLE_DETECTED; 1862 xhci_xfer_report(xfer); 1863 xhci_stall_ep(xfer); 1864 break; 1865 default: 1866 DPRINTF("%s: FIXME: status = %d\n", __func__, 1867 xfer->packet.status); 1868 FIXME("unhandled USB_RET_*"); 1869 } 1870 return 0; 1871 } 1872 1873 static int xhci_fire_ctl_transfer(XHCIState *xhci, XHCITransfer *xfer) 1874 { 1875 XHCITRB *trb_setup, *trb_status; 1876 uint8_t bmRequestType; 1877 1878 trb_setup = &xfer->trbs[0]; 1879 trb_status = &xfer->trbs[xfer->trb_count-1]; 1880 1881 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 1882 xfer->epctx->epid, xfer->streamid); 1883 1884 /* at most one Event Data TRB allowed after STATUS */ 1885 if (TRB_TYPE(*trb_status) == TR_EVDATA && xfer->trb_count > 2) { 1886 trb_status--; 1887 } 1888 1889 /* do some sanity checks */ 1890 if (TRB_TYPE(*trb_setup) != TR_SETUP) { 1891 DPRINTF("xhci: ep0 first TD not SETUP: %d\n", 1892 TRB_TYPE(*trb_setup)); 1893 return -1; 1894 } 1895 if (TRB_TYPE(*trb_status) != TR_STATUS) { 1896 DPRINTF("xhci: ep0 last TD not STATUS: %d\n", 1897 TRB_TYPE(*trb_status)); 1898 return -1; 1899 } 1900 if (!(trb_setup->control & TRB_TR_IDT)) { 1901 DPRINTF("xhci: Setup TRB doesn't have IDT set\n"); 1902 return -1; 1903 } 1904 if ((trb_setup->status & 0x1ffff) != 8) { 1905 DPRINTF("xhci: Setup TRB has bad length (%d)\n", 1906 (trb_setup->status & 0x1ffff)); 1907 return -1; 1908 } 1909 1910 bmRequestType = trb_setup->parameter; 1911 1912 xfer->in_xfer = bmRequestType & USB_DIR_IN; 1913 xfer->iso_xfer = false; 1914 xfer->timed_xfer = false; 1915 1916 if (xhci_setup_packet(xfer) < 0) { 1917 return -1; 1918 } 1919 xfer->packet.parameter = trb_setup->parameter; 1920 1921 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 1922 xhci_try_complete_packet(xfer); 1923 return 0; 1924 } 1925 1926 static void xhci_calc_intr_kick(XHCIState *xhci, XHCITransfer *xfer, 1927 XHCIEPContext *epctx, uint64_t mfindex) 1928 { 1929 uint64_t asap = ((mfindex + epctx->interval - 1) & 1930 ~(epctx->interval-1)); 1931 uint64_t kick = epctx->mfindex_last + epctx->interval; 1932 1933 assert(epctx->interval != 0); 1934 xfer->mfindex_kick = MAX(asap, kick); 1935 } 1936 1937 static void xhci_calc_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1938 XHCIEPContext *epctx, uint64_t mfindex) 1939 { 1940 if (xfer->trbs[0].control & TRB_TR_SIA) { 1941 uint64_t asap = ((mfindex + epctx->interval - 1) & 1942 ~(epctx->interval-1)); 1943 if (asap >= epctx->mfindex_last && 1944 asap <= epctx->mfindex_last + epctx->interval * 4) { 1945 xfer->mfindex_kick = epctx->mfindex_last + epctx->interval; 1946 } else { 1947 xfer->mfindex_kick = asap; 1948 } 1949 } else { 1950 xfer->mfindex_kick = ((xfer->trbs[0].control >> TRB_TR_FRAMEID_SHIFT) 1951 & TRB_TR_FRAMEID_MASK) << 3; 1952 xfer->mfindex_kick |= mfindex & ~0x3fff; 1953 if (xfer->mfindex_kick + 0x100 < mfindex) { 1954 xfer->mfindex_kick += 0x4000; 1955 } 1956 } 1957 } 1958 1959 static void xhci_check_intr_iso_kick(XHCIState *xhci, XHCITransfer *xfer, 1960 XHCIEPContext *epctx, uint64_t mfindex) 1961 { 1962 if (xfer->mfindex_kick > mfindex) { 1963 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 1964 (xfer->mfindex_kick - mfindex) * 125000); 1965 xfer->running_retry = 1; 1966 } else { 1967 epctx->mfindex_last = xfer->mfindex_kick; 1968 timer_del(epctx->kick_timer); 1969 xfer->running_retry = 0; 1970 } 1971 } 1972 1973 1974 static int xhci_submit(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 1975 { 1976 uint64_t mfindex; 1977 1978 DPRINTF("xhci_submit(slotid=%d,epid=%d)\n", xfer->slotid, xfer->epid); 1979 1980 xfer->in_xfer = epctx->type>>2; 1981 1982 switch(epctx->type) { 1983 case ET_INTR_OUT: 1984 case ET_INTR_IN: 1985 xfer->pkts = 0; 1986 xfer->iso_xfer = false; 1987 xfer->timed_xfer = true; 1988 mfindex = xhci_mfindex_get(xhci); 1989 xhci_calc_intr_kick(xhci, xfer, epctx, mfindex); 1990 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 1991 if (xfer->running_retry) { 1992 return -1; 1993 } 1994 break; 1995 case ET_BULK_OUT: 1996 case ET_BULK_IN: 1997 xfer->pkts = 0; 1998 xfer->iso_xfer = false; 1999 xfer->timed_xfer = false; 2000 break; 2001 case ET_ISO_OUT: 2002 case ET_ISO_IN: 2003 xfer->pkts = 1; 2004 xfer->iso_xfer = true; 2005 xfer->timed_xfer = true; 2006 mfindex = xhci_mfindex_get(xhci); 2007 xhci_calc_iso_kick(xhci, xfer, epctx, mfindex); 2008 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2009 if (xfer->running_retry) { 2010 return -1; 2011 } 2012 break; 2013 default: 2014 trace_usb_xhci_unimplemented("endpoint type", epctx->type); 2015 return -1; 2016 } 2017 2018 if (xhci_setup_packet(xfer) < 0) { 2019 return -1; 2020 } 2021 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2022 xhci_try_complete_packet(xfer); 2023 return 0; 2024 } 2025 2026 static int xhci_fire_transfer(XHCIState *xhci, XHCITransfer *xfer, XHCIEPContext *epctx) 2027 { 2028 trace_usb_xhci_xfer_start(xfer, xfer->epctx->slotid, 2029 xfer->epctx->epid, xfer->streamid); 2030 return xhci_submit(xhci, xfer, epctx); 2031 } 2032 2033 static void xhci_kick_ep(XHCIState *xhci, unsigned int slotid, 2034 unsigned int epid, unsigned int streamid) 2035 { 2036 XHCIEPContext *epctx; 2037 2038 assert(slotid >= 1 && slotid <= xhci->numslots); 2039 assert(epid >= 1 && epid <= 31); 2040 2041 if (!xhci->slots[slotid-1].enabled) { 2042 DPRINTF("xhci: xhci_kick_ep for disabled slot %d\n", slotid); 2043 return; 2044 } 2045 epctx = xhci->slots[slotid-1].eps[epid-1]; 2046 if (!epctx) { 2047 DPRINTF("xhci: xhci_kick_ep for disabled endpoint %d,%d\n", 2048 epid, slotid); 2049 return; 2050 } 2051 2052 if (epctx->kick_active) { 2053 return; 2054 } 2055 xhci_kick_epctx(epctx, streamid); 2056 } 2057 2058 static void xhci_kick_epctx(XHCIEPContext *epctx, unsigned int streamid) 2059 { 2060 XHCIState *xhci = epctx->xhci; 2061 XHCIStreamContext *stctx; 2062 XHCITransfer *xfer; 2063 XHCIRing *ring; 2064 USBEndpoint *ep = NULL; 2065 uint64_t mfindex; 2066 unsigned int count = 0; 2067 int length; 2068 int i; 2069 2070 trace_usb_xhci_ep_kick(epctx->slotid, epctx->epid, streamid); 2071 assert(!epctx->kick_active); 2072 2073 /* If the device has been detached, but the guest has not noticed this 2074 yet the 2 above checks will succeed, but we must NOT continue */ 2075 if (!xhci->slots[epctx->slotid - 1].uport || 2076 !xhci->slots[epctx->slotid - 1].uport->dev || 2077 !xhci->slots[epctx->slotid - 1].uport->dev->attached) { 2078 return; 2079 } 2080 2081 if (epctx->retry) { 2082 XHCITransfer *xfer = epctx->retry; 2083 2084 trace_usb_xhci_xfer_retry(xfer); 2085 assert(xfer->running_retry); 2086 if (xfer->timed_xfer) { 2087 /* time to kick the transfer? */ 2088 mfindex = xhci_mfindex_get(xhci); 2089 xhci_check_intr_iso_kick(xhci, xfer, epctx, mfindex); 2090 if (xfer->running_retry) { 2091 return; 2092 } 2093 xfer->timed_xfer = 0; 2094 xfer->running_retry = 1; 2095 } 2096 if (xfer->iso_xfer) { 2097 /* retry iso transfer */ 2098 if (xhci_setup_packet(xfer) < 0) { 2099 return; 2100 } 2101 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2102 assert(xfer->packet.status != USB_RET_NAK); 2103 xhci_try_complete_packet(xfer); 2104 } else { 2105 /* retry nak'ed transfer */ 2106 if (xhci_setup_packet(xfer) < 0) { 2107 return; 2108 } 2109 usb_handle_packet(xfer->packet.ep->dev, &xfer->packet); 2110 if (xfer->packet.status == USB_RET_NAK) { 2111 return; 2112 } 2113 xhci_try_complete_packet(xfer); 2114 } 2115 assert(!xfer->running_retry); 2116 if (xfer->complete) { 2117 xhci_ep_free_xfer(epctx->retry); 2118 } 2119 epctx->retry = NULL; 2120 } 2121 2122 if (epctx->state == EP_HALTED) { 2123 DPRINTF("xhci: ep halted, not running schedule\n"); 2124 return; 2125 } 2126 2127 2128 if (epctx->nr_pstreams) { 2129 uint32_t err; 2130 stctx = xhci_find_stream(epctx, streamid, &err); 2131 if (stctx == NULL) { 2132 return; 2133 } 2134 ring = &stctx->ring; 2135 xhci_set_ep_state(xhci, epctx, stctx, EP_RUNNING); 2136 } else { 2137 ring = &epctx->ring; 2138 streamid = 0; 2139 xhci_set_ep_state(xhci, epctx, NULL, EP_RUNNING); 2140 } 2141 assert(ring->dequeue != 0); 2142 2143 epctx->kick_active++; 2144 while (1) { 2145 length = xhci_ring_chain_length(xhci, ring); 2146 if (length <= 0) { 2147 break; 2148 } 2149 xfer = xhci_ep_alloc_xfer(epctx, length); 2150 if (xfer == NULL) { 2151 break; 2152 } 2153 2154 for (i = 0; i < length; i++) { 2155 TRBType type; 2156 type = xhci_ring_fetch(xhci, ring, &xfer->trbs[i], NULL); 2157 assert(type); 2158 } 2159 xfer->streamid = streamid; 2160 2161 if (epctx->epid == 1) { 2162 xhci_fire_ctl_transfer(xhci, xfer); 2163 } else { 2164 xhci_fire_transfer(xhci, xfer, epctx); 2165 } 2166 if (xfer->complete) { 2167 xhci_ep_free_xfer(xfer); 2168 xfer = NULL; 2169 } 2170 2171 if (epctx->state == EP_HALTED) { 2172 break; 2173 } 2174 if (xfer != NULL && xfer->running_retry) { 2175 DPRINTF("xhci: xfer nacked, stopping schedule\n"); 2176 epctx->retry = xfer; 2177 break; 2178 } 2179 if (count++ > TRANSFER_LIMIT) { 2180 trace_usb_xhci_enforced_limit("transfers"); 2181 break; 2182 } 2183 } 2184 epctx->kick_active--; 2185 2186 ep = xhci_epid_to_usbep(epctx); 2187 if (ep) { 2188 usb_device_flush_ep_queue(ep->dev, ep); 2189 } 2190 } 2191 2192 static TRBCCode xhci_enable_slot(XHCIState *xhci, unsigned int slotid) 2193 { 2194 trace_usb_xhci_slot_enable(slotid); 2195 assert(slotid >= 1 && slotid <= xhci->numslots); 2196 xhci->slots[slotid-1].enabled = 1; 2197 xhci->slots[slotid-1].uport = NULL; 2198 memset(xhci->slots[slotid-1].eps, 0, sizeof(XHCIEPContext*)*31); 2199 2200 return CC_SUCCESS; 2201 } 2202 2203 static TRBCCode xhci_disable_slot(XHCIState *xhci, unsigned int slotid) 2204 { 2205 int i; 2206 2207 trace_usb_xhci_slot_disable(slotid); 2208 assert(slotid >= 1 && slotid <= xhci->numslots); 2209 2210 for (i = 1; i <= 31; i++) { 2211 if (xhci->slots[slotid-1].eps[i-1]) { 2212 xhci_disable_ep(xhci, slotid, i); 2213 } 2214 } 2215 2216 xhci->slots[slotid-1].enabled = 0; 2217 xhci->slots[slotid-1].addressed = 0; 2218 xhci->slots[slotid-1].uport = NULL; 2219 return CC_SUCCESS; 2220 } 2221 2222 static USBPort *xhci_lookup_uport(XHCIState *xhci, uint32_t *slot_ctx) 2223 { 2224 USBPort *uport; 2225 char path[32]; 2226 int i, pos, port; 2227 2228 port = (slot_ctx[1]>>16) & 0xFF; 2229 if (port < 1 || port > xhci->numports) { 2230 return NULL; 2231 } 2232 port = xhci->ports[port-1].uport->index+1; 2233 pos = snprintf(path, sizeof(path), "%d", port); 2234 for (i = 0; i < 5; i++) { 2235 port = (slot_ctx[0] >> 4*i) & 0x0f; 2236 if (!port) { 2237 break; 2238 } 2239 pos += snprintf(path + pos, sizeof(path) - pos, ".%d", port); 2240 } 2241 2242 QTAILQ_FOREACH(uport, &xhci->bus.used, next) { 2243 if (strcmp(uport->path, path) == 0) { 2244 return uport; 2245 } 2246 } 2247 return NULL; 2248 } 2249 2250 static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, 2251 uint64_t pictx, bool bsr) 2252 { 2253 XHCISlot *slot; 2254 USBPort *uport; 2255 USBDevice *dev; 2256 dma_addr_t ictx, octx, dcbaap; 2257 uint64_t poctx; 2258 uint32_t ictl_ctx[2]; 2259 uint32_t slot_ctx[4]; 2260 uint32_t ep0_ctx[5]; 2261 int i; 2262 TRBCCode res; 2263 2264 assert(slotid >= 1 && slotid <= xhci->numslots); 2265 2266 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 2267 poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); 2268 ictx = xhci_mask64(pictx); 2269 octx = xhci_mask64(poctx); 2270 2271 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2272 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2273 2274 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2275 2276 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] != 0x3) { 2277 DPRINTF("xhci: invalid input context control %08x %08x\n", 2278 ictl_ctx[0], ictl_ctx[1]); 2279 return CC_TRB_ERROR; 2280 } 2281 2282 xhci_dma_read_u32s(xhci, ictx+32, slot_ctx, sizeof(slot_ctx)); 2283 xhci_dma_read_u32s(xhci, ictx+64, ep0_ctx, sizeof(ep0_ctx)); 2284 2285 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2286 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2287 2288 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2289 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2290 2291 uport = xhci_lookup_uport(xhci, slot_ctx); 2292 if (uport == NULL) { 2293 DPRINTF("xhci: port not found\n"); 2294 return CC_TRB_ERROR; 2295 } 2296 trace_usb_xhci_slot_address(slotid, uport->path); 2297 2298 dev = uport->dev; 2299 if (!dev || !dev->attached) { 2300 DPRINTF("xhci: port %s not connected\n", uport->path); 2301 return CC_USB_TRANSACTION_ERROR; 2302 } 2303 2304 for (i = 0; i < xhci->numslots; i++) { 2305 if (i == slotid-1) { 2306 continue; 2307 } 2308 if (xhci->slots[i].uport == uport) { 2309 DPRINTF("xhci: port %s already assigned to slot %d\n", 2310 uport->path, i+1); 2311 return CC_TRB_ERROR; 2312 } 2313 } 2314 2315 slot = &xhci->slots[slotid-1]; 2316 slot->uport = uport; 2317 slot->ctx = octx; 2318 2319 /* Make sure device is in USB_STATE_DEFAULT state */ 2320 usb_device_reset(dev); 2321 if (bsr) { 2322 slot_ctx[3] = SLOT_DEFAULT << SLOT_STATE_SHIFT; 2323 } else { 2324 USBPacket p; 2325 uint8_t buf[1]; 2326 2327 slot_ctx[3] = (SLOT_ADDRESSED << SLOT_STATE_SHIFT) | slotid; 2328 memset(&p, 0, sizeof(p)); 2329 usb_packet_addbuf(&p, buf, sizeof(buf)); 2330 usb_packet_setup(&p, USB_TOKEN_OUT, 2331 usb_ep_get(dev, USB_TOKEN_OUT, 0), 0, 2332 0, false, false); 2333 usb_device_handle_control(dev, &p, 2334 DeviceOutRequest | USB_REQ_SET_ADDRESS, 2335 slotid, 0, 0, NULL); 2336 assert(p.status != USB_RET_ASYNC); 2337 } 2338 2339 res = xhci_enable_ep(xhci, slotid, 1, octx+32, ep0_ctx); 2340 2341 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2342 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2343 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2344 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2345 2346 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2347 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2348 2349 xhci->slots[slotid-1].addressed = 1; 2350 return res; 2351 } 2352 2353 2354 static TRBCCode xhci_configure_slot(XHCIState *xhci, unsigned int slotid, 2355 uint64_t pictx, bool dc) 2356 { 2357 dma_addr_t ictx, octx; 2358 uint32_t ictl_ctx[2]; 2359 uint32_t slot_ctx[4]; 2360 uint32_t islot_ctx[4]; 2361 uint32_t ep_ctx[5]; 2362 int i; 2363 TRBCCode res; 2364 2365 trace_usb_xhci_slot_configure(slotid); 2366 assert(slotid >= 1 && slotid <= xhci->numslots); 2367 2368 ictx = xhci_mask64(pictx); 2369 octx = xhci->slots[slotid-1].ctx; 2370 2371 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2372 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2373 2374 if (dc) { 2375 for (i = 2; i <= 31; i++) { 2376 if (xhci->slots[slotid-1].eps[i-1]) { 2377 xhci_disable_ep(xhci, slotid, i); 2378 } 2379 } 2380 2381 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2382 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2383 slot_ctx[3] |= SLOT_ADDRESSED << SLOT_STATE_SHIFT; 2384 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2385 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2386 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2387 2388 return CC_SUCCESS; 2389 } 2390 2391 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2392 2393 if ((ictl_ctx[0] & 0x3) != 0x0 || (ictl_ctx[1] & 0x3) != 0x1) { 2394 DPRINTF("xhci: invalid input context control %08x %08x\n", 2395 ictl_ctx[0], ictl_ctx[1]); 2396 return CC_TRB_ERROR; 2397 } 2398 2399 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2400 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2401 2402 if (SLOT_STATE(slot_ctx[3]) < SLOT_ADDRESSED) { 2403 DPRINTF("xhci: invalid slot state %08x\n", slot_ctx[3]); 2404 return CC_CONTEXT_STATE_ERROR; 2405 } 2406 2407 xhci_free_device_streams(xhci, slotid, ictl_ctx[0] | ictl_ctx[1]); 2408 2409 for (i = 2; i <= 31; i++) { 2410 if (ictl_ctx[0] & (1<<i)) { 2411 xhci_disable_ep(xhci, slotid, i); 2412 } 2413 if (ictl_ctx[1] & (1<<i)) { 2414 xhci_dma_read_u32s(xhci, ictx+32+(32*i), ep_ctx, sizeof(ep_ctx)); 2415 DPRINTF("xhci: input ep%d.%d context: %08x %08x %08x %08x %08x\n", 2416 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2417 ep_ctx[3], ep_ctx[4]); 2418 xhci_disable_ep(xhci, slotid, i); 2419 res = xhci_enable_ep(xhci, slotid, i, octx+(32*i), ep_ctx); 2420 if (res != CC_SUCCESS) { 2421 return res; 2422 } 2423 DPRINTF("xhci: output ep%d.%d context: %08x %08x %08x %08x %08x\n", 2424 i/2, i%2, ep_ctx[0], ep_ctx[1], ep_ctx[2], 2425 ep_ctx[3], ep_ctx[4]); 2426 xhci_dma_write_u32s(xhci, octx+(32*i), ep_ctx, sizeof(ep_ctx)); 2427 } 2428 } 2429 2430 res = xhci_alloc_device_streams(xhci, slotid, ictl_ctx[1]); 2431 if (res != CC_SUCCESS) { 2432 for (i = 2; i <= 31; i++) { 2433 if (ictl_ctx[1] & (1u << i)) { 2434 xhci_disable_ep(xhci, slotid, i); 2435 } 2436 } 2437 return res; 2438 } 2439 2440 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2441 slot_ctx[3] |= SLOT_CONFIGURED << SLOT_STATE_SHIFT; 2442 slot_ctx[0] &= ~(SLOT_CONTEXT_ENTRIES_MASK << SLOT_CONTEXT_ENTRIES_SHIFT); 2443 slot_ctx[0] |= islot_ctx[0] & (SLOT_CONTEXT_ENTRIES_MASK << 2444 SLOT_CONTEXT_ENTRIES_SHIFT); 2445 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2446 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2447 2448 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2449 2450 return CC_SUCCESS; 2451 } 2452 2453 2454 static TRBCCode xhci_evaluate_slot(XHCIState *xhci, unsigned int slotid, 2455 uint64_t pictx) 2456 { 2457 dma_addr_t ictx, octx; 2458 uint32_t ictl_ctx[2]; 2459 uint32_t iep0_ctx[5]; 2460 uint32_t ep0_ctx[5]; 2461 uint32_t islot_ctx[4]; 2462 uint32_t slot_ctx[4]; 2463 2464 trace_usb_xhci_slot_evaluate(slotid); 2465 assert(slotid >= 1 && slotid <= xhci->numslots); 2466 2467 ictx = xhci_mask64(pictx); 2468 octx = xhci->slots[slotid-1].ctx; 2469 2470 DPRINTF("xhci: input context at "DMA_ADDR_FMT"\n", ictx); 2471 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2472 2473 xhci_dma_read_u32s(xhci, ictx, ictl_ctx, sizeof(ictl_ctx)); 2474 2475 if (ictl_ctx[0] != 0x0 || ictl_ctx[1] & ~0x3) { 2476 DPRINTF("xhci: invalid input context control %08x %08x\n", 2477 ictl_ctx[0], ictl_ctx[1]); 2478 return CC_TRB_ERROR; 2479 } 2480 2481 if (ictl_ctx[1] & 0x1) { 2482 xhci_dma_read_u32s(xhci, ictx+32, islot_ctx, sizeof(islot_ctx)); 2483 2484 DPRINTF("xhci: input slot context: %08x %08x %08x %08x\n", 2485 islot_ctx[0], islot_ctx[1], islot_ctx[2], islot_ctx[3]); 2486 2487 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2488 2489 slot_ctx[1] &= ~0xFFFF; /* max exit latency */ 2490 slot_ctx[1] |= islot_ctx[1] & 0xFFFF; 2491 slot_ctx[2] &= ~0xFF00000; /* interrupter target */ 2492 slot_ctx[2] |= islot_ctx[2] & 0xFF000000; 2493 2494 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2495 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2496 2497 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2498 } 2499 2500 if (ictl_ctx[1] & 0x2) { 2501 xhci_dma_read_u32s(xhci, ictx+64, iep0_ctx, sizeof(iep0_ctx)); 2502 2503 DPRINTF("xhci: input ep0 context: %08x %08x %08x %08x %08x\n", 2504 iep0_ctx[0], iep0_ctx[1], iep0_ctx[2], 2505 iep0_ctx[3], iep0_ctx[4]); 2506 2507 xhci_dma_read_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2508 2509 ep0_ctx[1] &= ~0xFFFF0000; /* max packet size*/ 2510 ep0_ctx[1] |= iep0_ctx[1] & 0xFFFF0000; 2511 2512 DPRINTF("xhci: output ep0 context: %08x %08x %08x %08x %08x\n", 2513 ep0_ctx[0], ep0_ctx[1], ep0_ctx[2], ep0_ctx[3], ep0_ctx[4]); 2514 2515 xhci_dma_write_u32s(xhci, octx+32, ep0_ctx, sizeof(ep0_ctx)); 2516 } 2517 2518 return CC_SUCCESS; 2519 } 2520 2521 static TRBCCode xhci_reset_slot(XHCIState *xhci, unsigned int slotid) 2522 { 2523 uint32_t slot_ctx[4]; 2524 dma_addr_t octx; 2525 int i; 2526 2527 trace_usb_xhci_slot_reset(slotid); 2528 assert(slotid >= 1 && slotid <= xhci->numslots); 2529 2530 octx = xhci->slots[slotid-1].ctx; 2531 2532 DPRINTF("xhci: output context at "DMA_ADDR_FMT"\n", octx); 2533 2534 for (i = 2; i <= 31; i++) { 2535 if (xhci->slots[slotid-1].eps[i-1]) { 2536 xhci_disable_ep(xhci, slotid, i); 2537 } 2538 } 2539 2540 xhci_dma_read_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2541 slot_ctx[3] &= ~(SLOT_STATE_MASK << SLOT_STATE_SHIFT); 2542 slot_ctx[3] |= SLOT_DEFAULT << SLOT_STATE_SHIFT; 2543 DPRINTF("xhci: output slot context: %08x %08x %08x %08x\n", 2544 slot_ctx[0], slot_ctx[1], slot_ctx[2], slot_ctx[3]); 2545 xhci_dma_write_u32s(xhci, octx, slot_ctx, sizeof(slot_ctx)); 2546 2547 return CC_SUCCESS; 2548 } 2549 2550 static unsigned int xhci_get_slot(XHCIState *xhci, XHCIEvent *event, XHCITRB *trb) 2551 { 2552 unsigned int slotid; 2553 slotid = (trb->control >> TRB_CR_SLOTID_SHIFT) & TRB_CR_SLOTID_MASK; 2554 if (slotid < 1 || slotid > xhci->numslots) { 2555 DPRINTF("xhci: bad slot id %d\n", slotid); 2556 event->ccode = CC_TRB_ERROR; 2557 return 0; 2558 } else if (!xhci->slots[slotid-1].enabled) { 2559 DPRINTF("xhci: slot id %d not enabled\n", slotid); 2560 event->ccode = CC_SLOT_NOT_ENABLED_ERROR; 2561 return 0; 2562 } 2563 return slotid; 2564 } 2565 2566 /* cleanup slot state on usb device detach */ 2567 static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) 2568 { 2569 int slot, ep; 2570 2571 for (slot = 0; slot < xhci->numslots; slot++) { 2572 if (xhci->slots[slot].uport == uport) { 2573 break; 2574 } 2575 } 2576 if (slot == xhci->numslots) { 2577 return; 2578 } 2579 2580 for (ep = 0; ep < 31; ep++) { 2581 if (xhci->slots[slot].eps[ep]) { 2582 xhci_ep_nuke_xfers(xhci, slot + 1, ep + 1, 0); 2583 } 2584 } 2585 xhci->slots[slot].uport = NULL; 2586 } 2587 2588 static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) 2589 { 2590 dma_addr_t ctx; 2591 uint8_t bw_ctx[xhci->numports+1]; 2592 2593 DPRINTF("xhci_get_port_bandwidth()\n"); 2594 2595 ctx = xhci_mask64(pctx); 2596 2597 DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); 2598 2599 /* TODO: actually implement real values here */ 2600 bw_ctx[0] = 0; 2601 memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ 2602 pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); 2603 2604 return CC_SUCCESS; 2605 } 2606 2607 static uint32_t rotl(uint32_t v, unsigned count) 2608 { 2609 count &= 31; 2610 return (v << count) | (v >> (32 - count)); 2611 } 2612 2613 2614 static uint32_t xhci_nec_challenge(uint32_t hi, uint32_t lo) 2615 { 2616 uint32_t val; 2617 val = rotl(lo - 0x49434878, 32 - ((hi>>8) & 0x1F)); 2618 val += rotl(lo + 0x49434878, hi & 0x1F); 2619 val -= rotl(hi ^ 0x49434878, (lo >> 16) & 0x1F); 2620 return ~val; 2621 } 2622 2623 static void xhci_process_commands(XHCIState *xhci) 2624 { 2625 XHCITRB trb; 2626 TRBType type; 2627 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_SUCCESS}; 2628 dma_addr_t addr; 2629 unsigned int i, slotid = 0, count = 0; 2630 2631 DPRINTF("xhci_process_commands()\n"); 2632 if (!xhci_running(xhci)) { 2633 DPRINTF("xhci_process_commands() called while xHC stopped or paused\n"); 2634 return; 2635 } 2636 2637 xhci->crcr_low |= CRCR_CRR; 2638 2639 while ((type = xhci_ring_fetch(xhci, &xhci->cmd_ring, &trb, &addr))) { 2640 event.ptr = addr; 2641 switch (type) { 2642 case CR_ENABLE_SLOT: 2643 for (i = 0; i < xhci->numslots; i++) { 2644 if (!xhci->slots[i].enabled) { 2645 break; 2646 } 2647 } 2648 if (i >= xhci->numslots) { 2649 DPRINTF("xhci: no device slots available\n"); 2650 event.ccode = CC_NO_SLOTS_ERROR; 2651 } else { 2652 slotid = i+1; 2653 event.ccode = xhci_enable_slot(xhci, slotid); 2654 } 2655 break; 2656 case CR_DISABLE_SLOT: 2657 slotid = xhci_get_slot(xhci, &event, &trb); 2658 if (slotid) { 2659 event.ccode = xhci_disable_slot(xhci, slotid); 2660 } 2661 break; 2662 case CR_ADDRESS_DEVICE: 2663 slotid = xhci_get_slot(xhci, &event, &trb); 2664 if (slotid) { 2665 event.ccode = xhci_address_slot(xhci, slotid, trb.parameter, 2666 trb.control & TRB_CR_BSR); 2667 } 2668 break; 2669 case CR_CONFIGURE_ENDPOINT: 2670 slotid = xhci_get_slot(xhci, &event, &trb); 2671 if (slotid) { 2672 event.ccode = xhci_configure_slot(xhci, slotid, trb.parameter, 2673 trb.control & TRB_CR_DC); 2674 } 2675 break; 2676 case CR_EVALUATE_CONTEXT: 2677 slotid = xhci_get_slot(xhci, &event, &trb); 2678 if (slotid) { 2679 event.ccode = xhci_evaluate_slot(xhci, slotid, trb.parameter); 2680 } 2681 break; 2682 case CR_STOP_ENDPOINT: 2683 slotid = xhci_get_slot(xhci, &event, &trb); 2684 if (slotid) { 2685 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2686 & TRB_CR_EPID_MASK; 2687 event.ccode = xhci_stop_ep(xhci, slotid, epid); 2688 } 2689 break; 2690 case CR_RESET_ENDPOINT: 2691 slotid = xhci_get_slot(xhci, &event, &trb); 2692 if (slotid) { 2693 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2694 & TRB_CR_EPID_MASK; 2695 event.ccode = xhci_reset_ep(xhci, slotid, epid); 2696 } 2697 break; 2698 case CR_SET_TR_DEQUEUE: 2699 slotid = xhci_get_slot(xhci, &event, &trb); 2700 if (slotid) { 2701 unsigned int epid = (trb.control >> TRB_CR_EPID_SHIFT) 2702 & TRB_CR_EPID_MASK; 2703 unsigned int streamid = (trb.status >> 16) & 0xffff; 2704 event.ccode = xhci_set_ep_dequeue(xhci, slotid, 2705 epid, streamid, 2706 trb.parameter); 2707 } 2708 break; 2709 case CR_RESET_DEVICE: 2710 slotid = xhci_get_slot(xhci, &event, &trb); 2711 if (slotid) { 2712 event.ccode = xhci_reset_slot(xhci, slotid); 2713 } 2714 break; 2715 case CR_GET_PORT_BANDWIDTH: 2716 event.ccode = xhci_get_port_bandwidth(xhci, trb.parameter); 2717 break; 2718 case CR_VENDOR_NEC_FIRMWARE_REVISION: 2719 if (xhci->nec_quirks) { 2720 event.type = 48; /* NEC reply */ 2721 event.length = 0x3025; 2722 } else { 2723 event.ccode = CC_TRB_ERROR; 2724 } 2725 break; 2726 case CR_VENDOR_NEC_CHALLENGE_RESPONSE: 2727 if (xhci->nec_quirks) { 2728 uint32_t chi = trb.parameter >> 32; 2729 uint32_t clo = trb.parameter; 2730 uint32_t val = xhci_nec_challenge(chi, clo); 2731 event.length = val & 0xFFFF; 2732 event.epid = val >> 16; 2733 slotid = val >> 24; 2734 event.type = 48; /* NEC reply */ 2735 } else { 2736 event.ccode = CC_TRB_ERROR; 2737 } 2738 break; 2739 default: 2740 trace_usb_xhci_unimplemented("command", type); 2741 event.ccode = CC_TRB_ERROR; 2742 break; 2743 } 2744 event.slotid = slotid; 2745 xhci_event(xhci, &event, 0); 2746 2747 if (count++ > COMMAND_LIMIT) { 2748 trace_usb_xhci_enforced_limit("commands"); 2749 return; 2750 } 2751 } 2752 } 2753 2754 static bool xhci_port_have_device(XHCIPort *port) 2755 { 2756 if (!port->uport->dev || !port->uport->dev->attached) { 2757 return false; /* no device present */ 2758 } 2759 if (!((1 << port->uport->dev->speed) & port->speedmask)) { 2760 return false; /* speed mismatch */ 2761 } 2762 return true; 2763 } 2764 2765 static void xhci_port_notify(XHCIPort *port, uint32_t bits) 2766 { 2767 XHCIEvent ev = { ER_PORT_STATUS_CHANGE, CC_SUCCESS, 2768 port->portnr << 24 }; 2769 2770 if ((port->portsc & bits) == bits) { 2771 return; 2772 } 2773 trace_usb_xhci_port_notify(port->portnr, bits); 2774 port->portsc |= bits; 2775 if (!xhci_running(port->xhci)) { 2776 return; 2777 } 2778 xhci_event(port->xhci, &ev, 0); 2779 } 2780 2781 static void xhci_port_update(XHCIPort *port, int is_detach) 2782 { 2783 uint32_t pls = PLS_RX_DETECT; 2784 2785 port->portsc = PORTSC_PP; 2786 if (!is_detach && xhci_port_have_device(port)) { 2787 port->portsc |= PORTSC_CCS; 2788 switch (port->uport->dev->speed) { 2789 case USB_SPEED_LOW: 2790 port->portsc |= PORTSC_SPEED_LOW; 2791 pls = PLS_POLLING; 2792 break; 2793 case USB_SPEED_FULL: 2794 port->portsc |= PORTSC_SPEED_FULL; 2795 pls = PLS_POLLING; 2796 break; 2797 case USB_SPEED_HIGH: 2798 port->portsc |= PORTSC_SPEED_HIGH; 2799 pls = PLS_POLLING; 2800 break; 2801 case USB_SPEED_SUPER: 2802 port->portsc |= PORTSC_SPEED_SUPER; 2803 port->portsc |= PORTSC_PED; 2804 pls = PLS_U0; 2805 break; 2806 } 2807 } 2808 set_field(&port->portsc, pls, PORTSC_PLS); 2809 trace_usb_xhci_port_link(port->portnr, pls); 2810 xhci_port_notify(port, PORTSC_CSC); 2811 } 2812 2813 static void xhci_port_reset(XHCIPort *port, bool warm_reset) 2814 { 2815 trace_usb_xhci_port_reset(port->portnr, warm_reset); 2816 2817 if (!xhci_port_have_device(port)) { 2818 return; 2819 } 2820 2821 usb_device_reset(port->uport->dev); 2822 2823 switch (port->uport->dev->speed) { 2824 case USB_SPEED_SUPER: 2825 if (warm_reset) { 2826 port->portsc |= PORTSC_WRC; 2827 } 2828 /* fall through */ 2829 case USB_SPEED_LOW: 2830 case USB_SPEED_FULL: 2831 case USB_SPEED_HIGH: 2832 set_field(&port->portsc, PLS_U0, PORTSC_PLS); 2833 trace_usb_xhci_port_link(port->portnr, PLS_U0); 2834 port->portsc |= PORTSC_PED; 2835 break; 2836 } 2837 2838 port->portsc &= ~PORTSC_PR; 2839 xhci_port_notify(port, PORTSC_PRC); 2840 } 2841 2842 static void xhci_reset(DeviceState *dev) 2843 { 2844 XHCIState *xhci = XHCI(dev); 2845 int i; 2846 2847 trace_usb_xhci_reset(); 2848 if (!(xhci->usbsts & USBSTS_HCH)) { 2849 DPRINTF("xhci: reset while running!\n"); 2850 } 2851 2852 xhci->usbcmd = 0; 2853 xhci->usbsts = USBSTS_HCH; 2854 xhci->dnctrl = 0; 2855 xhci->crcr_low = 0; 2856 xhci->crcr_high = 0; 2857 xhci->dcbaap_low = 0; 2858 xhci->dcbaap_high = 0; 2859 xhci->config = 0; 2860 2861 for (i = 0; i < xhci->numslots; i++) { 2862 xhci_disable_slot(xhci, i+1); 2863 } 2864 2865 for (i = 0; i < xhci->numports; i++) { 2866 xhci_port_update(xhci->ports + i, 0); 2867 } 2868 2869 for (i = 0; i < xhci->numintrs; i++) { 2870 xhci->intr[i].iman = 0; 2871 xhci->intr[i].imod = 0; 2872 xhci->intr[i].erstsz = 0; 2873 xhci->intr[i].erstba_low = 0; 2874 xhci->intr[i].erstba_high = 0; 2875 xhci->intr[i].erdp_low = 0; 2876 xhci->intr[i].erdp_high = 0; 2877 xhci->intr[i].msix_used = 0; 2878 2879 xhci->intr[i].er_ep_idx = 0; 2880 xhci->intr[i].er_pcs = 1; 2881 xhci->intr[i].ev_buffer_put = 0; 2882 xhci->intr[i].ev_buffer_get = 0; 2883 } 2884 2885 xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); 2886 xhci_mfwrap_update(xhci); 2887 } 2888 2889 static uint64_t xhci_cap_read(void *ptr, hwaddr reg, unsigned size) 2890 { 2891 XHCIState *xhci = ptr; 2892 uint32_t ret; 2893 2894 switch (reg) { 2895 case 0x00: /* HCIVERSION, CAPLENGTH */ 2896 ret = 0x01000000 | LEN_CAP; 2897 break; 2898 case 0x04: /* HCSPARAMS 1 */ 2899 ret = ((xhci->numports_2+xhci->numports_3)<<24) 2900 | (xhci->numintrs<<8) | xhci->numslots; 2901 break; 2902 case 0x08: /* HCSPARAMS 2 */ 2903 ret = 0x0000000f; 2904 break; 2905 case 0x0c: /* HCSPARAMS 3 */ 2906 ret = 0x00000000; 2907 break; 2908 case 0x10: /* HCCPARAMS */ 2909 if (sizeof(dma_addr_t) == 4) { 2910 ret = 0x00080000 | (xhci->max_pstreams_mask << 12); 2911 } else { 2912 ret = 0x00080001 | (xhci->max_pstreams_mask << 12); 2913 } 2914 break; 2915 case 0x14: /* DBOFF */ 2916 ret = OFF_DOORBELL; 2917 break; 2918 case 0x18: /* RTSOFF */ 2919 ret = OFF_RUNTIME; 2920 break; 2921 2922 /* extended capabilities */ 2923 case 0x20: /* Supported Protocol:00 */ 2924 ret = 0x02000402; /* USB 2.0 */ 2925 break; 2926 case 0x24: /* Supported Protocol:04 */ 2927 ret = 0x20425355; /* "USB " */ 2928 break; 2929 case 0x28: /* Supported Protocol:08 */ 2930 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 2931 ret = (xhci->numports_2<<8) | (xhci->numports_3+1); 2932 } else { 2933 ret = (xhci->numports_2<<8) | 1; 2934 } 2935 break; 2936 case 0x2c: /* Supported Protocol:0c */ 2937 ret = 0x00000000; /* reserved */ 2938 break; 2939 case 0x30: /* Supported Protocol:00 */ 2940 ret = 0x03000002; /* USB 3.0 */ 2941 break; 2942 case 0x34: /* Supported Protocol:04 */ 2943 ret = 0x20425355; /* "USB " */ 2944 break; 2945 case 0x38: /* Supported Protocol:08 */ 2946 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 2947 ret = (xhci->numports_3<<8) | 1; 2948 } else { 2949 ret = (xhci->numports_3<<8) | (xhci->numports_2+1); 2950 } 2951 break; 2952 case 0x3c: /* Supported Protocol:0c */ 2953 ret = 0x00000000; /* reserved */ 2954 break; 2955 default: 2956 trace_usb_xhci_unimplemented("cap read", reg); 2957 ret = 0; 2958 } 2959 2960 trace_usb_xhci_cap_read(reg, ret); 2961 return ret; 2962 } 2963 2964 static uint64_t xhci_port_read(void *ptr, hwaddr reg, unsigned size) 2965 { 2966 XHCIPort *port = ptr; 2967 uint32_t ret; 2968 2969 switch (reg) { 2970 case 0x00: /* PORTSC */ 2971 ret = port->portsc; 2972 break; 2973 case 0x04: /* PORTPMSC */ 2974 case 0x08: /* PORTLI */ 2975 ret = 0; 2976 break; 2977 case 0x0c: /* reserved */ 2978 default: 2979 trace_usb_xhci_unimplemented("port read", reg); 2980 ret = 0; 2981 } 2982 2983 trace_usb_xhci_port_read(port->portnr, reg, ret); 2984 return ret; 2985 } 2986 2987 static void xhci_port_write(void *ptr, hwaddr reg, 2988 uint64_t val, unsigned size) 2989 { 2990 XHCIPort *port = ptr; 2991 uint32_t portsc, notify; 2992 2993 trace_usb_xhci_port_write(port->portnr, reg, val); 2994 2995 switch (reg) { 2996 case 0x00: /* PORTSC */ 2997 /* write-1-to-start bits */ 2998 if (val & PORTSC_WPR) { 2999 xhci_port_reset(port, true); 3000 break; 3001 } 3002 if (val & PORTSC_PR) { 3003 xhci_port_reset(port, false); 3004 break; 3005 } 3006 3007 portsc = port->portsc; 3008 notify = 0; 3009 /* write-1-to-clear bits*/ 3010 portsc &= ~(val & (PORTSC_CSC|PORTSC_PEC|PORTSC_WRC|PORTSC_OCC| 3011 PORTSC_PRC|PORTSC_PLC|PORTSC_CEC)); 3012 if (val & PORTSC_LWS) { 3013 /* overwrite PLS only when LWS=1 */ 3014 uint32_t old_pls = get_field(port->portsc, PORTSC_PLS); 3015 uint32_t new_pls = get_field(val, PORTSC_PLS); 3016 switch (new_pls) { 3017 case PLS_U0: 3018 if (old_pls != PLS_U0) { 3019 set_field(&portsc, new_pls, PORTSC_PLS); 3020 trace_usb_xhci_port_link(port->portnr, new_pls); 3021 notify = PORTSC_PLC; 3022 } 3023 break; 3024 case PLS_U3: 3025 if (old_pls < PLS_U3) { 3026 set_field(&portsc, new_pls, PORTSC_PLS); 3027 trace_usb_xhci_port_link(port->portnr, new_pls); 3028 } 3029 break; 3030 case PLS_RESUME: 3031 /* windows does this for some reason, don't spam stderr */ 3032 break; 3033 default: 3034 DPRINTF("%s: ignore pls write (old %d, new %d)\n", 3035 __func__, old_pls, new_pls); 3036 break; 3037 } 3038 } 3039 /* read/write bits */ 3040 portsc &= ~(PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE); 3041 portsc |= (val & (PORTSC_PP|PORTSC_WCE|PORTSC_WDE|PORTSC_WOE)); 3042 port->portsc = portsc; 3043 if (notify) { 3044 xhci_port_notify(port, notify); 3045 } 3046 break; 3047 case 0x04: /* PORTPMSC */ 3048 case 0x08: /* PORTLI */ 3049 default: 3050 trace_usb_xhci_unimplemented("port write", reg); 3051 } 3052 } 3053 3054 static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) 3055 { 3056 XHCIState *xhci = ptr; 3057 uint32_t ret; 3058 3059 switch (reg) { 3060 case 0x00: /* USBCMD */ 3061 ret = xhci->usbcmd; 3062 break; 3063 case 0x04: /* USBSTS */ 3064 ret = xhci->usbsts; 3065 break; 3066 case 0x08: /* PAGESIZE */ 3067 ret = 1; /* 4KiB */ 3068 break; 3069 case 0x14: /* DNCTRL */ 3070 ret = xhci->dnctrl; 3071 break; 3072 case 0x18: /* CRCR low */ 3073 ret = xhci->crcr_low & ~0xe; 3074 break; 3075 case 0x1c: /* CRCR high */ 3076 ret = xhci->crcr_high; 3077 break; 3078 case 0x30: /* DCBAAP low */ 3079 ret = xhci->dcbaap_low; 3080 break; 3081 case 0x34: /* DCBAAP high */ 3082 ret = xhci->dcbaap_high; 3083 break; 3084 case 0x38: /* CONFIG */ 3085 ret = xhci->config; 3086 break; 3087 default: 3088 trace_usb_xhci_unimplemented("oper read", reg); 3089 ret = 0; 3090 } 3091 3092 trace_usb_xhci_oper_read(reg, ret); 3093 return ret; 3094 } 3095 3096 static void xhci_oper_write(void *ptr, hwaddr reg, 3097 uint64_t val, unsigned size) 3098 { 3099 XHCIState *xhci = ptr; 3100 DeviceState *d = DEVICE(ptr); 3101 3102 trace_usb_xhci_oper_write(reg, val); 3103 3104 switch (reg) { 3105 case 0x00: /* USBCMD */ 3106 if ((val & USBCMD_RS) && !(xhci->usbcmd & USBCMD_RS)) { 3107 xhci_run(xhci); 3108 } else if (!(val & USBCMD_RS) && (xhci->usbcmd & USBCMD_RS)) { 3109 xhci_stop(xhci); 3110 } 3111 if (val & USBCMD_CSS) { 3112 /* save state */ 3113 xhci->usbsts &= ~USBSTS_SRE; 3114 } 3115 if (val & USBCMD_CRS) { 3116 /* restore state */ 3117 xhci->usbsts |= USBSTS_SRE; 3118 } 3119 xhci->usbcmd = val & 0xc0f; 3120 xhci_mfwrap_update(xhci); 3121 if (val & USBCMD_HCRST) { 3122 xhci_reset(d); 3123 } 3124 xhci_intx_update(xhci); 3125 break; 3126 3127 case 0x04: /* USBSTS */ 3128 /* these bits are write-1-to-clear */ 3129 xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); 3130 xhci_intx_update(xhci); 3131 break; 3132 3133 case 0x14: /* DNCTRL */ 3134 xhci->dnctrl = val & 0xffff; 3135 break; 3136 case 0x18: /* CRCR low */ 3137 xhci->crcr_low = (val & 0xffffffcf) | (xhci->crcr_low & CRCR_CRR); 3138 break; 3139 case 0x1c: /* CRCR high */ 3140 xhci->crcr_high = val; 3141 if (xhci->crcr_low & (CRCR_CA|CRCR_CS) && (xhci->crcr_low & CRCR_CRR)) { 3142 XHCIEvent event = {ER_COMMAND_COMPLETE, CC_COMMAND_RING_STOPPED}; 3143 xhci->crcr_low &= ~CRCR_CRR; 3144 xhci_event(xhci, &event, 0); 3145 DPRINTF("xhci: command ring stopped (CRCR=%08x)\n", xhci->crcr_low); 3146 } else { 3147 dma_addr_t base = xhci_addr64(xhci->crcr_low & ~0x3f, val); 3148 xhci_ring_init(xhci, &xhci->cmd_ring, base); 3149 } 3150 xhci->crcr_low &= ~(CRCR_CA | CRCR_CS); 3151 break; 3152 case 0x30: /* DCBAAP low */ 3153 xhci->dcbaap_low = val & 0xffffffc0; 3154 break; 3155 case 0x34: /* DCBAAP high */ 3156 xhci->dcbaap_high = val; 3157 break; 3158 case 0x38: /* CONFIG */ 3159 xhci->config = val & 0xff; 3160 break; 3161 default: 3162 trace_usb_xhci_unimplemented("oper write", reg); 3163 } 3164 } 3165 3166 static uint64_t xhci_runtime_read(void *ptr, hwaddr reg, 3167 unsigned size) 3168 { 3169 XHCIState *xhci = ptr; 3170 uint32_t ret = 0; 3171 3172 if (reg < 0x20) { 3173 switch (reg) { 3174 case 0x00: /* MFINDEX */ 3175 ret = xhci_mfindex_get(xhci) & 0x3fff; 3176 break; 3177 default: 3178 trace_usb_xhci_unimplemented("runtime read", reg); 3179 break; 3180 } 3181 } else { 3182 int v = (reg - 0x20) / 0x20; 3183 XHCIInterrupter *intr = &xhci->intr[v]; 3184 switch (reg & 0x1f) { 3185 case 0x00: /* IMAN */ 3186 ret = intr->iman; 3187 break; 3188 case 0x04: /* IMOD */ 3189 ret = intr->imod; 3190 break; 3191 case 0x08: /* ERSTSZ */ 3192 ret = intr->erstsz; 3193 break; 3194 case 0x10: /* ERSTBA low */ 3195 ret = intr->erstba_low; 3196 break; 3197 case 0x14: /* ERSTBA high */ 3198 ret = intr->erstba_high; 3199 break; 3200 case 0x18: /* ERDP low */ 3201 ret = intr->erdp_low; 3202 break; 3203 case 0x1c: /* ERDP high */ 3204 ret = intr->erdp_high; 3205 break; 3206 } 3207 } 3208 3209 trace_usb_xhci_runtime_read(reg, ret); 3210 return ret; 3211 } 3212 3213 static void xhci_runtime_write(void *ptr, hwaddr reg, 3214 uint64_t val, unsigned size) 3215 { 3216 XHCIState *xhci = ptr; 3217 int v = (reg - 0x20) / 0x20; 3218 XHCIInterrupter *intr = &xhci->intr[v]; 3219 trace_usb_xhci_runtime_write(reg, val); 3220 3221 if (reg < 0x20) { 3222 trace_usb_xhci_unimplemented("runtime write", reg); 3223 return; 3224 } 3225 3226 switch (reg & 0x1f) { 3227 case 0x00: /* IMAN */ 3228 if (val & IMAN_IP) { 3229 intr->iman &= ~IMAN_IP; 3230 } 3231 intr->iman &= ~IMAN_IE; 3232 intr->iman |= val & IMAN_IE; 3233 if (v == 0) { 3234 xhci_intx_update(xhci); 3235 } 3236 xhci_msix_update(xhci, v); 3237 break; 3238 case 0x04: /* IMOD */ 3239 intr->imod = val; 3240 break; 3241 case 0x08: /* ERSTSZ */ 3242 intr->erstsz = val & 0xffff; 3243 break; 3244 case 0x10: /* ERSTBA low */ 3245 if (xhci->nec_quirks) { 3246 /* NEC driver bug: it doesn't align this to 64 bytes */ 3247 intr->erstba_low = val & 0xfffffff0; 3248 } else { 3249 intr->erstba_low = val & 0xffffffc0; 3250 } 3251 break; 3252 case 0x14: /* ERSTBA high */ 3253 intr->erstba_high = val; 3254 xhci_er_reset(xhci, v); 3255 break; 3256 case 0x18: /* ERDP low */ 3257 if (val & ERDP_EHB) { 3258 intr->erdp_low &= ~ERDP_EHB; 3259 } 3260 intr->erdp_low = (val & ~ERDP_EHB) | (intr->erdp_low & ERDP_EHB); 3261 if (val & ERDP_EHB) { 3262 dma_addr_t erdp = xhci_addr64(intr->erdp_low, intr->erdp_high); 3263 unsigned int dp_idx = (erdp - intr->er_start) / TRB_SIZE; 3264 if (erdp >= intr->er_start && 3265 erdp < (intr->er_start + TRB_SIZE * intr->er_size) && 3266 dp_idx != intr->er_ep_idx) { 3267 xhci_intr_raise(xhci, v); 3268 } 3269 } 3270 break; 3271 case 0x1c: /* ERDP high */ 3272 intr->erdp_high = val; 3273 break; 3274 default: 3275 trace_usb_xhci_unimplemented("oper write", reg); 3276 } 3277 } 3278 3279 static uint64_t xhci_doorbell_read(void *ptr, hwaddr reg, 3280 unsigned size) 3281 { 3282 /* doorbells always read as 0 */ 3283 trace_usb_xhci_doorbell_read(reg, 0); 3284 return 0; 3285 } 3286 3287 static void xhci_doorbell_write(void *ptr, hwaddr reg, 3288 uint64_t val, unsigned size) 3289 { 3290 XHCIState *xhci = ptr; 3291 unsigned int epid, streamid; 3292 3293 trace_usb_xhci_doorbell_write(reg, val); 3294 3295 if (!xhci_running(xhci)) { 3296 DPRINTF("xhci: wrote doorbell while xHC stopped or paused\n"); 3297 return; 3298 } 3299 3300 reg >>= 2; 3301 3302 if (reg == 0) { 3303 if (val == 0) { 3304 xhci_process_commands(xhci); 3305 } else { 3306 DPRINTF("xhci: bad doorbell 0 write: 0x%x\n", 3307 (uint32_t)val); 3308 } 3309 } else { 3310 epid = val & 0xff; 3311 streamid = (val >> 16) & 0xffff; 3312 if (reg > xhci->numslots) { 3313 DPRINTF("xhci: bad doorbell %d\n", (int)reg); 3314 } else if (epid > 31) { 3315 DPRINTF("xhci: bad doorbell %d write: 0x%x\n", 3316 (int)reg, (uint32_t)val); 3317 } else { 3318 xhci_kick_ep(xhci, reg, epid, streamid); 3319 } 3320 } 3321 } 3322 3323 static void xhci_cap_write(void *opaque, hwaddr addr, uint64_t val, 3324 unsigned width) 3325 { 3326 /* nothing */ 3327 } 3328 3329 static const MemoryRegionOps xhci_cap_ops = { 3330 .read = xhci_cap_read, 3331 .write = xhci_cap_write, 3332 .valid.min_access_size = 1, 3333 .valid.max_access_size = 4, 3334 .impl.min_access_size = 4, 3335 .impl.max_access_size = 4, 3336 .endianness = DEVICE_LITTLE_ENDIAN, 3337 }; 3338 3339 static const MemoryRegionOps xhci_oper_ops = { 3340 .read = xhci_oper_read, 3341 .write = xhci_oper_write, 3342 .valid.min_access_size = 4, 3343 .valid.max_access_size = 4, 3344 .endianness = DEVICE_LITTLE_ENDIAN, 3345 }; 3346 3347 static const MemoryRegionOps xhci_port_ops = { 3348 .read = xhci_port_read, 3349 .write = xhci_port_write, 3350 .valid.min_access_size = 4, 3351 .valid.max_access_size = 4, 3352 .endianness = DEVICE_LITTLE_ENDIAN, 3353 }; 3354 3355 static const MemoryRegionOps xhci_runtime_ops = { 3356 .read = xhci_runtime_read, 3357 .write = xhci_runtime_write, 3358 .valid.min_access_size = 4, 3359 .valid.max_access_size = 4, 3360 .endianness = DEVICE_LITTLE_ENDIAN, 3361 }; 3362 3363 static const MemoryRegionOps xhci_doorbell_ops = { 3364 .read = xhci_doorbell_read, 3365 .write = xhci_doorbell_write, 3366 .valid.min_access_size = 4, 3367 .valid.max_access_size = 4, 3368 .endianness = DEVICE_LITTLE_ENDIAN, 3369 }; 3370 3371 static void xhci_attach(USBPort *usbport) 3372 { 3373 XHCIState *xhci = usbport->opaque; 3374 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3375 3376 xhci_port_update(port, 0); 3377 } 3378 3379 static void xhci_detach(USBPort *usbport) 3380 { 3381 XHCIState *xhci = usbport->opaque; 3382 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3383 3384 xhci_detach_slot(xhci, usbport); 3385 xhci_port_update(port, 1); 3386 } 3387 3388 static void xhci_wakeup(USBPort *usbport) 3389 { 3390 XHCIState *xhci = usbport->opaque; 3391 XHCIPort *port = xhci_lookup_port(xhci, usbport); 3392 3393 if (get_field(port->portsc, PORTSC_PLS) != PLS_U3) { 3394 return; 3395 } 3396 set_field(&port->portsc, PLS_RESUME, PORTSC_PLS); 3397 xhci_port_notify(port, PORTSC_PLC); 3398 } 3399 3400 static void xhci_complete(USBPort *port, USBPacket *packet) 3401 { 3402 XHCITransfer *xfer = container_of(packet, XHCITransfer, packet); 3403 3404 if (packet->status == USB_RET_REMOVE_FROM_QUEUE) { 3405 xhci_ep_nuke_one_xfer(xfer, 0); 3406 return; 3407 } 3408 xhci_try_complete_packet(xfer); 3409 xhci_kick_epctx(xfer->epctx, xfer->streamid); 3410 if (xfer->complete) { 3411 xhci_ep_free_xfer(xfer); 3412 } 3413 } 3414 3415 static void xhci_child_detach(USBPort *uport, USBDevice *child) 3416 { 3417 USBBus *bus = usb_bus_from_device(child); 3418 XHCIState *xhci = container_of(bus, XHCIState, bus); 3419 3420 xhci_detach_slot(xhci, child->port); 3421 } 3422 3423 static USBPortOps xhci_uport_ops = { 3424 .attach = xhci_attach, 3425 .detach = xhci_detach, 3426 .wakeup = xhci_wakeup, 3427 .complete = xhci_complete, 3428 .child_detach = xhci_child_detach, 3429 }; 3430 3431 static int xhci_find_epid(USBEndpoint *ep) 3432 { 3433 if (ep->nr == 0) { 3434 return 1; 3435 } 3436 if (ep->pid == USB_TOKEN_IN) { 3437 return ep->nr * 2 + 1; 3438 } else { 3439 return ep->nr * 2; 3440 } 3441 } 3442 3443 static USBEndpoint *xhci_epid_to_usbep(XHCIEPContext *epctx) 3444 { 3445 USBPort *uport; 3446 uint32_t token; 3447 3448 if (!epctx) { 3449 return NULL; 3450 } 3451 uport = epctx->xhci->slots[epctx->slotid - 1].uport; 3452 token = (epctx->epid & 1) ? USB_TOKEN_IN : USB_TOKEN_OUT; 3453 if (!uport) { 3454 return NULL; 3455 } 3456 return usb_ep_get(uport->dev, token, epctx->epid >> 1); 3457 } 3458 3459 static void xhci_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, 3460 unsigned int stream) 3461 { 3462 XHCIState *xhci = container_of(bus, XHCIState, bus); 3463 int slotid; 3464 3465 DPRINTF("%s\n", __func__); 3466 slotid = ep->dev->addr; 3467 if (slotid == 0 || !xhci->slots[slotid-1].enabled) { 3468 DPRINTF("%s: oops, no slot for dev %d\n", __func__, ep->dev->addr); 3469 return; 3470 } 3471 xhci_kick_ep(xhci, slotid, xhci_find_epid(ep), stream); 3472 } 3473 3474 static USBBusOps xhci_bus_ops = { 3475 .wakeup_endpoint = xhci_wakeup_endpoint, 3476 }; 3477 3478 static void usb_xhci_init(XHCIState *xhci) 3479 { 3480 DeviceState *dev = DEVICE(xhci); 3481 XHCIPort *port; 3482 int i, usbports, speedmask; 3483 3484 xhci->usbsts = USBSTS_HCH; 3485 3486 if (xhci->numports_2 > MAXPORTS_2) { 3487 xhci->numports_2 = MAXPORTS_2; 3488 } 3489 if (xhci->numports_3 > MAXPORTS_3) { 3490 xhci->numports_3 = MAXPORTS_3; 3491 } 3492 usbports = MAX(xhci->numports_2, xhci->numports_3); 3493 xhci->numports = xhci->numports_2 + xhci->numports_3; 3494 3495 usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); 3496 3497 for (i = 0; i < usbports; i++) { 3498 speedmask = 0; 3499 if (i < xhci->numports_2) { 3500 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3501 port = &xhci->ports[i + xhci->numports_3]; 3502 port->portnr = i + 1 + xhci->numports_3; 3503 } else { 3504 port = &xhci->ports[i]; 3505 port->portnr = i + 1; 3506 } 3507 port->uport = &xhci->uports[i]; 3508 port->speedmask = 3509 USB_SPEED_MASK_LOW | 3510 USB_SPEED_MASK_FULL | 3511 USB_SPEED_MASK_HIGH; 3512 snprintf(port->name, sizeof(port->name), "usb2 port #%d", i+1); 3513 speedmask |= port->speedmask; 3514 } 3515 if (i < xhci->numports_3) { 3516 if (xhci_get_flag(xhci, XHCI_FLAG_SS_FIRST)) { 3517 port = &xhci->ports[i]; 3518 port->portnr = i + 1; 3519 } else { 3520 port = &xhci->ports[i + xhci->numports_2]; 3521 port->portnr = i + 1 + xhci->numports_2; 3522 } 3523 port->uport = &xhci->uports[i]; 3524 port->speedmask = USB_SPEED_MASK_SUPER; 3525 snprintf(port->name, sizeof(port->name), "usb3 port #%d", i+1); 3526 speedmask |= port->speedmask; 3527 } 3528 usb_register_port(&xhci->bus, &xhci->uports[i], xhci, i, 3529 &xhci_uport_ops, speedmask); 3530 } 3531 } 3532 3533 static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) 3534 { 3535 int i, ret; 3536 Error *err = NULL; 3537 3538 XHCIState *xhci = XHCI(dev); 3539 3540 dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ 3541 dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ 3542 dev->config[PCI_CACHE_LINE_SIZE] = 0x10; 3543 dev->config[0x60] = 0x30; /* release number */ 3544 3545 if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) { 3546 xhci->nec_quirks = true; 3547 } 3548 if (xhci->numintrs > MAXINTRS) { 3549 xhci->numintrs = MAXINTRS; 3550 } 3551 while (xhci->numintrs & (xhci->numintrs - 1)) { /* ! power of 2 */ 3552 xhci->numintrs++; 3553 } 3554 if (xhci->numintrs < 1) { 3555 xhci->numintrs = 1; 3556 } 3557 if (xhci->numslots > MAXSLOTS) { 3558 xhci->numslots = MAXSLOTS; 3559 } 3560 if (xhci->numslots < 1) { 3561 xhci->numslots = 1; 3562 } 3563 if (xhci_get_flag(xhci, XHCI_FLAG_ENABLE_STREAMS)) { 3564 xhci->max_pstreams_mask = 7; /* == 256 primary streams */ 3565 } else { 3566 xhci->max_pstreams_mask = 0; 3567 } 3568 3569 if (xhci->msi != ON_OFF_AUTO_OFF) { 3570 ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err); 3571 /* Any error other than -ENOTSUP(board's MSI support is broken) 3572 * is a programming error */ 3573 assert(!ret || ret == -ENOTSUP); 3574 if (ret && xhci->msi == ON_OFF_AUTO_ON) { 3575 /* Can't satisfy user's explicit msi=on request, fail */ 3576 error_append_hint(&err, "You have to use msi=auto (default) or " 3577 "msi=off with this machine type.\n"); 3578 error_propagate(errp, err); 3579 return; 3580 } 3581 assert(!err || xhci->msi == ON_OFF_AUTO_AUTO); 3582 /* With msi=auto, we fall back to MSI off silently */ 3583 error_free(err); 3584 } 3585 3586 usb_xhci_init(xhci); 3587 xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); 3588 3589 memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); 3590 memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, 3591 "capabilities", LEN_CAP); 3592 memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, 3593 "operational", 0x400); 3594 memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, 3595 "runtime", LEN_RUNTIME); 3596 memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, 3597 "doorbell", LEN_DOORBELL); 3598 3599 memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); 3600 memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); 3601 memory_region_add_subregion(&xhci->mem, OFF_RUNTIME, &xhci->mem_runtime); 3602 memory_region_add_subregion(&xhci->mem, OFF_DOORBELL, &xhci->mem_doorbell); 3603 3604 for (i = 0; i < xhci->numports; i++) { 3605 XHCIPort *port = &xhci->ports[i]; 3606 uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; 3607 port->xhci = xhci; 3608 memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, 3609 port->name, 0x10); 3610 memory_region_add_subregion(&xhci->mem, offset, &port->mem); 3611 } 3612 3613 pci_register_bar(dev, 0, 3614 PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, 3615 &xhci->mem); 3616 3617 if (pci_bus_is_express(dev->bus) || 3618 xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { 3619 ret = pcie_endpoint_cap_init(dev, 0xa0); 3620 assert(ret >= 0); 3621 } 3622 3623 if (xhci->msix != ON_OFF_AUTO_OFF) { 3624 /* TODO check for errors, and should fail when msix=on */ 3625 msix_init(dev, xhci->numintrs, 3626 &xhci->mem, 0, OFF_MSIX_TABLE, 3627 &xhci->mem, 0, OFF_MSIX_PBA, 3628 0x90, NULL); 3629 } 3630 } 3631 3632 static void usb_xhci_exit(PCIDevice *dev) 3633 { 3634 int i; 3635 XHCIState *xhci = XHCI(dev); 3636 3637 trace_usb_xhci_exit(); 3638 3639 for (i = 0; i < xhci->numslots; i++) { 3640 xhci_disable_slot(xhci, i + 1); 3641 } 3642 3643 if (xhci->mfwrap_timer) { 3644 timer_del(xhci->mfwrap_timer); 3645 timer_free(xhci->mfwrap_timer); 3646 xhci->mfwrap_timer = NULL; 3647 } 3648 3649 memory_region_del_subregion(&xhci->mem, &xhci->mem_cap); 3650 memory_region_del_subregion(&xhci->mem, &xhci->mem_oper); 3651 memory_region_del_subregion(&xhci->mem, &xhci->mem_runtime); 3652 memory_region_del_subregion(&xhci->mem, &xhci->mem_doorbell); 3653 3654 for (i = 0; i < xhci->numports; i++) { 3655 XHCIPort *port = &xhci->ports[i]; 3656 memory_region_del_subregion(&xhci->mem, &port->mem); 3657 } 3658 3659 /* destroy msix memory region */ 3660 if (dev->msix_table && dev->msix_pba 3661 && dev->msix_entry_used) { 3662 msix_uninit(dev, &xhci->mem, &xhci->mem); 3663 } 3664 3665 usb_bus_release(&xhci->bus); 3666 } 3667 3668 static int usb_xhci_post_load(void *opaque, int version_id) 3669 { 3670 XHCIState *xhci = opaque; 3671 PCIDevice *pci_dev = PCI_DEVICE(xhci); 3672 XHCISlot *slot; 3673 XHCIEPContext *epctx; 3674 dma_addr_t dcbaap, pctx; 3675 uint32_t slot_ctx[4]; 3676 uint32_t ep_ctx[5]; 3677 int slotid, epid, state, intr; 3678 3679 dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); 3680 3681 for (slotid = 1; slotid <= xhci->numslots; slotid++) { 3682 slot = &xhci->slots[slotid-1]; 3683 if (!slot->addressed) { 3684 continue; 3685 } 3686 slot->ctx = 3687 xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); 3688 xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); 3689 slot->uport = xhci_lookup_uport(xhci, slot_ctx); 3690 if (!slot->uport) { 3691 /* should not happen, but may trigger on guest bugs */ 3692 slot->enabled = 0; 3693 slot->addressed = 0; 3694 continue; 3695 } 3696 assert(slot->uport && slot->uport->dev); 3697 3698 for (epid = 1; epid <= 31; epid++) { 3699 pctx = slot->ctx + 32 * epid; 3700 xhci_dma_read_u32s(xhci, pctx, ep_ctx, sizeof(ep_ctx)); 3701 state = ep_ctx[0] & EP_STATE_MASK; 3702 if (state == EP_DISABLED) { 3703 continue; 3704 } 3705 epctx = xhci_alloc_epctx(xhci, slotid, epid); 3706 slot->eps[epid-1] = epctx; 3707 xhci_init_epctx(epctx, pctx, ep_ctx); 3708 epctx->state = state; 3709 if (state == EP_RUNNING) { 3710 /* kick endpoint after vmload is finished */ 3711 timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); 3712 } 3713 } 3714 } 3715 3716 for (intr = 0; intr < xhci->numintrs; intr++) { 3717 if (xhci->intr[intr].msix_used) { 3718 msix_vector_use(pci_dev, intr); 3719 } else { 3720 msix_vector_unuse(pci_dev, intr); 3721 } 3722 } 3723 3724 return 0; 3725 } 3726 3727 static const VMStateDescription vmstate_xhci_ring = { 3728 .name = "xhci-ring", 3729 .version_id = 1, 3730 .fields = (VMStateField[]) { 3731 VMSTATE_UINT64(dequeue, XHCIRing), 3732 VMSTATE_BOOL(ccs, XHCIRing), 3733 VMSTATE_END_OF_LIST() 3734 } 3735 }; 3736 3737 static const VMStateDescription vmstate_xhci_port = { 3738 .name = "xhci-port", 3739 .version_id = 1, 3740 .fields = (VMStateField[]) { 3741 VMSTATE_UINT32(portsc, XHCIPort), 3742 VMSTATE_END_OF_LIST() 3743 } 3744 }; 3745 3746 static const VMStateDescription vmstate_xhci_slot = { 3747 .name = "xhci-slot", 3748 .version_id = 1, 3749 .fields = (VMStateField[]) { 3750 VMSTATE_BOOL(enabled, XHCISlot), 3751 VMSTATE_BOOL(addressed, XHCISlot), 3752 VMSTATE_END_OF_LIST() 3753 } 3754 }; 3755 3756 static const VMStateDescription vmstate_xhci_event = { 3757 .name = "xhci-event", 3758 .version_id = 1, 3759 .fields = (VMStateField[]) { 3760 VMSTATE_UINT32(type, XHCIEvent), 3761 VMSTATE_UINT32(ccode, XHCIEvent), 3762 VMSTATE_UINT64(ptr, XHCIEvent), 3763 VMSTATE_UINT32(length, XHCIEvent), 3764 VMSTATE_UINT32(flags, XHCIEvent), 3765 VMSTATE_UINT8(slotid, XHCIEvent), 3766 VMSTATE_UINT8(epid, XHCIEvent), 3767 VMSTATE_END_OF_LIST() 3768 } 3769 }; 3770 3771 static bool xhci_er_full(void *opaque, int version_id) 3772 { 3773 return false; 3774 } 3775 3776 static const VMStateDescription vmstate_xhci_intr = { 3777 .name = "xhci-intr", 3778 .version_id = 1, 3779 .fields = (VMStateField[]) { 3780 /* registers */ 3781 VMSTATE_UINT32(iman, XHCIInterrupter), 3782 VMSTATE_UINT32(imod, XHCIInterrupter), 3783 VMSTATE_UINT32(erstsz, XHCIInterrupter), 3784 VMSTATE_UINT32(erstba_low, XHCIInterrupter), 3785 VMSTATE_UINT32(erstba_high, XHCIInterrupter), 3786 VMSTATE_UINT32(erdp_low, XHCIInterrupter), 3787 VMSTATE_UINT32(erdp_high, XHCIInterrupter), 3788 3789 /* state */ 3790 VMSTATE_BOOL(msix_used, XHCIInterrupter), 3791 VMSTATE_BOOL(er_pcs, XHCIInterrupter), 3792 VMSTATE_UINT64(er_start, XHCIInterrupter), 3793 VMSTATE_UINT32(er_size, XHCIInterrupter), 3794 VMSTATE_UINT32(er_ep_idx, XHCIInterrupter), 3795 3796 /* event queue (used if ring is full) */ 3797 VMSTATE_BOOL(er_full_unused, XHCIInterrupter), 3798 VMSTATE_UINT32_TEST(ev_buffer_put, XHCIInterrupter, xhci_er_full), 3799 VMSTATE_UINT32_TEST(ev_buffer_get, XHCIInterrupter, xhci_er_full), 3800 VMSTATE_STRUCT_ARRAY_TEST(ev_buffer, XHCIInterrupter, EV_QUEUE, 3801 xhci_er_full, 1, 3802 vmstate_xhci_event, XHCIEvent), 3803 3804 VMSTATE_END_OF_LIST() 3805 } 3806 }; 3807 3808 static const VMStateDescription vmstate_xhci = { 3809 .name = "xhci", 3810 .version_id = 1, 3811 .post_load = usb_xhci_post_load, 3812 .fields = (VMStateField[]) { 3813 VMSTATE_PCI_DEVICE(parent_obj, XHCIState), 3814 VMSTATE_MSIX(parent_obj, XHCIState), 3815 3816 VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, 3817 vmstate_xhci_port, XHCIPort), 3818 VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, 3819 vmstate_xhci_slot, XHCISlot), 3820 VMSTATE_STRUCT_VARRAY_UINT32(intr, XHCIState, numintrs, 1, 3821 vmstate_xhci_intr, XHCIInterrupter), 3822 3823 /* Operational Registers */ 3824 VMSTATE_UINT32(usbcmd, XHCIState), 3825 VMSTATE_UINT32(usbsts, XHCIState), 3826 VMSTATE_UINT32(dnctrl, XHCIState), 3827 VMSTATE_UINT32(crcr_low, XHCIState), 3828 VMSTATE_UINT32(crcr_high, XHCIState), 3829 VMSTATE_UINT32(dcbaap_low, XHCIState), 3830 VMSTATE_UINT32(dcbaap_high, XHCIState), 3831 VMSTATE_UINT32(config, XHCIState), 3832 3833 /* Runtime Registers & state */ 3834 VMSTATE_INT64(mfindex_start, XHCIState), 3835 VMSTATE_TIMER_PTR(mfwrap_timer, XHCIState), 3836 VMSTATE_STRUCT(cmd_ring, XHCIState, 1, vmstate_xhci_ring, XHCIRing), 3837 3838 VMSTATE_END_OF_LIST() 3839 } 3840 }; 3841 3842 static Property xhci_properties[] = { 3843 DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO), 3844 DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO), 3845 DEFINE_PROP_BIT("superspeed-ports-first", 3846 XHCIState, flags, XHCI_FLAG_SS_FIRST, true), 3847 DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags, 3848 XHCI_FLAG_FORCE_PCIE_ENDCAP, false), 3849 DEFINE_PROP_BIT("streams", XHCIState, flags, 3850 XHCI_FLAG_ENABLE_STREAMS, true), 3851 DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), 3852 DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), 3853 DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), 3854 DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), 3855 DEFINE_PROP_END_OF_LIST(), 3856 }; 3857 3858 static void xhci_class_init(ObjectClass *klass, void *data) 3859 { 3860 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3861 DeviceClass *dc = DEVICE_CLASS(klass); 3862 3863 dc->vmsd = &vmstate_xhci; 3864 dc->props = xhci_properties; 3865 dc->reset = xhci_reset; 3866 set_bit(DEVICE_CATEGORY_USB, dc->categories); 3867 k->realize = usb_xhci_realize; 3868 k->exit = usb_xhci_exit; 3869 k->class_id = PCI_CLASS_SERIAL_USB; 3870 k->is_express = 1; 3871 } 3872 3873 static const TypeInfo xhci_info = { 3874 .name = TYPE_XHCI, 3875 .parent = TYPE_PCI_DEVICE, 3876 .instance_size = sizeof(XHCIState), 3877 .class_init = xhci_class_init, 3878 .abstract = true, 3879 }; 3880 3881 static void nec_xhci_class_init(ObjectClass *klass, void *data) 3882 { 3883 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3884 3885 k->vendor_id = PCI_VENDOR_ID_NEC; 3886 k->device_id = PCI_DEVICE_ID_NEC_UPD720200; 3887 k->revision = 0x03; 3888 } 3889 3890 static const TypeInfo nec_xhci_info = { 3891 .name = TYPE_NEC_XHCI, 3892 .parent = TYPE_XHCI, 3893 .class_init = nec_xhci_class_init, 3894 }; 3895 3896 static void qemu_xhci_class_init(ObjectClass *klass, void *data) 3897 { 3898 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 3899 3900 k->vendor_id = PCI_VENDOR_ID_REDHAT; 3901 k->device_id = PCI_DEVICE_ID_REDHAT_XHCI; 3902 k->revision = 0x01; 3903 } 3904 3905 static const TypeInfo qemu_xhci_info = { 3906 .name = TYPE_QEMU_XHCI, 3907 .parent = TYPE_XHCI, 3908 .class_init = qemu_xhci_class_init, 3909 }; 3910 3911 static void xhci_register_types(void) 3912 { 3913 type_register_static(&xhci_info); 3914 type_register_static(&nec_xhci_info); 3915 type_register_static(&qemu_xhci_info); 3916 } 3917 3918 type_init(xhci_register_types) 3919