1 /* 2 * Texas Instruments TUSB6010 emulation. 3 * Based on reverse-engineering of a linux driver. 4 * 5 * Copyright (C) 2008 Nokia Corporation 6 * Written by Andrzej Zaborowski <andrew@openedhand.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 or 11 * (at your option) version 3 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/module.h" 24 #include "qemu/timer.h" 25 #include "hw/usb.h" 26 #include "hw/usb/hcd-musb.h" 27 #include "hw/arm/omap.h" 28 #include "hw/hw.h" 29 #include "hw/irq.h" 30 #include "hw/sysbus.h" 31 32 #define TYPE_TUSB6010 "tusb6010" 33 #define TUSB(obj) OBJECT_CHECK(TUSBState, (obj), TYPE_TUSB6010) 34 35 typedef struct TUSBState { 36 SysBusDevice parent_obj; 37 38 MemoryRegion iomem[2]; 39 qemu_irq irq; 40 MUSBState *musb; 41 QEMUTimer *otg_timer; 42 QEMUTimer *pwr_timer; 43 44 int power; 45 uint32_t scratch; 46 uint16_t test_reset; 47 uint32_t prcm_config; 48 uint32_t prcm_mngmt; 49 uint16_t otg_status; 50 uint32_t dev_config; 51 int host_mode; 52 uint32_t intr; 53 uint32_t intr_ok; 54 uint32_t mask; 55 uint32_t usbip_intr; 56 uint32_t usbip_mask; 57 uint32_t gpio_intr; 58 uint32_t gpio_mask; 59 uint32_t gpio_config; 60 uint32_t dma_intr; 61 uint32_t dma_mask; 62 uint32_t dma_map; 63 uint32_t dma_config; 64 uint32_t ep0_config; 65 uint32_t rx_config[15]; 66 uint32_t tx_config[15]; 67 uint32_t wkup_mask; 68 uint32_t pullup[2]; 69 uint32_t control_config; 70 uint32_t otg_timer_val; 71 } TUSBState; 72 73 #define TUSB_DEVCLOCK 60000000 /* 60 MHz */ 74 75 #define TUSB_VLYNQ_CTRL 0x004 76 77 /* Mentor Graphics OTG core registers. */ 78 #define TUSB_BASE_OFFSET 0x400 79 80 /* FIFO registers, 32-bit. */ 81 #define TUSB_FIFO_BASE 0x600 82 83 /* Device System & Control registers, 32-bit. */ 84 #define TUSB_SYS_REG_BASE 0x800 85 86 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) 87 #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) 88 #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) 89 #define TUSB_DEV_CONF_SOFT_ID (1 << 1) 90 #define TUSB_DEV_CONF_ID_SEL (1 << 0) 91 92 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) 93 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) 94 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) 95 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) 96 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) 97 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) 98 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) 99 #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) 100 #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) 101 #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) 102 #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) 103 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) 104 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) 105 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) 106 #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) 107 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) 108 #define TUSB_PHY_OTG_CTRL_PD (1 << 6) 109 #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) 110 #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) 111 #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) 112 #define TUSB_PHY_OTG_CTRL_RESET (1 << 2) 113 #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) 114 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) 115 116 /* OTG status register */ 117 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) 118 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) 119 #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) 120 #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) 121 #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) 122 #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) 123 #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) 124 #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) 125 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) 126 #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) 127 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) 128 129 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) 130 #define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) 131 #define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) 132 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) 133 134 /* PRCM configuration register */ 135 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) 136 #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) 137 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) 138 139 /* PRCM management register */ 140 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) 141 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) 142 #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) 143 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) 144 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) 145 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) 146 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) 147 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) 148 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) 149 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) 150 #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) 151 #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) 152 #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) 153 #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) 154 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) 155 156 /* Wake-up source clear and mask registers */ 157 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) 158 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) 159 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) 160 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) 161 #define TUSB_PRCM_WGPIO_7 (1 << 12) 162 #define TUSB_PRCM_WGPIO_6 (1 << 11) 163 #define TUSB_PRCM_WGPIO_5 (1 << 10) 164 #define TUSB_PRCM_WGPIO_4 (1 << 9) 165 #define TUSB_PRCM_WGPIO_3 (1 << 8) 166 #define TUSB_PRCM_WGPIO_2 (1 << 7) 167 #define TUSB_PRCM_WGPIO_1 (1 << 6) 168 #define TUSB_PRCM_WGPIO_0 (1 << 5) 169 #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ 170 #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ 171 #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ 172 #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ 173 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ 174 175 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) 176 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) 177 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) 178 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) 179 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) 180 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) 181 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) 182 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) 183 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) 184 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) 185 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) 186 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) 187 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) 188 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) 189 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) 190 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) 191 192 /* NOR flash interrupt source registers */ 193 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) 194 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) 195 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) 196 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) 197 #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) 198 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17) 199 #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) 200 #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) 201 #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) 202 #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) 203 #define TUSB_INT_SRC_DEV_READY (1 << 12) 204 #define TUSB_INT_SRC_USB_IP_TX (1 << 9) 205 #define TUSB_INT_SRC_USB_IP_RX (1 << 8) 206 #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) 207 #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) 208 #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) 209 #define TUSB_INT_SRC_USB_IP_CONN (1 << 4) 210 #define TUSB_INT_SRC_USB_IP_SOF (1 << 3) 211 #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) 212 #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) 213 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) 214 215 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) 216 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) 217 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) 218 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) 219 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) 220 #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) 221 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) 222 #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) 223 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) 224 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) 225 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) 226 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) 227 228 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) 229 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) 230 231 /* Device System & Control register bitfields */ 232 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) 233 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) 234 #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) 235 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) 236 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) 237 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) 238 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) 239 #define TUSB_EP0_CONFIG_SW_EN (1 << 8) 240 #define TUSB_EP0_CONFIG_DIR_TX (1 << 7) 241 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) 242 #define TUSB_EP_CONFIG_SW_EN (1 << 31) 243 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) 244 #define TUSB_PROD_TEST_RESET_VAL 0xa596 245 246 static void tusb_intr_update(TUSBState *s) 247 { 248 if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY) 249 qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); 250 else 251 qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); 252 } 253 254 static void tusb_usbip_intr_update(TUSBState *s) 255 { 256 /* TX interrupt in the MUSB */ 257 if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) 258 s->intr |= TUSB_INT_SRC_USB_IP_TX; 259 else 260 s->intr &= ~TUSB_INT_SRC_USB_IP_TX; 261 262 /* RX interrupt in the MUSB */ 263 if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) 264 s->intr |= TUSB_INT_SRC_USB_IP_RX; 265 else 266 s->intr &= ~TUSB_INT_SRC_USB_IP_RX; 267 268 /* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */ 269 270 tusb_intr_update(s); 271 } 272 273 static void tusb_dma_intr_update(TUSBState *s) 274 { 275 if (s->dma_intr & ~s->dma_mask) 276 s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; 277 else 278 s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; 279 280 tusb_intr_update(s); 281 } 282 283 static void tusb_gpio_intr_update(TUSBState *s) 284 { 285 /* TODO: How is this signalled? */ 286 } 287 288 static uint32_t tusb_async_readb(void *opaque, hwaddr addr) 289 { 290 TUSBState *s = (TUSBState *) opaque; 291 292 switch (addr & 0xfff) { 293 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 294 return musb_read[0](s->musb, addr & 0x1ff); 295 296 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 297 return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); 298 } 299 300 printf("%s: unknown register at %03x\n", 301 __func__, (int) (addr & 0xfff)); 302 return 0; 303 } 304 305 static uint32_t tusb_async_readh(void *opaque, hwaddr addr) 306 { 307 TUSBState *s = (TUSBState *) opaque; 308 309 switch (addr & 0xfff) { 310 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 311 return musb_read[1](s->musb, addr & 0x1ff); 312 313 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 314 return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); 315 } 316 317 printf("%s: unknown register at %03x\n", 318 __func__, (int) (addr & 0xfff)); 319 return 0; 320 } 321 322 static uint32_t tusb_async_readw(void *opaque, hwaddr addr) 323 { 324 TUSBState *s = (TUSBState *) opaque; 325 int offset = addr & 0xfff; 326 int epnum; 327 uint32_t ret; 328 329 switch (offset) { 330 case TUSB_DEV_CONF: 331 return s->dev_config; 332 333 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 334 return musb_read[2](s->musb, offset & 0x1ff); 335 336 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 337 return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); 338 339 case TUSB_PHY_OTG_CTRL_ENABLE: 340 case TUSB_PHY_OTG_CTRL: 341 return 0x00; /* TODO */ 342 343 case TUSB_DEV_OTG_STAT: 344 ret = s->otg_status; 345 #if 0 346 if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) 347 ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; 348 #endif 349 return ret; 350 case TUSB_DEV_OTG_TIMER: 351 return s->otg_timer_val; 352 353 case TUSB_PRCM_REV: 354 return 0x20; 355 case TUSB_PRCM_CONF: 356 return s->prcm_config; 357 case TUSB_PRCM_MNGMT: 358 return s->prcm_mngmt; 359 case TUSB_PRCM_WAKEUP_SOURCE: 360 case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ 361 return 0x00000000; 362 case TUSB_PRCM_WAKEUP_MASK: 363 return s->wkup_mask; 364 365 case TUSB_PULLUP_1_CTRL: 366 return s->pullup[0]; 367 case TUSB_PULLUP_2_CTRL: 368 return s->pullup[1]; 369 370 case TUSB_INT_CTRL_REV: 371 return 0x20; 372 case TUSB_INT_CTRL_CONF: 373 return s->control_config; 374 375 case TUSB_USBIP_INT_SRC: 376 case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ 377 case TUSB_USBIP_INT_CLEAR: 378 return s->usbip_intr; 379 case TUSB_USBIP_INT_MASK: 380 return s->usbip_mask; 381 382 case TUSB_DMA_INT_SRC: 383 case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ 384 case TUSB_DMA_INT_CLEAR: 385 return s->dma_intr; 386 case TUSB_DMA_INT_MASK: 387 return s->dma_mask; 388 389 case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ 390 case TUSB_GPIO_INT_SET: 391 case TUSB_GPIO_INT_CLEAR: 392 return s->gpio_intr; 393 case TUSB_GPIO_INT_MASK: 394 return s->gpio_mask; 395 396 case TUSB_INT_SRC: 397 case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ 398 case TUSB_INT_SRC_CLEAR: 399 return s->intr; 400 case TUSB_INT_MASK: 401 return s->mask; 402 403 case TUSB_GPIO_REV: 404 return 0x30; 405 case TUSB_GPIO_CONF: 406 return s->gpio_config; 407 408 case TUSB_DMA_CTRL_REV: 409 return 0x30; 410 case TUSB_DMA_REQ_CONF: 411 return s->dma_config; 412 case TUSB_EP0_CONF: 413 return s->ep0_config; 414 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): 415 epnum = (offset - TUSB_EP_IN_SIZE) >> 2; 416 return s->tx_config[epnum]; 417 case TUSB_DMA_EP_MAP: 418 return s->dma_map; 419 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): 420 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2; 421 return s->rx_config[epnum]; 422 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ... 423 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b): 424 return 0x00000000; /* TODO */ 425 case TUSB_WAIT_COUNT: 426 return 0x00; /* TODO */ 427 428 case TUSB_SCRATCH_PAD: 429 return s->scratch; 430 431 case TUSB_PROD_TEST_RESET: 432 return s->test_reset; 433 434 /* DIE IDs */ 435 case TUSB_DIDR1_LO: 436 return 0xa9453c59; 437 case TUSB_DIDR1_HI: 438 return 0x54059adf; 439 } 440 441 printf("%s: unknown register at %03x\n", __func__, offset); 442 return 0; 443 } 444 445 static void tusb_async_writeb(void *opaque, hwaddr addr, 446 uint32_t value) 447 { 448 TUSBState *s = (TUSBState *) opaque; 449 450 switch (addr & 0xfff) { 451 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 452 musb_write[0](s->musb, addr & 0x1ff, value); 453 break; 454 455 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 456 musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); 457 break; 458 459 default: 460 printf("%s: unknown register at %03x\n", 461 __func__, (int) (addr & 0xfff)); 462 return; 463 } 464 } 465 466 static void tusb_async_writeh(void *opaque, hwaddr addr, 467 uint32_t value) 468 { 469 TUSBState *s = (TUSBState *) opaque; 470 471 switch (addr & 0xfff) { 472 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 473 musb_write[1](s->musb, addr & 0x1ff, value); 474 break; 475 476 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 477 musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); 478 break; 479 480 default: 481 printf("%s: unknown register at %03x\n", 482 __func__, (int) (addr & 0xfff)); 483 return; 484 } 485 } 486 487 static void tusb_async_writew(void *opaque, hwaddr addr, 488 uint32_t value) 489 { 490 TUSBState *s = (TUSBState *) opaque; 491 int offset = addr & 0xfff; 492 int epnum; 493 494 switch (offset) { 495 case TUSB_VLYNQ_CTRL: 496 break; 497 498 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 499 musb_write[2](s->musb, offset & 0x1ff, value); 500 break; 501 502 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 503 musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); 504 break; 505 506 case TUSB_DEV_CONF: 507 s->dev_config = value; 508 s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); 509 if (value & TUSB_DEV_CONF_PROD_TEST_MODE) 510 hw_error("%s: Product Test mode not allowed\n", __func__); 511 break; 512 513 case TUSB_PHY_OTG_CTRL_ENABLE: 514 case TUSB_PHY_OTG_CTRL: 515 return; /* TODO */ 516 case TUSB_DEV_OTG_TIMER: 517 s->otg_timer_val = value; 518 if (value & TUSB_DEV_OTG_TIMER_ENABLE) 519 timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 520 muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), 521 NANOSECONDS_PER_SECOND, TUSB_DEVCLOCK)); 522 else 523 timer_del(s->otg_timer); 524 break; 525 526 case TUSB_PRCM_CONF: 527 s->prcm_config = value; 528 break; 529 case TUSB_PRCM_MNGMT: 530 s->prcm_mngmt = value; 531 break; 532 case TUSB_PRCM_WAKEUP_CLEAR: 533 break; 534 case TUSB_PRCM_WAKEUP_MASK: 535 s->wkup_mask = value; 536 break; 537 538 case TUSB_PULLUP_1_CTRL: 539 s->pullup[0] = value; 540 break; 541 case TUSB_PULLUP_2_CTRL: 542 s->pullup[1] = value; 543 break; 544 case TUSB_INT_CTRL_CONF: 545 s->control_config = value; 546 tusb_intr_update(s); 547 break; 548 549 case TUSB_USBIP_INT_SET: 550 s->usbip_intr |= value; 551 tusb_usbip_intr_update(s); 552 break; 553 case TUSB_USBIP_INT_CLEAR: 554 s->usbip_intr &= ~value; 555 tusb_usbip_intr_update(s); 556 musb_core_intr_clear(s->musb, ~value); 557 break; 558 case TUSB_USBIP_INT_MASK: 559 s->usbip_mask = value; 560 tusb_usbip_intr_update(s); 561 break; 562 563 case TUSB_DMA_INT_SET: 564 s->dma_intr |= value; 565 tusb_dma_intr_update(s); 566 break; 567 case TUSB_DMA_INT_CLEAR: 568 s->dma_intr &= ~value; 569 tusb_dma_intr_update(s); 570 break; 571 case TUSB_DMA_INT_MASK: 572 s->dma_mask = value; 573 tusb_dma_intr_update(s); 574 break; 575 576 case TUSB_GPIO_INT_SET: 577 s->gpio_intr |= value; 578 tusb_gpio_intr_update(s); 579 break; 580 case TUSB_GPIO_INT_CLEAR: 581 s->gpio_intr &= ~value; 582 tusb_gpio_intr_update(s); 583 break; 584 case TUSB_GPIO_INT_MASK: 585 s->gpio_mask = value; 586 tusb_gpio_intr_update(s); 587 break; 588 589 case TUSB_INT_SRC_SET: 590 s->intr |= value; 591 tusb_intr_update(s); 592 break; 593 case TUSB_INT_SRC_CLEAR: 594 s->intr &= ~value; 595 tusb_intr_update(s); 596 break; 597 case TUSB_INT_MASK: 598 s->mask = value; 599 tusb_intr_update(s); 600 break; 601 602 case TUSB_GPIO_CONF: 603 s->gpio_config = value; 604 break; 605 case TUSB_DMA_REQ_CONF: 606 s->dma_config = value; 607 break; 608 case TUSB_EP0_CONF: 609 s->ep0_config = value & 0x1ff; 610 musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value), 611 value & TUSB_EP0_CONFIG_DIR_TX); 612 break; 613 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): 614 epnum = (offset - TUSB_EP_IN_SIZE) >> 2; 615 s->tx_config[epnum] = value; 616 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); 617 break; 618 case TUSB_DMA_EP_MAP: 619 s->dma_map = value; 620 break; 621 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): 622 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2; 623 s->rx_config[epnum] = value; 624 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); 625 break; 626 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ... 627 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b): 628 return; /* TODO */ 629 case TUSB_WAIT_COUNT: 630 return; /* TODO */ 631 632 case TUSB_SCRATCH_PAD: 633 s->scratch = value; 634 break; 635 636 case TUSB_PROD_TEST_RESET: 637 s->test_reset = value; 638 break; 639 640 default: 641 printf("%s: unknown register at %03x\n", __func__, offset); 642 return; 643 } 644 } 645 646 static uint64_t tusb_async_readfn(void *opaque, hwaddr addr, unsigned size) 647 { 648 switch (size) { 649 case 1: 650 return tusb_async_readb(opaque, addr); 651 case 2: 652 return tusb_async_readh(opaque, addr); 653 case 4: 654 return tusb_async_readw(opaque, addr); 655 default: 656 g_assert_not_reached(); 657 } 658 } 659 660 static void tusb_async_writefn(void *opaque, hwaddr addr, 661 uint64_t value, unsigned size) 662 { 663 switch (size) { 664 case 1: 665 tusb_async_writeb(opaque, addr, value); 666 break; 667 case 2: 668 tusb_async_writeh(opaque, addr, value); 669 break; 670 case 4: 671 tusb_async_writew(opaque, addr, value); 672 break; 673 default: 674 g_assert_not_reached(); 675 } 676 } 677 678 static const MemoryRegionOps tusb_async_ops = { 679 .read = tusb_async_readfn, 680 .write = tusb_async_writefn, 681 .valid.min_access_size = 1, 682 .valid.max_access_size = 4, 683 .endianness = DEVICE_NATIVE_ENDIAN, 684 }; 685 686 static void tusb_otg_tick(void *opaque) 687 { 688 TUSBState *s = (TUSBState *) opaque; 689 690 s->otg_timer_val = 0; 691 s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; 692 tusb_intr_update(s); 693 } 694 695 static void tusb_power_tick(void *opaque) 696 { 697 TUSBState *s = (TUSBState *) opaque; 698 699 if (s->power) { 700 s->intr_ok = ~0; 701 tusb_intr_update(s); 702 } 703 } 704 705 static void tusb_musb_core_intr(void *opaque, int source, int level) 706 { 707 TUSBState *s = (TUSBState *) opaque; 708 uint16_t otg_status = s->otg_status; 709 710 switch (source) { 711 case musb_set_vbus: 712 if (level) 713 otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; 714 else 715 otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; 716 717 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */ 718 /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */ 719 if (s->otg_status != otg_status) { 720 s->otg_status = otg_status; 721 s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; 722 tusb_intr_update(s); 723 } 724 break; 725 726 case musb_set_session: 727 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */ 728 /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */ 729 if (level) { 730 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; 731 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; 732 } else { 733 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; 734 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; 735 } 736 737 /* XXX: some IRQ or anything? */ 738 break; 739 740 case musb_irq_tx: 741 case musb_irq_rx: 742 s->usbip_intr = musb_core_intr_get(s->musb); 743 /* Fall through. */ 744 default: 745 if (level) 746 s->intr |= 1 << source; 747 else 748 s->intr &= ~(1 << source); 749 tusb_intr_update(s); 750 break; 751 } 752 } 753 754 static void tusb6010_power(TUSBState *s, int on) 755 { 756 if (!on) { 757 s->power = 0; 758 } else if (!s->power && on) { 759 s->power = 1; 760 /* Pull the interrupt down after TUSB6010 comes up. */ 761 s->intr_ok = 0; 762 tusb_intr_update(s); 763 timer_mod(s->pwr_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 764 NANOSECONDS_PER_SECOND / 2); 765 } 766 } 767 768 static void tusb6010_irq(void *opaque, int source, int level) 769 { 770 if (source) { 771 tusb_musb_core_intr(opaque, source - 1, level); 772 } else { 773 tusb6010_power(opaque, level); 774 } 775 } 776 777 static void tusb6010_reset(DeviceState *dev) 778 { 779 TUSBState *s = TUSB(dev); 780 int i; 781 782 s->test_reset = TUSB_PROD_TEST_RESET_VAL; 783 s->host_mode = 0; 784 s->dev_config = 0; 785 s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ 786 s->power = 0; 787 s->mask = 0xffffffff; 788 s->intr = 0x00000000; 789 s->otg_timer_val = 0; 790 s->scratch = 0; 791 s->prcm_config = 0; 792 s->prcm_mngmt = 0; 793 s->intr_ok = 0; 794 s->usbip_intr = 0; 795 s->usbip_mask = 0; 796 s->gpio_intr = 0; 797 s->gpio_mask = 0; 798 s->gpio_config = 0; 799 s->dma_intr = 0; 800 s->dma_mask = 0; 801 s->dma_map = 0; 802 s->dma_config = 0; 803 s->ep0_config = 0; 804 s->wkup_mask = 0; 805 s->pullup[0] = s->pullup[1] = 0; 806 s->control_config = 0; 807 for (i = 0; i < 15; i++) { 808 s->rx_config[i] = s->tx_config[i] = 0; 809 } 810 musb_reset(s->musb); 811 } 812 813 static void tusb6010_realize(DeviceState *dev, Error **errp) 814 { 815 TUSBState *s = TUSB(dev); 816 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 817 818 s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s); 819 s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s); 820 memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s, 821 "tusb-async", UINT32_MAX); 822 sysbus_init_mmio(sbd, &s->iomem[0]); 823 sysbus_init_mmio(sbd, &s->iomem[1]); 824 sysbus_init_irq(sbd, &s->irq); 825 qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1); 826 s->musb = musb_init(dev, 1); 827 } 828 829 static void tusb6010_class_init(ObjectClass *klass, void *data) 830 { 831 DeviceClass *dc = DEVICE_CLASS(klass); 832 833 dc->realize = tusb6010_realize; 834 dc->reset = tusb6010_reset; 835 } 836 837 static const TypeInfo tusb6010_info = { 838 .name = TYPE_TUSB6010, 839 .parent = TYPE_SYS_BUS_DEVICE, 840 .instance_size = sizeof(TUSBState), 841 .class_init = tusb6010_class_init, 842 }; 843 844 static void tusb6010_register_types(void) 845 { 846 type_register_static(&tusb6010_info); 847 } 848 849 type_init(tusb6010_register_types) 850