1 /* 2 * Texas Instruments TUSB6010 emulation. 3 * Based on reverse-engineering of a linux driver. 4 * 5 * Copyright (C) 2008 Nokia Corporation 6 * Written by Andrzej Zaborowski <andrew@openedhand.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 or 11 * (at your option) version 3 of the License. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "qemu/module.h" 24 #include "qemu/timer.h" 25 #include "hw/usb.h" 26 #include "hw/usb/hcd-musb.h" 27 #include "hw/arm/omap.h" 28 #include "hw/hw.h" 29 #include "hw/irq.h" 30 #include "hw/sysbus.h" 31 #include "qom/object.h" 32 33 #define TYPE_TUSB6010 "tusb6010" 34 typedef struct TUSBState TUSBState; 35 DECLARE_INSTANCE_CHECKER(TUSBState, TUSB6010, 36 TYPE_TUSB6010) 37 38 struct TUSBState { 39 SysBusDevice parent_obj; 40 41 MemoryRegion iomem[2]; 42 qemu_irq irq; 43 MUSBState *musb; 44 QEMUTimer *otg_timer; 45 QEMUTimer *pwr_timer; 46 47 int power; 48 uint32_t scratch; 49 uint16_t test_reset; 50 uint32_t prcm_config; 51 uint32_t prcm_mngmt; 52 uint16_t otg_status; 53 uint32_t dev_config; 54 int host_mode; 55 uint32_t intr; 56 uint32_t intr_ok; 57 uint32_t mask; 58 uint32_t usbip_intr; 59 uint32_t usbip_mask; 60 uint32_t gpio_intr; 61 uint32_t gpio_mask; 62 uint32_t gpio_config; 63 uint32_t dma_intr; 64 uint32_t dma_mask; 65 uint32_t dma_map; 66 uint32_t dma_config; 67 uint32_t ep0_config; 68 uint32_t rx_config[15]; 69 uint32_t tx_config[15]; 70 uint32_t wkup_mask; 71 uint32_t pullup[2]; 72 uint32_t control_config; 73 uint32_t otg_timer_val; 74 }; 75 76 #define TUSB_DEVCLOCK 60000000 /* 60 MHz */ 77 78 #define TUSB_VLYNQ_CTRL 0x004 79 80 /* Mentor Graphics OTG core registers. */ 81 #define TUSB_BASE_OFFSET 0x400 82 83 /* FIFO registers, 32-bit. */ 84 #define TUSB_FIFO_BASE 0x600 85 86 /* Device System & Control registers, 32-bit. */ 87 #define TUSB_SYS_REG_BASE 0x800 88 89 #define TUSB_DEV_CONF (TUSB_SYS_REG_BASE + 0x000) 90 #define TUSB_DEV_CONF_USB_HOST_MODE (1 << 16) 91 #define TUSB_DEV_CONF_PROD_TEST_MODE (1 << 15) 92 #define TUSB_DEV_CONF_SOFT_ID (1 << 1) 93 #define TUSB_DEV_CONF_ID_SEL (1 << 0) 94 95 #define TUSB_PHY_OTG_CTRL_ENABLE (TUSB_SYS_REG_BASE + 0x004) 96 #define TUSB_PHY_OTG_CTRL (TUSB_SYS_REG_BASE + 0x008) 97 #define TUSB_PHY_OTG_CTRL_WRPROTECT (0xa5 << 24) 98 #define TUSB_PHY_OTG_CTRL_O_ID_PULLUP (1 << 23) 99 #define TUSB_PHY_OTG_CTRL_O_VBUS_DET_EN (1 << 19) 100 #define TUSB_PHY_OTG_CTRL_O_SESS_END_EN (1 << 18) 101 #define TUSB_PHY_OTG_CTRL_TESTM2 (1 << 17) 102 #define TUSB_PHY_OTG_CTRL_TESTM1 (1 << 16) 103 #define TUSB_PHY_OTG_CTRL_TESTM0 (1 << 15) 104 #define TUSB_PHY_OTG_CTRL_TX_DATA2 (1 << 14) 105 #define TUSB_PHY_OTG_CTRL_TX_GZ2 (1 << 13) 106 #define TUSB_PHY_OTG_CTRL_TX_ENABLE2 (1 << 12) 107 #define TUSB_PHY_OTG_CTRL_DM_PULLDOWN (1 << 11) 108 #define TUSB_PHY_OTG_CTRL_DP_PULLDOWN (1 << 10) 109 #define TUSB_PHY_OTG_CTRL_OSC_EN (1 << 9) 110 #define TUSB_PHY_OTG_CTRL_PHYREF_CLK(v) (((v) & 3) << 7) 111 #define TUSB_PHY_OTG_CTRL_PD (1 << 6) 112 #define TUSB_PHY_OTG_CTRL_PLL_ON (1 << 5) 113 #define TUSB_PHY_OTG_CTRL_EXT_RPU (1 << 4) 114 #define TUSB_PHY_OTG_CTRL_PWR_GOOD (1 << 3) 115 #define TUSB_PHY_OTG_CTRL_RESET (1 << 2) 116 #define TUSB_PHY_OTG_CTRL_SUSPENDM (1 << 1) 117 #define TUSB_PHY_OTG_CTRL_CLK_MODE (1 << 0) 118 119 /* OTG status register */ 120 #define TUSB_DEV_OTG_STAT (TUSB_SYS_REG_BASE + 0x00c) 121 #define TUSB_DEV_OTG_STAT_PWR_CLK_GOOD (1 << 8) 122 #define TUSB_DEV_OTG_STAT_SESS_END (1 << 7) 123 #define TUSB_DEV_OTG_STAT_SESS_VALID (1 << 6) 124 #define TUSB_DEV_OTG_STAT_VBUS_VALID (1 << 5) 125 #define TUSB_DEV_OTG_STAT_VBUS_SENSE (1 << 4) 126 #define TUSB_DEV_OTG_STAT_ID_STATUS (1 << 3) 127 #define TUSB_DEV_OTG_STAT_HOST_DISCON (1 << 2) 128 #define TUSB_DEV_OTG_STAT_LINE_STATE (3 << 0) 129 #define TUSB_DEV_OTG_STAT_DP_ENABLE (1 << 1) 130 #define TUSB_DEV_OTG_STAT_DM_ENABLE (1 << 0) 131 132 #define TUSB_DEV_OTG_TIMER (TUSB_SYS_REG_BASE + 0x010) 133 #define TUSB_DEV_OTG_TIMER_ENABLE (1 << 31) 134 #define TUSB_DEV_OTG_TIMER_VAL(v) ((v) & 0x07ffffff) 135 #define TUSB_PRCM_REV (TUSB_SYS_REG_BASE + 0x014) 136 137 /* PRCM configuration register */ 138 #define TUSB_PRCM_CONF (TUSB_SYS_REG_BASE + 0x018) 139 #define TUSB_PRCM_CONF_SFW_CPEN (1 << 24) 140 #define TUSB_PRCM_CONF_SYS_CLKSEL(v) (((v) & 3) << 16) 141 142 /* PRCM management register */ 143 #define TUSB_PRCM_MNGMT (TUSB_SYS_REG_BASE + 0x01c) 144 #define TUSB_PRCM_MNGMT_SRP_FIX_TMR(v) (((v) & 0xf) << 25) 145 #define TUSB_PRCM_MNGMT_SRP_FIX_EN (1 << 24) 146 #define TUSB_PRCM_MNGMT_VBUS_VAL_TMR(v) (((v) & 0xf) << 20) 147 #define TUSB_PRCM_MNGMT_VBUS_VAL_FLT_EN (1 << 19) 148 #define TUSB_PRCM_MNGMT_DFT_CLK_DIS (1 << 18) 149 #define TUSB_PRCM_MNGMT_VLYNQ_CLK_DIS (1 << 17) 150 #define TUSB_PRCM_MNGMT_OTG_SESS_END_EN (1 << 10) 151 #define TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN (1 << 9) 152 #define TUSB_PRCM_MNGMT_OTG_ID_PULLUP (1 << 8) 153 #define TUSB_PRCM_MNGMT_15_SW_EN (1 << 4) 154 #define TUSB_PRCM_MNGMT_33_SW_EN (1 << 3) 155 #define TUSB_PRCM_MNGMT_5V_CPEN (1 << 2) 156 #define TUSB_PRCM_MNGMT_PM_IDLE (1 << 1) 157 #define TUSB_PRCM_MNGMT_DEV_IDLE (1 << 0) 158 159 /* Wake-up source clear and mask registers */ 160 #define TUSB_PRCM_WAKEUP_SOURCE (TUSB_SYS_REG_BASE + 0x020) 161 #define TUSB_PRCM_WAKEUP_CLEAR (TUSB_SYS_REG_BASE + 0x028) 162 #define TUSB_PRCM_WAKEUP_MASK (TUSB_SYS_REG_BASE + 0x02c) 163 #define TUSB_PRCM_WAKEUP_RESERVED_BITS (0xffffe << 13) 164 #define TUSB_PRCM_WGPIO_7 (1 << 12) 165 #define TUSB_PRCM_WGPIO_6 (1 << 11) 166 #define TUSB_PRCM_WGPIO_5 (1 << 10) 167 #define TUSB_PRCM_WGPIO_4 (1 << 9) 168 #define TUSB_PRCM_WGPIO_3 (1 << 8) 169 #define TUSB_PRCM_WGPIO_2 (1 << 7) 170 #define TUSB_PRCM_WGPIO_1 (1 << 6) 171 #define TUSB_PRCM_WGPIO_0 (1 << 5) 172 #define TUSB_PRCM_WHOSTDISCON (1 << 4) /* Host disconnect */ 173 #define TUSB_PRCM_WBUS (1 << 3) /* USB bus resume */ 174 #define TUSB_PRCM_WNORCS (1 << 2) /* NOR chip select */ 175 #define TUSB_PRCM_WVBUS (1 << 1) /* OTG PHY VBUS */ 176 #define TUSB_PRCM_WID (1 << 0) /* OTG PHY ID detect */ 177 178 #define TUSB_PULLUP_1_CTRL (TUSB_SYS_REG_BASE + 0x030) 179 #define TUSB_PULLUP_2_CTRL (TUSB_SYS_REG_BASE + 0x034) 180 #define TUSB_INT_CTRL_REV (TUSB_SYS_REG_BASE + 0x038) 181 #define TUSB_INT_CTRL_CONF (TUSB_SYS_REG_BASE + 0x03c) 182 #define TUSB_USBIP_INT_SRC (TUSB_SYS_REG_BASE + 0x040) 183 #define TUSB_USBIP_INT_SET (TUSB_SYS_REG_BASE + 0x044) 184 #define TUSB_USBIP_INT_CLEAR (TUSB_SYS_REG_BASE + 0x048) 185 #define TUSB_USBIP_INT_MASK (TUSB_SYS_REG_BASE + 0x04c) 186 #define TUSB_DMA_INT_SRC (TUSB_SYS_REG_BASE + 0x050) 187 #define TUSB_DMA_INT_SET (TUSB_SYS_REG_BASE + 0x054) 188 #define TUSB_DMA_INT_CLEAR (TUSB_SYS_REG_BASE + 0x058) 189 #define TUSB_DMA_INT_MASK (TUSB_SYS_REG_BASE + 0x05c) 190 #define TUSB_GPIO_INT_SRC (TUSB_SYS_REG_BASE + 0x060) 191 #define TUSB_GPIO_INT_SET (TUSB_SYS_REG_BASE + 0x064) 192 #define TUSB_GPIO_INT_CLEAR (TUSB_SYS_REG_BASE + 0x068) 193 #define TUSB_GPIO_INT_MASK (TUSB_SYS_REG_BASE + 0x06c) 194 195 /* NOR flash interrupt source registers */ 196 #define TUSB_INT_SRC (TUSB_SYS_REG_BASE + 0x070) 197 #define TUSB_INT_SRC_SET (TUSB_SYS_REG_BASE + 0x074) 198 #define TUSB_INT_SRC_CLEAR (TUSB_SYS_REG_BASE + 0x078) 199 #define TUSB_INT_MASK (TUSB_SYS_REG_BASE + 0x07c) 200 #define TUSB_INT_SRC_TXRX_DMA_DONE (1 << 24) 201 #define TUSB_INT_SRC_USB_IP_CORE (1 << 17) 202 #define TUSB_INT_SRC_OTG_TIMEOUT (1 << 16) 203 #define TUSB_INT_SRC_VBUS_SENSE_CHNG (1 << 15) 204 #define TUSB_INT_SRC_ID_STATUS_CHNG (1 << 14) 205 #define TUSB_INT_SRC_DEV_WAKEUP (1 << 13) 206 #define TUSB_INT_SRC_DEV_READY (1 << 12) 207 #define TUSB_INT_SRC_USB_IP_TX (1 << 9) 208 #define TUSB_INT_SRC_USB_IP_RX (1 << 8) 209 #define TUSB_INT_SRC_USB_IP_VBUS_ERR (1 << 7) 210 #define TUSB_INT_SRC_USB_IP_VBUS_REQ (1 << 6) 211 #define TUSB_INT_SRC_USB_IP_DISCON (1 << 5) 212 #define TUSB_INT_SRC_USB_IP_CONN (1 << 4) 213 #define TUSB_INT_SRC_USB_IP_SOF (1 << 3) 214 #define TUSB_INT_SRC_USB_IP_RST_BABBLE (1 << 2) 215 #define TUSB_INT_SRC_USB_IP_RESUME (1 << 1) 216 #define TUSB_INT_SRC_USB_IP_SUSPEND (1 << 0) 217 218 #define TUSB_GPIO_REV (TUSB_SYS_REG_BASE + 0x080) 219 #define TUSB_GPIO_CONF (TUSB_SYS_REG_BASE + 0x084) 220 #define TUSB_DMA_CTRL_REV (TUSB_SYS_REG_BASE + 0x100) 221 #define TUSB_DMA_REQ_CONF (TUSB_SYS_REG_BASE + 0x104) 222 #define TUSB_EP0_CONF (TUSB_SYS_REG_BASE + 0x108) 223 #define TUSB_EP_IN_SIZE (TUSB_SYS_REG_BASE + 0x10c) 224 #define TUSB_DMA_EP_MAP (TUSB_SYS_REG_BASE + 0x148) 225 #define TUSB_EP_OUT_SIZE (TUSB_SYS_REG_BASE + 0x14c) 226 #define TUSB_EP_MAX_PACKET_SIZE_OFFSET (TUSB_SYS_REG_BASE + 0x188) 227 #define TUSB_SCRATCH_PAD (TUSB_SYS_REG_BASE + 0x1c4) 228 #define TUSB_WAIT_COUNT (TUSB_SYS_REG_BASE + 0x1c8) 229 #define TUSB_PROD_TEST_RESET (TUSB_SYS_REG_BASE + 0x1d8) 230 231 #define TUSB_DIDR1_LO (TUSB_SYS_REG_BASE + 0x1f8) 232 #define TUSB_DIDR1_HI (TUSB_SYS_REG_BASE + 0x1fc) 233 234 /* Device System & Control register bitfields */ 235 #define TUSB_INT_CTRL_CONF_INT_RLCYC(v) (((v) & 0x7) << 18) 236 #define TUSB_INT_CTRL_CONF_INT_POLARITY (1 << 17) 237 #define TUSB_INT_CTRL_CONF_INT_MODE (1 << 16) 238 #define TUSB_GPIO_CONF_DMAREQ(v) (((v) & 0x3f) << 24) 239 #define TUSB_DMA_REQ_CONF_BURST_SIZE(v) (((v) & 3) << 26) 240 #define TUSB_DMA_REQ_CONF_DMA_RQ_EN(v) (((v) & 0x3f) << 20) 241 #define TUSB_DMA_REQ_CONF_DMA_RQ_ASR(v) (((v) & 0xf) << 16) 242 #define TUSB_EP0_CONFIG_SW_EN (1 << 8) 243 #define TUSB_EP0_CONFIG_DIR_TX (1 << 7) 244 #define TUSB_EP0_CONFIG_XFR_SIZE(v) ((v) & 0x7f) 245 #define TUSB_EP_CONFIG_SW_EN (1 << 31) 246 #define TUSB_EP_CONFIG_XFR_SIZE(v) ((v) & 0x7fffffff) 247 #define TUSB_PROD_TEST_RESET_VAL 0xa596 248 249 static void tusb_intr_update(TUSBState *s) 250 { 251 if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY) 252 qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok); 253 else 254 qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok); 255 } 256 257 static void tusb_usbip_intr_update(TUSBState *s) 258 { 259 /* TX interrupt in the MUSB */ 260 if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask) 261 s->intr |= TUSB_INT_SRC_USB_IP_TX; 262 else 263 s->intr &= ~TUSB_INT_SRC_USB_IP_TX; 264 265 /* RX interrupt in the MUSB */ 266 if (s->usbip_intr & 0xffff0000 & ~s->usbip_mask) 267 s->intr |= TUSB_INT_SRC_USB_IP_RX; 268 else 269 s->intr &= ~TUSB_INT_SRC_USB_IP_RX; 270 271 /* XXX: What about TUSB_INT_SRC_USB_IP_CORE? */ 272 273 tusb_intr_update(s); 274 } 275 276 static void tusb_dma_intr_update(TUSBState *s) 277 { 278 if (s->dma_intr & ~s->dma_mask) 279 s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE; 280 else 281 s->intr &= ~TUSB_INT_SRC_TXRX_DMA_DONE; 282 283 tusb_intr_update(s); 284 } 285 286 static void tusb_gpio_intr_update(TUSBState *s) 287 { 288 /* TODO: How is this signalled? */ 289 } 290 291 static uint32_t tusb_async_readb(void *opaque, hwaddr addr) 292 { 293 TUSBState *s = (TUSBState *) opaque; 294 295 switch (addr & 0xfff) { 296 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 297 return musb_read[0](s->musb, addr & 0x1ff); 298 299 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 300 return musb_read[0](s->musb, 0x20 + ((addr >> 3) & 0x3c)); 301 } 302 303 printf("%s: unknown register at %03x\n", 304 __func__, (int) (addr & 0xfff)); 305 return 0; 306 } 307 308 static uint32_t tusb_async_readh(void *opaque, hwaddr addr) 309 { 310 TUSBState *s = (TUSBState *) opaque; 311 312 switch (addr & 0xfff) { 313 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 314 return musb_read[1](s->musb, addr & 0x1ff); 315 316 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 317 return musb_read[1](s->musb, 0x20 + ((addr >> 3) & 0x3c)); 318 } 319 320 printf("%s: unknown register at %03x\n", 321 __func__, (int) (addr & 0xfff)); 322 return 0; 323 } 324 325 static uint32_t tusb_async_readw(void *opaque, hwaddr addr) 326 { 327 TUSBState *s = (TUSBState *) opaque; 328 int offset = addr & 0xfff; 329 int epnum; 330 uint32_t ret; 331 332 switch (offset) { 333 case TUSB_DEV_CONF: 334 return s->dev_config; 335 336 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 337 return musb_read[2](s->musb, offset & 0x1ff); 338 339 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 340 return musb_read[2](s->musb, 0x20 + ((addr >> 3) & 0x3c)); 341 342 case TUSB_PHY_OTG_CTRL_ENABLE: 343 case TUSB_PHY_OTG_CTRL: 344 return 0x00; /* TODO */ 345 346 case TUSB_DEV_OTG_STAT: 347 ret = s->otg_status; 348 #if 0 349 if (!(s->prcm_mngmt & TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN)) 350 ret &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; 351 #endif 352 return ret; 353 case TUSB_DEV_OTG_TIMER: 354 return s->otg_timer_val; 355 356 case TUSB_PRCM_REV: 357 return 0x20; 358 case TUSB_PRCM_CONF: 359 return s->prcm_config; 360 case TUSB_PRCM_MNGMT: 361 return s->prcm_mngmt; 362 case TUSB_PRCM_WAKEUP_SOURCE: 363 case TUSB_PRCM_WAKEUP_CLEAR: /* TODO: What does this one return? */ 364 return 0x00000000; 365 case TUSB_PRCM_WAKEUP_MASK: 366 return s->wkup_mask; 367 368 case TUSB_PULLUP_1_CTRL: 369 return s->pullup[0]; 370 case TUSB_PULLUP_2_CTRL: 371 return s->pullup[1]; 372 373 case TUSB_INT_CTRL_REV: 374 return 0x20; 375 case TUSB_INT_CTRL_CONF: 376 return s->control_config; 377 378 case TUSB_USBIP_INT_SRC: 379 case TUSB_USBIP_INT_SET: /* TODO: What do these two return? */ 380 case TUSB_USBIP_INT_CLEAR: 381 return s->usbip_intr; 382 case TUSB_USBIP_INT_MASK: 383 return s->usbip_mask; 384 385 case TUSB_DMA_INT_SRC: 386 case TUSB_DMA_INT_SET: /* TODO: What do these two return? */ 387 case TUSB_DMA_INT_CLEAR: 388 return s->dma_intr; 389 case TUSB_DMA_INT_MASK: 390 return s->dma_mask; 391 392 case TUSB_GPIO_INT_SRC: /* TODO: What do these two return? */ 393 case TUSB_GPIO_INT_SET: 394 case TUSB_GPIO_INT_CLEAR: 395 return s->gpio_intr; 396 case TUSB_GPIO_INT_MASK: 397 return s->gpio_mask; 398 399 case TUSB_INT_SRC: 400 case TUSB_INT_SRC_SET: /* TODO: What do these two return? */ 401 case TUSB_INT_SRC_CLEAR: 402 return s->intr; 403 case TUSB_INT_MASK: 404 return s->mask; 405 406 case TUSB_GPIO_REV: 407 return 0x30; 408 case TUSB_GPIO_CONF: 409 return s->gpio_config; 410 411 case TUSB_DMA_CTRL_REV: 412 return 0x30; 413 case TUSB_DMA_REQ_CONF: 414 return s->dma_config; 415 case TUSB_EP0_CONF: 416 return s->ep0_config; 417 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): 418 epnum = (offset - TUSB_EP_IN_SIZE) >> 2; 419 return s->tx_config[epnum]; 420 case TUSB_DMA_EP_MAP: 421 return s->dma_map; 422 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): 423 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2; 424 return s->rx_config[epnum]; 425 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ... 426 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b): 427 return 0x00000000; /* TODO */ 428 case TUSB_WAIT_COUNT: 429 return 0x00; /* TODO */ 430 431 case TUSB_SCRATCH_PAD: 432 return s->scratch; 433 434 case TUSB_PROD_TEST_RESET: 435 return s->test_reset; 436 437 /* DIE IDs */ 438 case TUSB_DIDR1_LO: 439 return 0xa9453c59; 440 case TUSB_DIDR1_HI: 441 return 0x54059adf; 442 } 443 444 printf("%s: unknown register at %03x\n", __func__, offset); 445 return 0; 446 } 447 448 static void tusb_async_writeb(void *opaque, hwaddr addr, 449 uint32_t value) 450 { 451 TUSBState *s = (TUSBState *) opaque; 452 453 switch (addr & 0xfff) { 454 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 455 musb_write[0](s->musb, addr & 0x1ff, value); 456 break; 457 458 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 459 musb_write[0](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); 460 break; 461 462 default: 463 printf("%s: unknown register at %03x\n", 464 __func__, (int) (addr & 0xfff)); 465 return; 466 } 467 } 468 469 static void tusb_async_writeh(void *opaque, hwaddr addr, 470 uint32_t value) 471 { 472 TUSBState *s = (TUSBState *) opaque; 473 474 switch (addr & 0xfff) { 475 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 476 musb_write[1](s->musb, addr & 0x1ff, value); 477 break; 478 479 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 480 musb_write[1](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); 481 break; 482 483 default: 484 printf("%s: unknown register at %03x\n", 485 __func__, (int) (addr & 0xfff)); 486 return; 487 } 488 } 489 490 static void tusb_async_writew(void *opaque, hwaddr addr, 491 uint32_t value) 492 { 493 TUSBState *s = (TUSBState *) opaque; 494 int offset = addr & 0xfff; 495 int epnum; 496 497 switch (offset) { 498 case TUSB_VLYNQ_CTRL: 499 break; 500 501 case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff): 502 musb_write[2](s->musb, offset & 0x1ff, value); 503 break; 504 505 case TUSB_FIFO_BASE ... (TUSB_FIFO_BASE | 0x1ff): 506 musb_write[2](s->musb, 0x20 + ((addr >> 3) & 0x3c), value); 507 break; 508 509 case TUSB_DEV_CONF: 510 s->dev_config = value; 511 s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE); 512 if (value & TUSB_DEV_CONF_PROD_TEST_MODE) 513 hw_error("%s: Product Test mode not allowed\n", __func__); 514 break; 515 516 case TUSB_PHY_OTG_CTRL_ENABLE: 517 case TUSB_PHY_OTG_CTRL: 518 return; /* TODO */ 519 case TUSB_DEV_OTG_TIMER: 520 s->otg_timer_val = value; 521 if (value & TUSB_DEV_OTG_TIMER_ENABLE) 522 timer_mod(s->otg_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 523 muldiv64(TUSB_DEV_OTG_TIMER_VAL(value), 524 NANOSECONDS_PER_SECOND, TUSB_DEVCLOCK)); 525 else 526 timer_del(s->otg_timer); 527 break; 528 529 case TUSB_PRCM_CONF: 530 s->prcm_config = value; 531 break; 532 case TUSB_PRCM_MNGMT: 533 s->prcm_mngmt = value; 534 break; 535 case TUSB_PRCM_WAKEUP_CLEAR: 536 break; 537 case TUSB_PRCM_WAKEUP_MASK: 538 s->wkup_mask = value; 539 break; 540 541 case TUSB_PULLUP_1_CTRL: 542 s->pullup[0] = value; 543 break; 544 case TUSB_PULLUP_2_CTRL: 545 s->pullup[1] = value; 546 break; 547 case TUSB_INT_CTRL_CONF: 548 s->control_config = value; 549 tusb_intr_update(s); 550 break; 551 552 case TUSB_USBIP_INT_SET: 553 s->usbip_intr |= value; 554 tusb_usbip_intr_update(s); 555 break; 556 case TUSB_USBIP_INT_CLEAR: 557 s->usbip_intr &= ~value; 558 tusb_usbip_intr_update(s); 559 musb_core_intr_clear(s->musb, ~value); 560 break; 561 case TUSB_USBIP_INT_MASK: 562 s->usbip_mask = value; 563 tusb_usbip_intr_update(s); 564 break; 565 566 case TUSB_DMA_INT_SET: 567 s->dma_intr |= value; 568 tusb_dma_intr_update(s); 569 break; 570 case TUSB_DMA_INT_CLEAR: 571 s->dma_intr &= ~value; 572 tusb_dma_intr_update(s); 573 break; 574 case TUSB_DMA_INT_MASK: 575 s->dma_mask = value; 576 tusb_dma_intr_update(s); 577 break; 578 579 case TUSB_GPIO_INT_SET: 580 s->gpio_intr |= value; 581 tusb_gpio_intr_update(s); 582 break; 583 case TUSB_GPIO_INT_CLEAR: 584 s->gpio_intr &= ~value; 585 tusb_gpio_intr_update(s); 586 break; 587 case TUSB_GPIO_INT_MASK: 588 s->gpio_mask = value; 589 tusb_gpio_intr_update(s); 590 break; 591 592 case TUSB_INT_SRC_SET: 593 s->intr |= value; 594 tusb_intr_update(s); 595 break; 596 case TUSB_INT_SRC_CLEAR: 597 s->intr &= ~value; 598 tusb_intr_update(s); 599 break; 600 case TUSB_INT_MASK: 601 s->mask = value; 602 tusb_intr_update(s); 603 break; 604 605 case TUSB_GPIO_CONF: 606 s->gpio_config = value; 607 break; 608 case TUSB_DMA_REQ_CONF: 609 s->dma_config = value; 610 break; 611 case TUSB_EP0_CONF: 612 s->ep0_config = value & 0x1ff; 613 musb_set_size(s->musb, 0, TUSB_EP0_CONFIG_XFR_SIZE(value), 614 value & TUSB_EP0_CONFIG_DIR_TX); 615 break; 616 case TUSB_EP_IN_SIZE ... (TUSB_EP_IN_SIZE + 0x3b): 617 epnum = (offset - TUSB_EP_IN_SIZE) >> 2; 618 s->tx_config[epnum] = value; 619 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 1); 620 break; 621 case TUSB_DMA_EP_MAP: 622 s->dma_map = value; 623 break; 624 case TUSB_EP_OUT_SIZE ... (TUSB_EP_OUT_SIZE + 0x3b): 625 epnum = (offset - TUSB_EP_OUT_SIZE) >> 2; 626 s->rx_config[epnum] = value; 627 musb_set_size(s->musb, epnum + 1, TUSB_EP_CONFIG_XFR_SIZE(value), 0); 628 break; 629 case TUSB_EP_MAX_PACKET_SIZE_OFFSET ... 630 (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b): 631 return; /* TODO */ 632 case TUSB_WAIT_COUNT: 633 return; /* TODO */ 634 635 case TUSB_SCRATCH_PAD: 636 s->scratch = value; 637 break; 638 639 case TUSB_PROD_TEST_RESET: 640 s->test_reset = value; 641 break; 642 643 default: 644 printf("%s: unknown register at %03x\n", __func__, offset); 645 return; 646 } 647 } 648 649 static uint64_t tusb_async_readfn(void *opaque, hwaddr addr, unsigned size) 650 { 651 switch (size) { 652 case 1: 653 return tusb_async_readb(opaque, addr); 654 case 2: 655 return tusb_async_readh(opaque, addr); 656 case 4: 657 return tusb_async_readw(opaque, addr); 658 default: 659 g_assert_not_reached(); 660 } 661 } 662 663 static void tusb_async_writefn(void *opaque, hwaddr addr, 664 uint64_t value, unsigned size) 665 { 666 switch (size) { 667 case 1: 668 tusb_async_writeb(opaque, addr, value); 669 break; 670 case 2: 671 tusb_async_writeh(opaque, addr, value); 672 break; 673 case 4: 674 tusb_async_writew(opaque, addr, value); 675 break; 676 default: 677 g_assert_not_reached(); 678 } 679 } 680 681 static const MemoryRegionOps tusb_async_ops = { 682 .read = tusb_async_readfn, 683 .write = tusb_async_writefn, 684 .valid.min_access_size = 1, 685 .valid.max_access_size = 4, 686 .endianness = DEVICE_NATIVE_ENDIAN, 687 }; 688 689 static void tusb_otg_tick(void *opaque) 690 { 691 TUSBState *s = (TUSBState *) opaque; 692 693 s->otg_timer_val = 0; 694 s->intr |= TUSB_INT_SRC_OTG_TIMEOUT; 695 tusb_intr_update(s); 696 } 697 698 static void tusb_power_tick(void *opaque) 699 { 700 TUSBState *s = (TUSBState *) opaque; 701 702 if (s->power) { 703 s->intr_ok = ~0; 704 tusb_intr_update(s); 705 } 706 } 707 708 static void tusb_musb_core_intr(void *opaque, int source, int level) 709 { 710 TUSBState *s = (TUSBState *) opaque; 711 uint16_t otg_status = s->otg_status; 712 713 switch (source) { 714 case musb_set_vbus: 715 if (level) 716 otg_status |= TUSB_DEV_OTG_STAT_VBUS_VALID; 717 else 718 otg_status &= ~TUSB_DEV_OTG_STAT_VBUS_VALID; 719 720 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_VBUS_DET_EN set? */ 721 /* XXX: only if TUSB_PRCM_MNGMT_OTG_VBUS_DET_EN set? */ 722 if (s->otg_status != otg_status) { 723 s->otg_status = otg_status; 724 s->intr |= TUSB_INT_SRC_VBUS_SENSE_CHNG; 725 tusb_intr_update(s); 726 } 727 break; 728 729 case musb_set_session: 730 /* XXX: only if TUSB_PHY_OTG_CTRL_OTG_SESS_END_EN set? */ 731 /* XXX: only if TUSB_PRCM_MNGMT_OTG_SESS_END_EN set? */ 732 if (level) { 733 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_VALID; 734 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_END; 735 } else { 736 s->otg_status &= ~TUSB_DEV_OTG_STAT_SESS_VALID; 737 s->otg_status |= TUSB_DEV_OTG_STAT_SESS_END; 738 } 739 740 /* XXX: some IRQ or anything? */ 741 break; 742 743 case musb_irq_tx: 744 case musb_irq_rx: 745 s->usbip_intr = musb_core_intr_get(s->musb); 746 /* Fall through. */ 747 default: 748 if (level) 749 s->intr |= 1 << source; 750 else 751 s->intr &= ~(1 << source); 752 tusb_intr_update(s); 753 break; 754 } 755 } 756 757 static void tusb6010_power(TUSBState *s, int on) 758 { 759 if (!on) { 760 s->power = 0; 761 } else if (!s->power && on) { 762 s->power = 1; 763 /* Pull the interrupt down after TUSB6010 comes up. */ 764 s->intr_ok = 0; 765 tusb_intr_update(s); 766 timer_mod(s->pwr_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + 767 NANOSECONDS_PER_SECOND / 2); 768 } 769 } 770 771 static void tusb6010_irq(void *opaque, int source, int level) 772 { 773 if (source) { 774 tusb_musb_core_intr(opaque, source - 1, level); 775 } else { 776 tusb6010_power(opaque, level); 777 } 778 } 779 780 static void tusb6010_reset(DeviceState *dev) 781 { 782 TUSBState *s = TUSB6010(dev); 783 int i; 784 785 s->test_reset = TUSB_PROD_TEST_RESET_VAL; 786 s->host_mode = 0; 787 s->dev_config = 0; 788 s->otg_status = 0; /* !TUSB_DEV_OTG_STAT_ID_STATUS means host mode */ 789 s->power = 0; 790 s->mask = 0xffffffff; 791 s->intr = 0x00000000; 792 s->otg_timer_val = 0; 793 s->scratch = 0; 794 s->prcm_config = 0; 795 s->prcm_mngmt = 0; 796 s->intr_ok = 0; 797 s->usbip_intr = 0; 798 s->usbip_mask = 0; 799 s->gpio_intr = 0; 800 s->gpio_mask = 0; 801 s->gpio_config = 0; 802 s->dma_intr = 0; 803 s->dma_mask = 0; 804 s->dma_map = 0; 805 s->dma_config = 0; 806 s->ep0_config = 0; 807 s->wkup_mask = 0; 808 s->pullup[0] = s->pullup[1] = 0; 809 s->control_config = 0; 810 for (i = 0; i < 15; i++) { 811 s->rx_config[i] = s->tx_config[i] = 0; 812 } 813 musb_reset(s->musb); 814 } 815 816 static void tusb6010_realize(DeviceState *dev, Error **errp) 817 { 818 TUSBState *s = TUSB6010(dev); 819 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 820 821 s->otg_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_otg_tick, s); 822 s->pwr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, tusb_power_tick, s); 823 memory_region_init_io(&s->iomem[1], OBJECT(s), &tusb_async_ops, s, 824 "tusb-async", UINT32_MAX); 825 sysbus_init_mmio(sbd, &s->iomem[0]); 826 sysbus_init_mmio(sbd, &s->iomem[1]); 827 sysbus_init_irq(sbd, &s->irq); 828 qdev_init_gpio_in(dev, tusb6010_irq, musb_irq_max + 1); 829 s->musb = musb_init(dev, 1); 830 } 831 832 static void tusb6010_class_init(ObjectClass *klass, void *data) 833 { 834 DeviceClass *dc = DEVICE_CLASS(klass); 835 836 dc->realize = tusb6010_realize; 837 dc->reset = tusb6010_reset; 838 } 839 840 static const TypeInfo tusb6010_info = { 841 .name = TYPE_TUSB6010, 842 .parent = TYPE_SYS_BUS_DEVICE, 843 .instance_size = sizeof(TUSBState), 844 .class_init = tusb6010_class_init, 845 }; 846 847 static void tusb6010_register_types(void) 848 { 849 type_register_static(&tusb6010_info); 850 } 851 852 type_init(tusb6010_register_types) 853