1*2c44220dSMarc-André Lureauxtensa_ss = ss.source_set() 2*2c44220dSMarc-André Lureauxtensa_ss.add(files( 3*2c44220dSMarc-André Lureau 'mx_pic.c', 4*2c44220dSMarc-André Lureau 'pic_cpu.c', 5*2c44220dSMarc-André Lureau 'xtensa_memory.c', 6*2c44220dSMarc-André Lureau)) 7*2c44220dSMarc-André Lureauxtensa_ss.add(when: 'CONFIG_XTENSA_SIM', if_true: files('sim.c')) 8*2c44220dSMarc-André Lureauxtensa_ss.add(when: 'CONFIG_XTENSA_VIRT', if_true: files('virt.c')) 9*2c44220dSMarc-André Lureauxtensa_ss.add(when: 'CONFIG_XTENSA_XTFPGA', if_true: files('xtfpga.c')) 10*2c44220dSMarc-André Lureau 11*2c44220dSMarc-André Lureauhw_arch += {'xtensa': xtensa_ss} 12