1b707ab75SMax Filippov /* 2b707ab75SMax Filippov * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3b707ab75SMax Filippov * All rights reserved. 4b707ab75SMax Filippov * 5b707ab75SMax Filippov * Redistribution and use in source and binary forms, with or without 6b707ab75SMax Filippov * modification, are permitted provided that the following conditions are met: 7b707ab75SMax Filippov * * Redistributions of source code must retain the above copyright 8b707ab75SMax Filippov * notice, this list of conditions and the following disclaimer. 9b707ab75SMax Filippov * * Redistributions in binary form must reproduce the above copyright 10b707ab75SMax Filippov * notice, this list of conditions and the following disclaimer in the 11b707ab75SMax Filippov * documentation and/or other materials provided with the distribution. 12b707ab75SMax Filippov * * Neither the name of the Open Source and Linux Lab nor the 13b707ab75SMax Filippov * names of its contributors may be used to endorse or promote products 14b707ab75SMax Filippov * derived from this software without specific prior written permission. 15b707ab75SMax Filippov * 16b707ab75SMax Filippov * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17b707ab75SMax Filippov * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18b707ab75SMax Filippov * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19b707ab75SMax Filippov * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20b707ab75SMax Filippov * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21b707ab75SMax Filippov * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22b707ab75SMax Filippov * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23b707ab75SMax Filippov * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24b707ab75SMax Filippov * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25b707ab75SMax Filippov * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b707ab75SMax Filippov */ 27b707ab75SMax Filippov 2809aae23dSPeter Maydell #include "qemu/osdep.h" 29da34e65cSMarkus Armbruster #include "qapi/error.h" 304771d756SPaolo Bonzini #include "qemu-common.h" 314771d756SPaolo Bonzini #include "cpu.h" 32b707ab75SMax Filippov #include "sysemu/sysemu.h" 33b707ab75SMax Filippov #include "hw/boards.h" 34b707ab75SMax Filippov #include "hw/loader.h" 35b707ab75SMax Filippov #include "elf.h" 36b707ab75SMax Filippov #include "exec/memory.h" 37b707ab75SMax Filippov #include "exec/address-spaces.h" 38b707ab75SMax Filippov #include "hw/char/serial.h" 39b707ab75SMax Filippov #include "net/net.h" 40b707ab75SMax Filippov #include "hw/sysbus.h" 41b707ab75SMax Filippov #include "hw/block/flash.h" 42fa1d36dfSMarkus Armbruster #include "sysemu/block-backend.h" 438228e353SMarc-André Lureau #include "chardev/char.h" 44996dfe98SMax Filippov #include "sysemu/device_tree.h" 458488ab02SMax Filippov #include "qemu/error-report.h" 46b707ab75SMax Filippov #include "bootparam.h" 47e53fa62cSMax Filippov #include "xtensa_memory.h" 48b707ab75SMax Filippov 49*740ad9f7SMax Filippov typedef struct XtfpgaFlashDesc { 50*740ad9f7SMax Filippov hwaddr base; 51*740ad9f7SMax Filippov size_t size; 52*740ad9f7SMax Filippov size_t boot_base; 53*740ad9f7SMax Filippov size_t sector_size; 54*740ad9f7SMax Filippov } XtfpgaFlashDesc; 55*740ad9f7SMax Filippov 56188ce01dSMax Filippov typedef struct XtfpgaBoardDesc { 57*740ad9f7SMax Filippov const XtfpgaFlashDesc *flash; 58b707ab75SMax Filippov size_t sram_size; 59188ce01dSMax Filippov } XtfpgaBoardDesc; 60b707ab75SMax Filippov 61188ce01dSMax Filippov typedef struct XtfpgaFpgaState { 62b707ab75SMax Filippov MemoryRegion iomem; 63b707ab75SMax Filippov uint32_t leds; 64b707ab75SMax Filippov uint32_t switches; 65188ce01dSMax Filippov } XtfpgaFpgaState; 66b707ab75SMax Filippov 67188ce01dSMax Filippov static void xtfpga_fpga_reset(void *opaque) 68b707ab75SMax Filippov { 69188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 70b707ab75SMax Filippov 71b707ab75SMax Filippov s->leds = 0; 72b707ab75SMax Filippov s->switches = 0; 73b707ab75SMax Filippov } 74b707ab75SMax Filippov 75188ce01dSMax Filippov static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 76b707ab75SMax Filippov unsigned size) 77b707ab75SMax Filippov { 78188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 79b707ab75SMax Filippov 80b707ab75SMax Filippov switch (addr) { 81b707ab75SMax Filippov case 0x0: /*build date code*/ 82b707ab75SMax Filippov return 0x09272011; 83b707ab75SMax Filippov 84b707ab75SMax Filippov case 0x4: /*processor clock frequency, Hz*/ 85b707ab75SMax Filippov return 10000000; 86b707ab75SMax Filippov 87b707ab75SMax Filippov case 0x8: /*LEDs (off = 0, on = 1)*/ 88b707ab75SMax Filippov return s->leds; 89b707ab75SMax Filippov 90b707ab75SMax Filippov case 0xc: /*DIP switches (off = 0, on = 1)*/ 91b707ab75SMax Filippov return s->switches; 92b707ab75SMax Filippov } 93b707ab75SMax Filippov return 0; 94b707ab75SMax Filippov } 95b707ab75SMax Filippov 96188ce01dSMax Filippov static void xtfpga_fpga_write(void *opaque, hwaddr addr, 97b707ab75SMax Filippov uint64_t val, unsigned size) 98b707ab75SMax Filippov { 99188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 100b707ab75SMax Filippov 101b707ab75SMax Filippov switch (addr) { 102b707ab75SMax Filippov case 0x8: /*LEDs (off = 0, on = 1)*/ 103b707ab75SMax Filippov s->leds = val; 104b707ab75SMax Filippov break; 105b707ab75SMax Filippov 106b707ab75SMax Filippov case 0x10: /*board reset*/ 107b707ab75SMax Filippov if (val == 0xdead) { 108cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 109b707ab75SMax Filippov } 110b707ab75SMax Filippov break; 111b707ab75SMax Filippov } 112b707ab75SMax Filippov } 113b707ab75SMax Filippov 114188ce01dSMax Filippov static const MemoryRegionOps xtfpga_fpga_ops = { 115188ce01dSMax Filippov .read = xtfpga_fpga_read, 116188ce01dSMax Filippov .write = xtfpga_fpga_write, 117b707ab75SMax Filippov .endianness = DEVICE_NATIVE_ENDIAN, 118b707ab75SMax Filippov }; 119b707ab75SMax Filippov 120188ce01dSMax Filippov static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 121b707ab75SMax Filippov hwaddr base) 122b707ab75SMax Filippov { 123188ce01dSMax Filippov XtfpgaFpgaState *s = g_malloc(sizeof(XtfpgaFpgaState)); 124b707ab75SMax Filippov 125188ce01dSMax Filippov memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 126188ce01dSMax Filippov "xtfpga.fpga", 0x10000); 127b707ab75SMax Filippov memory_region_add_subregion(address_space, base, &s->iomem); 128188ce01dSMax Filippov xtfpga_fpga_reset(s); 129188ce01dSMax Filippov qemu_register_reset(xtfpga_fpga_reset, s); 130b707ab75SMax Filippov return s; 131b707ab75SMax Filippov } 132b707ab75SMax Filippov 133188ce01dSMax Filippov static void xtfpga_net_init(MemoryRegion *address_space, 134b707ab75SMax Filippov hwaddr base, 135b707ab75SMax Filippov hwaddr descriptors, 136b707ab75SMax Filippov hwaddr buffers, 137b707ab75SMax Filippov qemu_irq irq, NICInfo *nd) 138b707ab75SMax Filippov { 139b707ab75SMax Filippov DeviceState *dev; 140b707ab75SMax Filippov SysBusDevice *s; 141b707ab75SMax Filippov MemoryRegion *ram; 142b707ab75SMax Filippov 143b707ab75SMax Filippov dev = qdev_create(NULL, "open_eth"); 144b707ab75SMax Filippov qdev_set_nic_properties(dev, nd); 145b707ab75SMax Filippov qdev_init_nofail(dev); 146b707ab75SMax Filippov 147b707ab75SMax Filippov s = SYS_BUS_DEVICE(dev); 148b707ab75SMax Filippov sysbus_connect_irq(s, 0, irq); 149b707ab75SMax Filippov memory_region_add_subregion(address_space, base, 150b707ab75SMax Filippov sysbus_mmio_get_region(s, 0)); 151b707ab75SMax Filippov memory_region_add_subregion(address_space, descriptors, 152b707ab75SMax Filippov sysbus_mmio_get_region(s, 1)); 153b707ab75SMax Filippov 154b707ab75SMax Filippov ram = g_malloc(sizeof(*ram)); 1551cfe48c1SPeter Maydell memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16384, 156f8ed85acSMarkus Armbruster &error_fatal); 157b707ab75SMax Filippov vmstate_register_ram_global(ram); 158b707ab75SMax Filippov memory_region_add_subregion(address_space, buffers, ram); 159b707ab75SMax Filippov } 160b707ab75SMax Filippov 16168931a40SMax Filippov static pflash_t *xtfpga_flash_init(MemoryRegion *address_space, 162188ce01dSMax Filippov const XtfpgaBoardDesc *board, 16368931a40SMax Filippov DriveInfo *dinfo, int be) 16468931a40SMax Filippov { 16568931a40SMax Filippov SysBusDevice *s; 16668931a40SMax Filippov DeviceState *dev = qdev_create(NULL, "cfi.pflash01"); 16768931a40SMax Filippov 16868931a40SMax Filippov qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo), 16968931a40SMax Filippov &error_abort); 17068931a40SMax Filippov qdev_prop_set_uint32(dev, "num-blocks", 171*740ad9f7SMax Filippov board->flash->size / board->flash->sector_size); 172*740ad9f7SMax Filippov qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 173f9a555e4SMax Filippov qdev_prop_set_uint8(dev, "width", 2); 17468931a40SMax Filippov qdev_prop_set_bit(dev, "big-endian", be); 175188ce01dSMax Filippov qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 17668931a40SMax Filippov qdev_init_nofail(dev); 17768931a40SMax Filippov s = SYS_BUS_DEVICE(dev); 178*740ad9f7SMax Filippov memory_region_add_subregion(address_space, board->flash->base, 17968931a40SMax Filippov sysbus_mmio_get_region(s, 0)); 18068931a40SMax Filippov return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01"); 18168931a40SMax Filippov } 18268931a40SMax Filippov 183b707ab75SMax Filippov static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 184b707ab75SMax Filippov { 185b707ab75SMax Filippov XtensaCPU *cpu = opaque; 186b707ab75SMax Filippov 187b707ab75SMax Filippov return cpu_get_phys_page_debug(CPU(cpu), addr); 188b707ab75SMax Filippov } 189b707ab75SMax Filippov 190188ce01dSMax Filippov static void xtfpga_reset(void *opaque) 191b707ab75SMax Filippov { 192b707ab75SMax Filippov XtensaCPU *cpu = opaque; 193b707ab75SMax Filippov 194b707ab75SMax Filippov cpu_reset(CPU(cpu)); 195b707ab75SMax Filippov } 196b707ab75SMax Filippov 197188ce01dSMax Filippov static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 1988bb3b575SMax Filippov unsigned size) 1998bb3b575SMax Filippov { 2008bb3b575SMax Filippov return 0; 2018bb3b575SMax Filippov } 2028bb3b575SMax Filippov 203188ce01dSMax Filippov static void xtfpga_io_write(void *opaque, hwaddr addr, 2048bb3b575SMax Filippov uint64_t val, unsigned size) 2058bb3b575SMax Filippov { 2068bb3b575SMax Filippov } 2078bb3b575SMax Filippov 208188ce01dSMax Filippov static const MemoryRegionOps xtfpga_io_ops = { 209188ce01dSMax Filippov .read = xtfpga_io_read, 210188ce01dSMax Filippov .write = xtfpga_io_write, 2118bb3b575SMax Filippov .endianness = DEVICE_NATIVE_ENDIAN, 2128bb3b575SMax Filippov }; 2138bb3b575SMax Filippov 214188ce01dSMax Filippov static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 215b707ab75SMax Filippov { 216b707ab75SMax Filippov #ifdef TARGET_WORDS_BIGENDIAN 217b707ab75SMax Filippov int be = 1; 218b707ab75SMax Filippov #else 219b707ab75SMax Filippov int be = 0; 220b707ab75SMax Filippov #endif 221b707ab75SMax Filippov MemoryRegion *system_memory = get_system_memory(); 222b707ab75SMax Filippov XtensaCPU *cpu = NULL; 223b707ab75SMax Filippov CPUXtensaState *env = NULL; 224e53fa62cSMax Filippov MemoryRegion *system_io; 225b707ab75SMax Filippov DriveInfo *dinfo; 226b707ab75SMax Filippov pflash_t *flash = NULL; 22737b259d0SMax Filippov QemuOpts *machine_opts = qemu_get_machine_opts(); 22837b259d0SMax Filippov const char *kernel_filename = qemu_opt_get(machine_opts, "kernel"); 22937b259d0SMax Filippov const char *kernel_cmdline = qemu_opt_get(machine_opts, "append"); 230996dfe98SMax Filippov const char *dtb_filename = qemu_opt_get(machine_opts, "dtb"); 231f55b32e7SMax Filippov const char *initrd_filename = qemu_opt_get(machine_opts, "initrd"); 232b707ab75SMax Filippov int n; 233b707ab75SMax Filippov 234b707ab75SMax Filippov for (n = 0; n < smp_cpus; n++) { 235f83eb10dSIgor Mammedov cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 236b707ab75SMax Filippov env = &cpu->env; 237b707ab75SMax Filippov 238b707ab75SMax Filippov env->sregs[PRID] = n; 239188ce01dSMax Filippov qemu_register_reset(xtfpga_reset, cpu); 240b707ab75SMax Filippov /* Need MMU initialized prior to ELF loading, 241b707ab75SMax Filippov * so that ELF gets loaded into virtual addresses 242b707ab75SMax Filippov */ 243b707ab75SMax Filippov cpu_reset(CPU(cpu)); 244b707ab75SMax Filippov } 245b707ab75SMax Filippov 246e53fa62cSMax Filippov if (env) { 247e53fa62cSMax Filippov XtensaMemory sysram = env->config->sysram; 248e53fa62cSMax Filippov 249e53fa62cSMax Filippov sysram.location[0].size = machine->ram_size; 250e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 251e53fa62cSMax Filippov system_memory); 252e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 253e53fa62cSMax Filippov system_memory); 254e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 255e53fa62cSMax Filippov system_memory); 256e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 257e53fa62cSMax Filippov system_memory); 258e53fa62cSMax Filippov xtensa_create_memory_regions(&sysram, "xtensa.sysram", 259e53fa62cSMax Filippov system_memory); 260e53fa62cSMax Filippov } 261b707ab75SMax Filippov 262b707ab75SMax Filippov system_io = g_malloc(sizeof(*system_io)); 263188ce01dSMax Filippov memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 2648bb3b575SMax Filippov 224 * 1024 * 1024); 265b707ab75SMax Filippov memory_region_add_subregion(system_memory, 0xf0000000, system_io); 266188ce01dSMax Filippov xtfpga_fpga_init(system_io, 0x0d020000); 267b707ab75SMax Filippov if (nd_table[0].used) { 268188ce01dSMax Filippov xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 269b707ab75SMax Filippov xtensa_get_extint(env, 1), nd_table); 270b707ab75SMax Filippov } 271b707ab75SMax Filippov 272b707ab75SMax Filippov if (!serial_hds[0]) { 273b4948be9SMarc-André Lureau serial_hds[0] = qemu_chr_new("serial0", "null"); 274b707ab75SMax Filippov } 275b707ab75SMax Filippov 276b707ab75SMax Filippov serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0), 277b707ab75SMax Filippov 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN); 278b707ab75SMax Filippov 279b707ab75SMax Filippov dinfo = drive_get(IF_PFLASH, 0, 0); 280b707ab75SMax Filippov if (dinfo) { 28168931a40SMax Filippov flash = xtfpga_flash_init(system_io, board, dinfo, be); 282b707ab75SMax Filippov } 283b707ab75SMax Filippov 284b707ab75SMax Filippov /* Use presence of kernel file name as 'boot from SRAM' switch. */ 285b707ab75SMax Filippov if (kernel_filename) { 286364d4802SMax Filippov uint32_t entry_point = env->pc; 287b6edea8bSMax Filippov size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 288e53fa62cSMax Filippov uint32_t tagptr = env->config->sysrom.location[0].addr + 289e53fa62cSMax Filippov board->sram_size; 290a9a28591SMax Filippov uint32_t cur_tagptr; 291b6edea8bSMax Filippov BpMemInfo memory_location = { 292b6edea8bSMax Filippov .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 293e53fa62cSMax Filippov .start = tswap32(env->config->sysram.location[0].addr), 294e53fa62cSMax Filippov .end = tswap32(env->config->sysram.location[0].addr + 295e53fa62cSMax Filippov machine->ram_size), 296b6edea8bSMax Filippov }; 297996dfe98SMax Filippov uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 298996dfe98SMax Filippov machine->ram_size : 0x08000000; 299996dfe98SMax Filippov uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 300a9a28591SMax Filippov 301e53fa62cSMax Filippov lowmem_end += env->config->sysram.location[0].addr; 302e53fa62cSMax Filippov cur_lowmem += env->config->sysram.location[0].addr; 303e53fa62cSMax Filippov 304e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 305e53fa62cSMax Filippov system_memory); 306b707ab75SMax Filippov 307b707ab75SMax Filippov if (kernel_cmdline) { 308a9a28591SMax Filippov bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 309a9a28591SMax Filippov } 310996dfe98SMax Filippov if (dtb_filename) { 311996dfe98SMax Filippov bp_size += get_tag_size(sizeof(uint32_t)); 312996dfe98SMax Filippov } 313f55b32e7SMax Filippov if (initrd_filename) { 314f55b32e7SMax Filippov bp_size += get_tag_size(sizeof(BpMemInfo)); 315f55b32e7SMax Filippov } 316b707ab75SMax Filippov 317a9a28591SMax Filippov /* Put kernel bootparameters to the end of that SRAM */ 318a9a28591SMax Filippov tagptr = (tagptr - bp_size) & ~0xff; 319a9a28591SMax Filippov cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 320b6edea8bSMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 321b6edea8bSMax Filippov sizeof(memory_location), &memory_location); 322a9a28591SMax Filippov 323a9a28591SMax Filippov if (kernel_cmdline) { 324a9a28591SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 325a9a28591SMax Filippov strlen(kernel_cmdline) + 1, kernel_cmdline); 326a9a28591SMax Filippov } 3270e80359eSMax Filippov #ifdef CONFIG_FDT 328996dfe98SMax Filippov if (dtb_filename) { 329996dfe98SMax Filippov int fdt_size; 330996dfe98SMax Filippov void *fdt = load_device_tree(dtb_filename, &fdt_size); 331996dfe98SMax Filippov uint32_t dtb_addr = tswap32(cur_lowmem); 332996dfe98SMax Filippov 333996dfe98SMax Filippov if (!fdt) { 334ebbb419aSGonglei error_report("could not load DTB '%s'", dtb_filename); 335996dfe98SMax Filippov exit(EXIT_FAILURE); 336996dfe98SMax Filippov } 337996dfe98SMax Filippov 338996dfe98SMax Filippov cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 339996dfe98SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 340996dfe98SMax Filippov sizeof(dtb_addr), &dtb_addr); 341996dfe98SMax Filippov cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096); 342996dfe98SMax Filippov } 3430e80359eSMax Filippov #else 3440e80359eSMax Filippov if (dtb_filename) { 3450e80359eSMax Filippov error_report("could not load DTB '%s': " 3460e80359eSMax Filippov "FDT support is not configured in QEMU", 3470e80359eSMax Filippov dtb_filename); 3480e80359eSMax Filippov exit(EXIT_FAILURE); 3490e80359eSMax Filippov } 3500e80359eSMax Filippov #endif 351f55b32e7SMax Filippov if (initrd_filename) { 352f55b32e7SMax Filippov BpMemInfo initrd_location = { 0 }; 353f55b32e7SMax Filippov int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 354f55b32e7SMax Filippov lowmem_end - cur_lowmem); 355f55b32e7SMax Filippov 356f55b32e7SMax Filippov if (initrd_size < 0) { 357f55b32e7SMax Filippov initrd_size = load_image_targphys(initrd_filename, 358f55b32e7SMax Filippov cur_lowmem, 359f55b32e7SMax Filippov lowmem_end - cur_lowmem); 360f55b32e7SMax Filippov } 361f55b32e7SMax Filippov if (initrd_size < 0) { 362ebbb419aSGonglei error_report("could not load initrd '%s'", initrd_filename); 363f55b32e7SMax Filippov exit(EXIT_FAILURE); 364f55b32e7SMax Filippov } 365f55b32e7SMax Filippov initrd_location.start = tswap32(cur_lowmem); 366f55b32e7SMax Filippov initrd_location.end = tswap32(cur_lowmem + initrd_size); 367f55b32e7SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 368f55b32e7SMax Filippov sizeof(initrd_location), &initrd_location); 369f55b32e7SMax Filippov cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096); 370f55b32e7SMax Filippov } 371a9a28591SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 372b707ab75SMax Filippov env->regs[2] = tagptr; 373b707ab75SMax Filippov 374b707ab75SMax Filippov uint64_t elf_entry; 375b707ab75SMax Filippov uint64_t elf_lowaddr; 376b707ab75SMax Filippov int success = load_elf(kernel_filename, translate_phys_addr, cpu, 3777ef295eaSPeter Crosthwaite &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0); 378b707ab75SMax Filippov if (success > 0) { 379364d4802SMax Filippov entry_point = elf_entry; 380364d4802SMax Filippov } else { 381364d4802SMax Filippov hwaddr ep; 382364d4802SMax Filippov int is_linux; 38325bda50aSMax Filippov success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 3846d2e4530SMax Filippov translate_phys_addr, cpu); 385364d4802SMax Filippov if (success > 0 && is_linux) { 386364d4802SMax Filippov entry_point = ep; 387364d4802SMax Filippov } else { 388ebbb419aSGonglei error_report("could not load kernel '%s'", 389364d4802SMax Filippov kernel_filename); 390364d4802SMax Filippov exit(EXIT_FAILURE); 391364d4802SMax Filippov } 392364d4802SMax Filippov } 393364d4802SMax Filippov if (entry_point != env->pc) { 394339ef8fbSMax Filippov uint8_t boot[] = { 395364d4802SMax Filippov #ifdef TARGET_WORDS_BIGENDIAN 396339ef8fbSMax Filippov 0x60, 0x00, 0x08, /* j 1f */ 397339ef8fbSMax Filippov 0x00, /* .literal_position */ 398339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 399339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 400339ef8fbSMax Filippov /* 1: */ 401339ef8fbSMax Filippov 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 402339ef8fbSMax Filippov 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 403339ef8fbSMax Filippov 0x0a, 0x00, 0x00, /* jx a0 */ 404364d4802SMax Filippov #else 405339ef8fbSMax Filippov 0x06, 0x02, 0x00, /* j 1f */ 406339ef8fbSMax Filippov 0x00, /* .literal_position */ 407339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 408339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 409339ef8fbSMax Filippov /* 1: */ 410339ef8fbSMax Filippov 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 411339ef8fbSMax Filippov 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 412339ef8fbSMax Filippov 0xa0, 0x00, 0x00, /* jx a0 */ 413364d4802SMax Filippov #endif 414364d4802SMax Filippov }; 415339ef8fbSMax Filippov uint32_t entry_pc = tswap32(entry_point); 416339ef8fbSMax Filippov uint32_t entry_a2 = tswap32(tagptr); 417339ef8fbSMax Filippov 418339ef8fbSMax Filippov memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 419339ef8fbSMax Filippov memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 420339ef8fbSMax Filippov cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 421b707ab75SMax Filippov } 422b707ab75SMax Filippov } else { 423b707ab75SMax Filippov if (flash) { 424b707ab75SMax Filippov MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 425b707ab75SMax Filippov MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 426e53fa62cSMax Filippov uint32_t size = env->config->sysrom.location[0].size; 427e53fa62cSMax Filippov 428*740ad9f7SMax Filippov if (board->flash->size - board->flash->boot_base < size) { 429*740ad9f7SMax Filippov size = board->flash->size - board->flash->boot_base; 430e53fa62cSMax Filippov } 431b707ab75SMax Filippov 432188ce01dSMax Filippov memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 433*740ad9f7SMax Filippov flash_mr, board->flash->boot_base, size); 434e53fa62cSMax Filippov memory_region_add_subregion(system_memory, 435e53fa62cSMax Filippov env->config->sysrom.location[0].addr, 436b707ab75SMax Filippov flash_io); 437e53fa62cSMax Filippov } else { 438e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 439e53fa62cSMax Filippov system_memory); 440b707ab75SMax Filippov } 441b707ab75SMax Filippov } 442b707ab75SMax Filippov } 443b707ab75SMax Filippov 444*740ad9f7SMax Filippov static const XtfpgaFlashDesc lx60_flash = { 445*740ad9f7SMax Filippov .base = 0x08000000, 446*740ad9f7SMax Filippov .size = 0x00400000, 447*740ad9f7SMax Filippov .sector_size = 0x10000, 448*740ad9f7SMax Filippov }; 449*740ad9f7SMax Filippov 450188ce01dSMax Filippov static void xtfpga_lx60_init(MachineState *machine) 451b707ab75SMax Filippov { 452188ce01dSMax Filippov static const XtfpgaBoardDesc lx60_board = { 453*740ad9f7SMax Filippov .flash = &lx60_flash, 454b707ab75SMax Filippov .sram_size = 0x20000, 455b707ab75SMax Filippov }; 456188ce01dSMax Filippov xtfpga_init(&lx60_board, machine); 457b707ab75SMax Filippov } 458b707ab75SMax Filippov 459*740ad9f7SMax Filippov static const XtfpgaFlashDesc lx200_flash = { 460*740ad9f7SMax Filippov .base = 0x08000000, 461*740ad9f7SMax Filippov .size = 0x01000000, 462*740ad9f7SMax Filippov .sector_size = 0x20000, 463*740ad9f7SMax Filippov }; 464*740ad9f7SMax Filippov 465188ce01dSMax Filippov static void xtfpga_lx200_init(MachineState *machine) 466b707ab75SMax Filippov { 467188ce01dSMax Filippov static const XtfpgaBoardDesc lx200_board = { 468*740ad9f7SMax Filippov .flash = &lx200_flash, 469b707ab75SMax Filippov .sram_size = 0x2000000, 470b707ab75SMax Filippov }; 471188ce01dSMax Filippov xtfpga_init(&lx200_board, machine); 472b707ab75SMax Filippov } 473b707ab75SMax Filippov 474*740ad9f7SMax Filippov static const XtfpgaFlashDesc ml605_flash = { 475*740ad9f7SMax Filippov .base = 0x08000000, 476*740ad9f7SMax Filippov .size = 0x01000000, 477*740ad9f7SMax Filippov .sector_size = 0x20000, 478*740ad9f7SMax Filippov }; 479*740ad9f7SMax Filippov 480188ce01dSMax Filippov static void xtfpga_ml605_init(MachineState *machine) 481b707ab75SMax Filippov { 482188ce01dSMax Filippov static const XtfpgaBoardDesc ml605_board = { 483*740ad9f7SMax Filippov .flash = &ml605_flash, 484b707ab75SMax Filippov .sram_size = 0x2000000, 485b707ab75SMax Filippov }; 486188ce01dSMax Filippov xtfpga_init(&ml605_board, machine); 487b707ab75SMax Filippov } 488b707ab75SMax Filippov 489*740ad9f7SMax Filippov static const XtfpgaFlashDesc kc705_flash = { 490*740ad9f7SMax Filippov .base = 0x00000000, 491*740ad9f7SMax Filippov .size = 0x08000000, 492*740ad9f7SMax Filippov .boot_base = 0x06000000, 493*740ad9f7SMax Filippov .sector_size = 0x20000, 494*740ad9f7SMax Filippov }; 495*740ad9f7SMax Filippov 496188ce01dSMax Filippov static void xtfpga_kc705_init(MachineState *machine) 497b707ab75SMax Filippov { 498188ce01dSMax Filippov static const XtfpgaBoardDesc kc705_board = { 499*740ad9f7SMax Filippov .flash = &kc705_flash, 500b707ab75SMax Filippov .sram_size = 0x2000000, 501b707ab75SMax Filippov }; 502188ce01dSMax Filippov xtfpga_init(&kc705_board, machine); 503b707ab75SMax Filippov } 504b707ab75SMax Filippov 505188ce01dSMax Filippov static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 506b707ab75SMax Filippov { 5078a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 5088a661aeaSAndreas Färber 509e264d29dSEduardo Habkost mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 510188ce01dSMax Filippov mc->init = xtfpga_lx60_init; 511e264d29dSEduardo Habkost mc->max_cpus = 4; 512f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 513b707ab75SMax Filippov } 514b707ab75SMax Filippov 515188ce01dSMax Filippov static const TypeInfo xtfpga_lx60_type = { 5168a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lx60"), 5178a661aeaSAndreas Färber .parent = TYPE_MACHINE, 518188ce01dSMax Filippov .class_init = xtfpga_lx60_class_init, 5198a661aeaSAndreas Färber }; 520e264d29dSEduardo Habkost 521188ce01dSMax Filippov static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 522e264d29dSEduardo Habkost { 5238a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 5248a661aeaSAndreas Färber 525e264d29dSEduardo Habkost mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 526188ce01dSMax Filippov mc->init = xtfpga_lx200_init; 527e264d29dSEduardo Habkost mc->max_cpus = 4; 528f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 529e264d29dSEduardo Habkost } 530e264d29dSEduardo Habkost 531188ce01dSMax Filippov static const TypeInfo xtfpga_lx200_type = { 5328a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lx200"), 5338a661aeaSAndreas Färber .parent = TYPE_MACHINE, 534188ce01dSMax Filippov .class_init = xtfpga_lx200_class_init, 5358a661aeaSAndreas Färber }; 536e264d29dSEduardo Habkost 537188ce01dSMax Filippov static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 538e264d29dSEduardo Habkost { 5398a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 5408a661aeaSAndreas Färber 541e264d29dSEduardo Habkost mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 542188ce01dSMax Filippov mc->init = xtfpga_ml605_init; 543e264d29dSEduardo Habkost mc->max_cpus = 4; 544f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 545e264d29dSEduardo Habkost } 546e264d29dSEduardo Habkost 547188ce01dSMax Filippov static const TypeInfo xtfpga_ml605_type = { 5488a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("ml605"), 5498a661aeaSAndreas Färber .parent = TYPE_MACHINE, 550188ce01dSMax Filippov .class_init = xtfpga_ml605_class_init, 5518a661aeaSAndreas Färber }; 552e264d29dSEduardo Habkost 553188ce01dSMax Filippov static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 554e264d29dSEduardo Habkost { 5558a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 5568a661aeaSAndreas Färber 557e264d29dSEduardo Habkost mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 558188ce01dSMax Filippov mc->init = xtfpga_kc705_init; 559e264d29dSEduardo Habkost mc->max_cpus = 4; 560f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 561e264d29dSEduardo Habkost } 562e264d29dSEduardo Habkost 563188ce01dSMax Filippov static const TypeInfo xtfpga_kc705_type = { 5648a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("kc705"), 5658a661aeaSAndreas Färber .parent = TYPE_MACHINE, 566188ce01dSMax Filippov .class_init = xtfpga_kc705_class_init, 5678a661aeaSAndreas Färber }; 5688a661aeaSAndreas Färber 569188ce01dSMax Filippov static void xtfpga_machines_init(void) 5708a661aeaSAndreas Färber { 571188ce01dSMax Filippov type_register_static(&xtfpga_lx60_type); 572188ce01dSMax Filippov type_register_static(&xtfpga_lx200_type); 573188ce01dSMax Filippov type_register_static(&xtfpga_ml605_type); 574188ce01dSMax Filippov type_register_static(&xtfpga_kc705_type); 5758a661aeaSAndreas Färber } 5768a661aeaSAndreas Färber 577188ce01dSMax Filippov type_init(xtfpga_machines_init) 578