1b707ab75SMax Filippov /* 2b707ab75SMax Filippov * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3b707ab75SMax Filippov * All rights reserved. 4b707ab75SMax Filippov * 5b707ab75SMax Filippov * Redistribution and use in source and binary forms, with or without 6b707ab75SMax Filippov * modification, are permitted provided that the following conditions are met: 7b707ab75SMax Filippov * * Redistributions of source code must retain the above copyright 8b707ab75SMax Filippov * notice, this list of conditions and the following disclaimer. 9b707ab75SMax Filippov * * Redistributions in binary form must reproduce the above copyright 10b707ab75SMax Filippov * notice, this list of conditions and the following disclaimer in the 11b707ab75SMax Filippov * documentation and/or other materials provided with the distribution. 12b707ab75SMax Filippov * * Neither the name of the Open Source and Linux Lab nor the 13b707ab75SMax Filippov * names of its contributors may be used to endorse or promote products 14b707ab75SMax Filippov * derived from this software without specific prior written permission. 15b707ab75SMax Filippov * 16b707ab75SMax Filippov * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17b707ab75SMax Filippov * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18b707ab75SMax Filippov * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19b707ab75SMax Filippov * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20b707ab75SMax Filippov * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21b707ab75SMax Filippov * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22b707ab75SMax Filippov * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23b707ab75SMax Filippov * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24b707ab75SMax Filippov * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25b707ab75SMax Filippov * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b707ab75SMax Filippov */ 27b707ab75SMax Filippov 2809aae23dSPeter Maydell #include "qemu/osdep.h" 29b941329dSPhilippe Mathieu-Daudé #include "qemu/units.h" 30da34e65cSMarkus Armbruster #include "qapi/error.h" 314771d756SPaolo Bonzini #include "cpu.h" 32b707ab75SMax Filippov #include "sysemu/sysemu.h" 33b707ab75SMax Filippov #include "hw/boards.h" 34b707ab75SMax Filippov #include "hw/loader.h" 35a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 36b707ab75SMax Filippov #include "elf.h" 37b707ab75SMax Filippov #include "exec/memory.h" 38b707ab75SMax Filippov #include "hw/char/serial.h" 39b707ab75SMax Filippov #include "net/net.h" 40b707ab75SMax Filippov #include "hw/sysbus.h" 41b707ab75SMax Filippov #include "hw/block/flash.h" 428228e353SMarc-André Lureau #include "chardev/char.h" 43996dfe98SMax Filippov #include "sysemu/device_tree.h" 4471e8a915SMarkus Armbruster #include "sysemu/reset.h" 4554d31236SMarkus Armbruster #include "sysemu/runstate.h" 468488ab02SMax Filippov #include "qemu/error-report.h" 47922a01a0SMarkus Armbruster #include "qemu/option.h" 48b707ab75SMax Filippov #include "bootparam.h" 49e53fa62cSMax Filippov #include "xtensa_memory.h" 501acd90bfSMax Filippov #include "hw/xtensa/mx_pic.h" 51d6454270SMarkus Armbruster #include "migration/vmstate.h" 52b707ab75SMax Filippov 53740ad9f7SMax Filippov typedef struct XtfpgaFlashDesc { 54740ad9f7SMax Filippov hwaddr base; 55740ad9f7SMax Filippov size_t size; 56740ad9f7SMax Filippov size_t boot_base; 57740ad9f7SMax Filippov size_t sector_size; 58740ad9f7SMax Filippov } XtfpgaFlashDesc; 59740ad9f7SMax Filippov 60188ce01dSMax Filippov typedef struct XtfpgaBoardDesc { 61740ad9f7SMax Filippov const XtfpgaFlashDesc *flash; 62b707ab75SMax Filippov size_t sram_size; 6385e2d8d5SMax Filippov const hwaddr *io; 64188ce01dSMax Filippov } XtfpgaBoardDesc; 65b707ab75SMax Filippov 66188ce01dSMax Filippov typedef struct XtfpgaFpgaState { 67b707ab75SMax Filippov MemoryRegion iomem; 68fff7bf14SMax Filippov uint32_t freq; 69b707ab75SMax Filippov uint32_t leds; 70b707ab75SMax Filippov uint32_t switches; 71188ce01dSMax Filippov } XtfpgaFpgaState; 72b707ab75SMax Filippov 73188ce01dSMax Filippov static void xtfpga_fpga_reset(void *opaque) 74b707ab75SMax Filippov { 75188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 76b707ab75SMax Filippov 77b707ab75SMax Filippov s->leds = 0; 78b707ab75SMax Filippov s->switches = 0; 79b707ab75SMax Filippov } 80b707ab75SMax Filippov 81188ce01dSMax Filippov static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 82b707ab75SMax Filippov unsigned size) 83b707ab75SMax Filippov { 84188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 85b707ab75SMax Filippov 86b707ab75SMax Filippov switch (addr) { 87b707ab75SMax Filippov case 0x0: /*build date code*/ 88b707ab75SMax Filippov return 0x09272011; 89b707ab75SMax Filippov 90b707ab75SMax Filippov case 0x4: /*processor clock frequency, Hz*/ 91fff7bf14SMax Filippov return s->freq; 92b707ab75SMax Filippov 93b707ab75SMax Filippov case 0x8: /*LEDs (off = 0, on = 1)*/ 94b707ab75SMax Filippov return s->leds; 95b707ab75SMax Filippov 96b707ab75SMax Filippov case 0xc: /*DIP switches (off = 0, on = 1)*/ 97b707ab75SMax Filippov return s->switches; 98b707ab75SMax Filippov } 99b707ab75SMax Filippov return 0; 100b707ab75SMax Filippov } 101b707ab75SMax Filippov 102188ce01dSMax Filippov static void xtfpga_fpga_write(void *opaque, hwaddr addr, 103b707ab75SMax Filippov uint64_t val, unsigned size) 104b707ab75SMax Filippov { 105188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 106b707ab75SMax Filippov 107b707ab75SMax Filippov switch (addr) { 108b707ab75SMax Filippov case 0x8: /*LEDs (off = 0, on = 1)*/ 109b707ab75SMax Filippov s->leds = val; 110b707ab75SMax Filippov break; 111b707ab75SMax Filippov 112b707ab75SMax Filippov case 0x10: /*board reset*/ 113b707ab75SMax Filippov if (val == 0xdead) { 114cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 115b707ab75SMax Filippov } 116b707ab75SMax Filippov break; 117b707ab75SMax Filippov } 118b707ab75SMax Filippov } 119b707ab75SMax Filippov 120188ce01dSMax Filippov static const MemoryRegionOps xtfpga_fpga_ops = { 121188ce01dSMax Filippov .read = xtfpga_fpga_read, 122188ce01dSMax Filippov .write = xtfpga_fpga_write, 123b707ab75SMax Filippov .endianness = DEVICE_NATIVE_ENDIAN, 124b707ab75SMax Filippov }; 125b707ab75SMax Filippov 126188ce01dSMax Filippov static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 127fff7bf14SMax Filippov hwaddr base, uint32_t freq) 128b707ab75SMax Filippov { 129*b21e2380SMarkus Armbruster XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1); 130b707ab75SMax Filippov 131188ce01dSMax Filippov memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 132188ce01dSMax Filippov "xtfpga.fpga", 0x10000); 133b707ab75SMax Filippov memory_region_add_subregion(address_space, base, &s->iomem); 134fff7bf14SMax Filippov s->freq = freq; 135188ce01dSMax Filippov xtfpga_fpga_reset(s); 136188ce01dSMax Filippov qemu_register_reset(xtfpga_fpga_reset, s); 137b707ab75SMax Filippov return s; 138b707ab75SMax Filippov } 139b707ab75SMax Filippov 140188ce01dSMax Filippov static void xtfpga_net_init(MemoryRegion *address_space, 141b707ab75SMax Filippov hwaddr base, 142b707ab75SMax Filippov hwaddr descriptors, 143b707ab75SMax Filippov hwaddr buffers, 144b707ab75SMax Filippov qemu_irq irq, NICInfo *nd) 145b707ab75SMax Filippov { 146b707ab75SMax Filippov DeviceState *dev; 147b707ab75SMax Filippov SysBusDevice *s; 148b707ab75SMax Filippov MemoryRegion *ram; 149b707ab75SMax Filippov 1503e80f690SMarkus Armbruster dev = qdev_new("open_eth"); 151b707ab75SMax Filippov qdev_set_nic_properties(dev, nd); 152b707ab75SMax Filippov 153b707ab75SMax Filippov s = SYS_BUS_DEVICE(dev); 1543c6ef471SMarkus Armbruster sysbus_realize_and_unref(s, &error_fatal); 155b707ab75SMax Filippov sysbus_connect_irq(s, 0, irq); 156b707ab75SMax Filippov memory_region_add_subregion(address_space, base, 157b707ab75SMax Filippov sysbus_mmio_get_region(s, 0)); 158b707ab75SMax Filippov memory_region_add_subregion(address_space, descriptors, 159b707ab75SMax Filippov sysbus_mmio_get_region(s, 1)); 160b707ab75SMax Filippov 161b707ab75SMax Filippov ram = g_malloc(sizeof(*ram)); 162b941329dSPhilippe Mathieu-Daudé memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, 163f8ed85acSMarkus Armbruster &error_fatal); 164b707ab75SMax Filippov vmstate_register_ram_global(ram); 165b707ab75SMax Filippov memory_region_add_subregion(address_space, buffers, ram); 166b707ab75SMax Filippov } 167b707ab75SMax Filippov 16816434065SMarkus Armbruster static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, 169188ce01dSMax Filippov const XtfpgaBoardDesc *board, 17068931a40SMax Filippov DriveInfo *dinfo, int be) 17168931a40SMax Filippov { 17268931a40SMax Filippov SysBusDevice *s; 1733e80f690SMarkus Armbruster DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 17468931a40SMax Filippov 175934df912SMarkus Armbruster qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 17668931a40SMax Filippov qdev_prop_set_uint32(dev, "num-blocks", 177740ad9f7SMax Filippov board->flash->size / board->flash->sector_size); 178740ad9f7SMax Filippov qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 179f9a555e4SMax Filippov qdev_prop_set_uint8(dev, "width", 2); 18068931a40SMax Filippov qdev_prop_set_bit(dev, "big-endian", be); 181188ce01dSMax Filippov qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 18268931a40SMax Filippov s = SYS_BUS_DEVICE(dev); 1833c6ef471SMarkus Armbruster sysbus_realize_and_unref(s, &error_fatal); 184740ad9f7SMax Filippov memory_region_add_subregion(address_space, board->flash->base, 18568931a40SMax Filippov sysbus_mmio_get_region(s, 0)); 18681c7db72SMarkus Armbruster return PFLASH_CFI01(dev); 18768931a40SMax Filippov } 18868931a40SMax Filippov 189b707ab75SMax Filippov static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 190b707ab75SMax Filippov { 191b707ab75SMax Filippov XtensaCPU *cpu = opaque; 192b707ab75SMax Filippov 193b707ab75SMax Filippov return cpu_get_phys_page_debug(CPU(cpu), addr); 194b707ab75SMax Filippov } 195b707ab75SMax Filippov 196188ce01dSMax Filippov static void xtfpga_reset(void *opaque) 197b707ab75SMax Filippov { 198b707ab75SMax Filippov XtensaCPU *cpu = opaque; 199b707ab75SMax Filippov 200b707ab75SMax Filippov cpu_reset(CPU(cpu)); 201b707ab75SMax Filippov } 202b707ab75SMax Filippov 203188ce01dSMax Filippov static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 2048bb3b575SMax Filippov unsigned size) 2058bb3b575SMax Filippov { 2068bb3b575SMax Filippov return 0; 2078bb3b575SMax Filippov } 2088bb3b575SMax Filippov 209188ce01dSMax Filippov static void xtfpga_io_write(void *opaque, hwaddr addr, 2108bb3b575SMax Filippov uint64_t val, unsigned size) 2118bb3b575SMax Filippov { 2128bb3b575SMax Filippov } 2138bb3b575SMax Filippov 214188ce01dSMax Filippov static const MemoryRegionOps xtfpga_io_ops = { 215188ce01dSMax Filippov .read = xtfpga_io_read, 216188ce01dSMax Filippov .write = xtfpga_io_write, 2178bb3b575SMax Filippov .endianness = DEVICE_NATIVE_ENDIAN, 2188bb3b575SMax Filippov }; 2198bb3b575SMax Filippov 220188ce01dSMax Filippov static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 221b707ab75SMax Filippov { 222b707ab75SMax Filippov #ifdef TARGET_WORDS_BIGENDIAN 223b707ab75SMax Filippov int be = 1; 224b707ab75SMax Filippov #else 225b707ab75SMax Filippov int be = 0; 226b707ab75SMax Filippov #endif 227b707ab75SMax Filippov MemoryRegion *system_memory = get_system_memory(); 228b707ab75SMax Filippov XtensaCPU *cpu = NULL; 229b707ab75SMax Filippov CPUXtensaState *env = NULL; 230e53fa62cSMax Filippov MemoryRegion *system_io; 2311acd90bfSMax Filippov XtensaMxPic *mx_pic = NULL; 23266f03d7eSMax Filippov qemu_irq *extints; 233b707ab75SMax Filippov DriveInfo *dinfo; 23416434065SMarkus Armbruster PFlashCFI01 *flash = NULL; 235f2ce39b4SPaolo Bonzini const char *kernel_filename = machine->kernel_filename; 236f2ce39b4SPaolo Bonzini const char *kernel_cmdline = machine->kernel_cmdline; 237f2ce39b4SPaolo Bonzini const char *dtb_filename = machine->dtb; 238f2ce39b4SPaolo Bonzini const char *initrd_filename = machine->initrd_filename; 239b941329dSPhilippe Mathieu-Daudé const unsigned system_io_size = 224 * MiB; 240fff7bf14SMax Filippov uint32_t freq = 10000000; 241b707ab75SMax Filippov int n; 24233decbd2SLike Xu unsigned int smp_cpus = machine->smp.cpus; 243b707ab75SMax Filippov 2441acd90bfSMax Filippov if (smp_cpus > 1) { 2451acd90bfSMax Filippov mx_pic = xtensa_mx_pic_init(31); 2461acd90bfSMax Filippov qemu_register_reset(xtensa_mx_pic_reset, mx_pic); 2471acd90bfSMax Filippov } 248b707ab75SMax Filippov for (n = 0; n < smp_cpus; n++) { 249288a3f2eSMax Filippov CPUXtensaState *cenv = NULL; 250b707ab75SMax Filippov 251288a3f2eSMax Filippov cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 252288a3f2eSMax Filippov cenv = &cpu->env; 253288a3f2eSMax Filippov if (!env) { 254288a3f2eSMax Filippov env = cenv; 255fff7bf14SMax Filippov freq = env->config->clock_freq_khz * 1000; 256288a3f2eSMax Filippov } 257288a3f2eSMax Filippov 2581acd90bfSMax Filippov if (mx_pic) { 2591acd90bfSMax Filippov MemoryRegion *mx_eri; 2601acd90bfSMax Filippov 2611acd90bfSMax Filippov mx_eri = xtensa_mx_pic_register_cpu(mx_pic, 2621acd90bfSMax Filippov xtensa_get_extints(cenv), 2631acd90bfSMax Filippov xtensa_get_runstall(cenv)); 2641acd90bfSMax Filippov memory_region_add_subregion(xtensa_get_er_region(cenv), 2651acd90bfSMax Filippov 0, mx_eri); 2661acd90bfSMax Filippov } 267288a3f2eSMax Filippov cenv->sregs[PRID] = n; 2681acd90bfSMax Filippov xtensa_select_static_vectors(cenv, n != 0); 269188ce01dSMax Filippov qemu_register_reset(xtfpga_reset, cpu); 270b707ab75SMax Filippov /* Need MMU initialized prior to ELF loading, 271b707ab75SMax Filippov * so that ELF gets loaded into virtual addresses 272b707ab75SMax Filippov */ 273b707ab75SMax Filippov cpu_reset(CPU(cpu)); 274b707ab75SMax Filippov } 2751acd90bfSMax Filippov if (smp_cpus > 1) { 2761acd90bfSMax Filippov extints = xtensa_mx_pic_get_extints(mx_pic); 2771acd90bfSMax Filippov } else { 27866f03d7eSMax Filippov extints = xtensa_get_extints(env); 2791acd90bfSMax Filippov } 280b707ab75SMax Filippov 281e53fa62cSMax Filippov if (env) { 282e53fa62cSMax Filippov XtensaMemory sysram = env->config->sysram; 283e53fa62cSMax Filippov 284e53fa62cSMax Filippov sysram.location[0].size = machine->ram_size; 285e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 286e53fa62cSMax Filippov system_memory); 287e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 288e53fa62cSMax Filippov system_memory); 289e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 290e53fa62cSMax Filippov system_memory); 291e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 292e53fa62cSMax Filippov system_memory); 293e53fa62cSMax Filippov xtensa_create_memory_regions(&sysram, "xtensa.sysram", 294e53fa62cSMax Filippov system_memory); 295e53fa62cSMax Filippov } 296b707ab75SMax Filippov 297b707ab75SMax Filippov system_io = g_malloc(sizeof(*system_io)); 298188ce01dSMax Filippov memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 29985e2d8d5SMax Filippov system_io_size); 30085e2d8d5SMax Filippov memory_region_add_subregion(system_memory, board->io[0], system_io); 30185e2d8d5SMax Filippov if (board->io[1]) { 30285e2d8d5SMax Filippov MemoryRegion *io = g_malloc(sizeof(*io)); 30385e2d8d5SMax Filippov 30485e2d8d5SMax Filippov memory_region_init_alias(io, NULL, "xtfpga.io.cached", 30585e2d8d5SMax Filippov system_io, 0, system_io_size); 30685e2d8d5SMax Filippov memory_region_add_subregion(system_memory, board->io[1], io); 30785e2d8d5SMax Filippov } 308fff7bf14SMax Filippov xtfpga_fpga_init(system_io, 0x0d020000, freq); 309b707ab75SMax Filippov if (nd_table[0].used) { 310188ce01dSMax Filippov xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 31166f03d7eSMax Filippov extints[1], nd_table); 312b707ab75SMax Filippov } 313b707ab75SMax Filippov 31466f03d7eSMax Filippov serial_mm_init(system_io, 0x0d050020, 2, extints[0], 3159bca0edbSPeter Maydell 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 316b707ab75SMax Filippov 317b707ab75SMax Filippov dinfo = drive_get(IF_PFLASH, 0, 0); 318b707ab75SMax Filippov if (dinfo) { 31968931a40SMax Filippov flash = xtfpga_flash_init(system_io, board, dinfo, be); 320b707ab75SMax Filippov } 321b707ab75SMax Filippov 322b707ab75SMax Filippov /* Use presence of kernel file name as 'boot from SRAM' switch. */ 323b707ab75SMax Filippov if (kernel_filename) { 324364d4802SMax Filippov uint32_t entry_point = env->pc; 325b6edea8bSMax Filippov size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 326e53fa62cSMax Filippov uint32_t tagptr = env->config->sysrom.location[0].addr + 327e53fa62cSMax Filippov board->sram_size; 328a9a28591SMax Filippov uint32_t cur_tagptr; 329b6edea8bSMax Filippov BpMemInfo memory_location = { 330b6edea8bSMax Filippov .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 331e53fa62cSMax Filippov .start = tswap32(env->config->sysram.location[0].addr), 332e53fa62cSMax Filippov .end = tswap32(env->config->sysram.location[0].addr + 333e53fa62cSMax Filippov machine->ram_size), 334b6edea8bSMax Filippov }; 335996dfe98SMax Filippov uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 336996dfe98SMax Filippov machine->ram_size : 0x08000000; 337996dfe98SMax Filippov uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 338a9a28591SMax Filippov 339e53fa62cSMax Filippov lowmem_end += env->config->sysram.location[0].addr; 340e53fa62cSMax Filippov cur_lowmem += env->config->sysram.location[0].addr; 341e53fa62cSMax Filippov 342e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 343e53fa62cSMax Filippov system_memory); 344b707ab75SMax Filippov 345b707ab75SMax Filippov if (kernel_cmdline) { 346a9a28591SMax Filippov bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 347a9a28591SMax Filippov } 348996dfe98SMax Filippov if (dtb_filename) { 349996dfe98SMax Filippov bp_size += get_tag_size(sizeof(uint32_t)); 350996dfe98SMax Filippov } 351f55b32e7SMax Filippov if (initrd_filename) { 352f55b32e7SMax Filippov bp_size += get_tag_size(sizeof(BpMemInfo)); 353f55b32e7SMax Filippov } 354b707ab75SMax Filippov 355a9a28591SMax Filippov /* Put kernel bootparameters to the end of that SRAM */ 356a9a28591SMax Filippov tagptr = (tagptr - bp_size) & ~0xff; 357a9a28591SMax Filippov cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 358b6edea8bSMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 359b6edea8bSMax Filippov sizeof(memory_location), &memory_location); 360a9a28591SMax Filippov 361a9a28591SMax Filippov if (kernel_cmdline) { 362a9a28591SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 363a9a28591SMax Filippov strlen(kernel_cmdline) + 1, kernel_cmdline); 364a9a28591SMax Filippov } 3650e80359eSMax Filippov #ifdef CONFIG_FDT 366996dfe98SMax Filippov if (dtb_filename) { 367996dfe98SMax Filippov int fdt_size; 368996dfe98SMax Filippov void *fdt = load_device_tree(dtb_filename, &fdt_size); 369996dfe98SMax Filippov uint32_t dtb_addr = tswap32(cur_lowmem); 370996dfe98SMax Filippov 371996dfe98SMax Filippov if (!fdt) { 372ebbb419aSGonglei error_report("could not load DTB '%s'", dtb_filename); 373996dfe98SMax Filippov exit(EXIT_FAILURE); 374996dfe98SMax Filippov } 375996dfe98SMax Filippov 376996dfe98SMax Filippov cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 377996dfe98SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 378996dfe98SMax Filippov sizeof(dtb_addr), &dtb_addr); 379b941329dSPhilippe Mathieu-Daudé cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); 380d1cb6784SChen Qun g_free(fdt); 381996dfe98SMax Filippov } 3820e80359eSMax Filippov #else 3830e80359eSMax Filippov if (dtb_filename) { 3840e80359eSMax Filippov error_report("could not load DTB '%s': " 3850e80359eSMax Filippov "FDT support is not configured in QEMU", 3860e80359eSMax Filippov dtb_filename); 3870e80359eSMax Filippov exit(EXIT_FAILURE); 3880e80359eSMax Filippov } 3890e80359eSMax Filippov #endif 390f55b32e7SMax Filippov if (initrd_filename) { 391f55b32e7SMax Filippov BpMemInfo initrd_location = { 0 }; 392f55b32e7SMax Filippov int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 393f55b32e7SMax Filippov lowmem_end - cur_lowmem); 394f55b32e7SMax Filippov 395f55b32e7SMax Filippov if (initrd_size < 0) { 396f55b32e7SMax Filippov initrd_size = load_image_targphys(initrd_filename, 397f55b32e7SMax Filippov cur_lowmem, 398f55b32e7SMax Filippov lowmem_end - cur_lowmem); 399f55b32e7SMax Filippov } 400f55b32e7SMax Filippov if (initrd_size < 0) { 401ebbb419aSGonglei error_report("could not load initrd '%s'", initrd_filename); 402f55b32e7SMax Filippov exit(EXIT_FAILURE); 403f55b32e7SMax Filippov } 404f55b32e7SMax Filippov initrd_location.start = tswap32(cur_lowmem); 405f55b32e7SMax Filippov initrd_location.end = tswap32(cur_lowmem + initrd_size); 406f55b32e7SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 407f55b32e7SMax Filippov sizeof(initrd_location), &initrd_location); 408b941329dSPhilippe Mathieu-Daudé cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); 409f55b32e7SMax Filippov } 410a9a28591SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 411b707ab75SMax Filippov env->regs[2] = tagptr; 412b707ab75SMax Filippov 413b707ab75SMax Filippov uint64_t elf_entry; 4144366e1dbSLiam Merwick int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, 415617160c9SBALATON Zoltan &elf_entry, NULL, NULL, NULL, be, EM_XTENSA, 0, 0); 416b707ab75SMax Filippov if (success > 0) { 417364d4802SMax Filippov entry_point = elf_entry; 418364d4802SMax Filippov } else { 419364d4802SMax Filippov hwaddr ep; 420364d4802SMax Filippov int is_linux; 42125bda50aSMax Filippov success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 4226d2e4530SMax Filippov translate_phys_addr, cpu); 423364d4802SMax Filippov if (success > 0 && is_linux) { 424364d4802SMax Filippov entry_point = ep; 425364d4802SMax Filippov } else { 426ebbb419aSGonglei error_report("could not load kernel '%s'", 427364d4802SMax Filippov kernel_filename); 428364d4802SMax Filippov exit(EXIT_FAILURE); 429364d4802SMax Filippov } 430364d4802SMax Filippov } 431364d4802SMax Filippov if (entry_point != env->pc) { 432339ef8fbSMax Filippov uint8_t boot[] = { 433364d4802SMax Filippov #ifdef TARGET_WORDS_BIGENDIAN 434339ef8fbSMax Filippov 0x60, 0x00, 0x08, /* j 1f */ 435339ef8fbSMax Filippov 0x00, /* .literal_position */ 436339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 437339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 438339ef8fbSMax Filippov /* 1: */ 439339ef8fbSMax Filippov 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 440339ef8fbSMax Filippov 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 441339ef8fbSMax Filippov 0x0a, 0x00, 0x00, /* jx a0 */ 442364d4802SMax Filippov #else 443339ef8fbSMax Filippov 0x06, 0x02, 0x00, /* j 1f */ 444339ef8fbSMax Filippov 0x00, /* .literal_position */ 445339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 446339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 447339ef8fbSMax Filippov /* 1: */ 448339ef8fbSMax Filippov 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 449339ef8fbSMax Filippov 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 450339ef8fbSMax Filippov 0xa0, 0x00, 0x00, /* jx a0 */ 451364d4802SMax Filippov #endif 452364d4802SMax Filippov }; 453339ef8fbSMax Filippov uint32_t entry_pc = tswap32(entry_point); 454339ef8fbSMax Filippov uint32_t entry_a2 = tswap32(tagptr); 455339ef8fbSMax Filippov 456339ef8fbSMax Filippov memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 457339ef8fbSMax Filippov memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 458339ef8fbSMax Filippov cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 459b707ab75SMax Filippov } 460b707ab75SMax Filippov } else { 461b707ab75SMax Filippov if (flash) { 462b707ab75SMax Filippov MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 463b707ab75SMax Filippov MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 464e53fa62cSMax Filippov uint32_t size = env->config->sysrom.location[0].size; 465e53fa62cSMax Filippov 466740ad9f7SMax Filippov if (board->flash->size - board->flash->boot_base < size) { 467740ad9f7SMax Filippov size = board->flash->size - board->flash->boot_base; 468e53fa62cSMax Filippov } 469b707ab75SMax Filippov 470188ce01dSMax Filippov memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 471740ad9f7SMax Filippov flash_mr, board->flash->boot_base, size); 472e53fa62cSMax Filippov memory_region_add_subregion(system_memory, 473e53fa62cSMax Filippov env->config->sysrom.location[0].addr, 474b707ab75SMax Filippov flash_io); 475e53fa62cSMax Filippov } else { 476e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 477e53fa62cSMax Filippov system_memory); 478b707ab75SMax Filippov } 479b707ab75SMax Filippov } 480b707ab75SMax Filippov } 481b707ab75SMax Filippov 48259b5e9bbSMax Filippov #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) 48359b5e9bbSMax Filippov 48485e2d8d5SMax Filippov static const hwaddr xtfpga_mmu_io[2] = { 48585e2d8d5SMax Filippov 0xf0000000, 48685e2d8d5SMax Filippov }; 48785e2d8d5SMax Filippov 48885e2d8d5SMax Filippov static const hwaddr xtfpga_nommu_io[2] = { 48985e2d8d5SMax Filippov 0x90000000, 49085e2d8d5SMax Filippov 0x70000000, 49185e2d8d5SMax Filippov }; 49285e2d8d5SMax Filippov 493740ad9f7SMax Filippov static const XtfpgaFlashDesc lx60_flash = { 494740ad9f7SMax Filippov .base = 0x08000000, 495740ad9f7SMax Filippov .size = 0x00400000, 496740ad9f7SMax Filippov .sector_size = 0x10000, 497740ad9f7SMax Filippov }; 498740ad9f7SMax Filippov 499188ce01dSMax Filippov static void xtfpga_lx60_init(MachineState *machine) 500b707ab75SMax Filippov { 501188ce01dSMax Filippov static const XtfpgaBoardDesc lx60_board = { 502740ad9f7SMax Filippov .flash = &lx60_flash, 503b707ab75SMax Filippov .sram_size = 0x20000, 50485e2d8d5SMax Filippov .io = xtfpga_mmu_io, 50585e2d8d5SMax Filippov }; 50685e2d8d5SMax Filippov xtfpga_init(&lx60_board, machine); 50785e2d8d5SMax Filippov } 50885e2d8d5SMax Filippov 50985e2d8d5SMax Filippov static void xtfpga_lx60_nommu_init(MachineState *machine) 51085e2d8d5SMax Filippov { 51185e2d8d5SMax Filippov static const XtfpgaBoardDesc lx60_board = { 51285e2d8d5SMax Filippov .flash = &lx60_flash, 51385e2d8d5SMax Filippov .sram_size = 0x20000, 51485e2d8d5SMax Filippov .io = xtfpga_nommu_io, 515b707ab75SMax Filippov }; 516188ce01dSMax Filippov xtfpga_init(&lx60_board, machine); 517b707ab75SMax Filippov } 518b707ab75SMax Filippov 519740ad9f7SMax Filippov static const XtfpgaFlashDesc lx200_flash = { 520740ad9f7SMax Filippov .base = 0x08000000, 521740ad9f7SMax Filippov .size = 0x01000000, 522740ad9f7SMax Filippov .sector_size = 0x20000, 523740ad9f7SMax Filippov }; 524740ad9f7SMax Filippov 525188ce01dSMax Filippov static void xtfpga_lx200_init(MachineState *machine) 526b707ab75SMax Filippov { 527188ce01dSMax Filippov static const XtfpgaBoardDesc lx200_board = { 528740ad9f7SMax Filippov .flash = &lx200_flash, 529b707ab75SMax Filippov .sram_size = 0x2000000, 53085e2d8d5SMax Filippov .io = xtfpga_mmu_io, 53185e2d8d5SMax Filippov }; 53285e2d8d5SMax Filippov xtfpga_init(&lx200_board, machine); 53385e2d8d5SMax Filippov } 53485e2d8d5SMax Filippov 53585e2d8d5SMax Filippov static void xtfpga_lx200_nommu_init(MachineState *machine) 53685e2d8d5SMax Filippov { 53785e2d8d5SMax Filippov static const XtfpgaBoardDesc lx200_board = { 53885e2d8d5SMax Filippov .flash = &lx200_flash, 53985e2d8d5SMax Filippov .sram_size = 0x2000000, 54085e2d8d5SMax Filippov .io = xtfpga_nommu_io, 541b707ab75SMax Filippov }; 542188ce01dSMax Filippov xtfpga_init(&lx200_board, machine); 543b707ab75SMax Filippov } 544b707ab75SMax Filippov 545740ad9f7SMax Filippov static const XtfpgaFlashDesc ml605_flash = { 546740ad9f7SMax Filippov .base = 0x08000000, 547740ad9f7SMax Filippov .size = 0x01000000, 548740ad9f7SMax Filippov .sector_size = 0x20000, 549740ad9f7SMax Filippov }; 550740ad9f7SMax Filippov 551188ce01dSMax Filippov static void xtfpga_ml605_init(MachineState *machine) 552b707ab75SMax Filippov { 553188ce01dSMax Filippov static const XtfpgaBoardDesc ml605_board = { 554740ad9f7SMax Filippov .flash = &ml605_flash, 555b707ab75SMax Filippov .sram_size = 0x2000000, 55685e2d8d5SMax Filippov .io = xtfpga_mmu_io, 55785e2d8d5SMax Filippov }; 55885e2d8d5SMax Filippov xtfpga_init(&ml605_board, machine); 55985e2d8d5SMax Filippov } 56085e2d8d5SMax Filippov 56185e2d8d5SMax Filippov static void xtfpga_ml605_nommu_init(MachineState *machine) 56285e2d8d5SMax Filippov { 56385e2d8d5SMax Filippov static const XtfpgaBoardDesc ml605_board = { 56485e2d8d5SMax Filippov .flash = &ml605_flash, 56585e2d8d5SMax Filippov .sram_size = 0x2000000, 56685e2d8d5SMax Filippov .io = xtfpga_nommu_io, 567b707ab75SMax Filippov }; 568188ce01dSMax Filippov xtfpga_init(&ml605_board, machine); 569b707ab75SMax Filippov } 570b707ab75SMax Filippov 571740ad9f7SMax Filippov static const XtfpgaFlashDesc kc705_flash = { 572740ad9f7SMax Filippov .base = 0x00000000, 573740ad9f7SMax Filippov .size = 0x08000000, 574740ad9f7SMax Filippov .boot_base = 0x06000000, 575740ad9f7SMax Filippov .sector_size = 0x20000, 576740ad9f7SMax Filippov }; 577740ad9f7SMax Filippov 578188ce01dSMax Filippov static void xtfpga_kc705_init(MachineState *machine) 579b707ab75SMax Filippov { 580188ce01dSMax Filippov static const XtfpgaBoardDesc kc705_board = { 581740ad9f7SMax Filippov .flash = &kc705_flash, 582b707ab75SMax Filippov .sram_size = 0x2000000, 58385e2d8d5SMax Filippov .io = xtfpga_mmu_io, 58485e2d8d5SMax Filippov }; 58585e2d8d5SMax Filippov xtfpga_init(&kc705_board, machine); 58685e2d8d5SMax Filippov } 58785e2d8d5SMax Filippov 58885e2d8d5SMax Filippov static void xtfpga_kc705_nommu_init(MachineState *machine) 58985e2d8d5SMax Filippov { 59085e2d8d5SMax Filippov static const XtfpgaBoardDesc kc705_board = { 59185e2d8d5SMax Filippov .flash = &kc705_flash, 59285e2d8d5SMax Filippov .sram_size = 0x2000000, 59385e2d8d5SMax Filippov .io = xtfpga_nommu_io, 594b707ab75SMax Filippov }; 595188ce01dSMax Filippov xtfpga_init(&kc705_board, machine); 596b707ab75SMax Filippov } 597b707ab75SMax Filippov 598188ce01dSMax Filippov static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 599b707ab75SMax Filippov { 6008a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 6018a661aeaSAndreas Färber 602e264d29dSEduardo Habkost mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 603188ce01dSMax Filippov mc->init = xtfpga_lx60_init; 604174e09b7SMax Filippov mc->max_cpus = 32; 605f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 60659b5e9bbSMax Filippov mc->default_ram_size = 64 * MiB; 607b707ab75SMax Filippov } 608b707ab75SMax Filippov 609188ce01dSMax Filippov static const TypeInfo xtfpga_lx60_type = { 6108a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lx60"), 6118a661aeaSAndreas Färber .parent = TYPE_MACHINE, 612188ce01dSMax Filippov .class_init = xtfpga_lx60_class_init, 6138a661aeaSAndreas Färber }; 614e264d29dSEduardo Habkost 61585e2d8d5SMax Filippov static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 61685e2d8d5SMax Filippov { 61785e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 61885e2d8d5SMax Filippov 619a3c5e49dSMax Filippov mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 62085e2d8d5SMax Filippov mc->init = xtfpga_lx60_nommu_init; 621174e09b7SMax Filippov mc->max_cpus = 32; 622a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 62359b5e9bbSMax Filippov mc->default_ram_size = 64 * MiB; 62485e2d8d5SMax Filippov } 62585e2d8d5SMax Filippov 62685e2d8d5SMax Filippov static const TypeInfo xtfpga_lx60_nommu_type = { 62785e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("lx60-nommu"), 62885e2d8d5SMax Filippov .parent = TYPE_MACHINE, 62985e2d8d5SMax Filippov .class_init = xtfpga_lx60_nommu_class_init, 63085e2d8d5SMax Filippov }; 63185e2d8d5SMax Filippov 632188ce01dSMax Filippov static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 633e264d29dSEduardo Habkost { 6348a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 6358a661aeaSAndreas Färber 636e264d29dSEduardo Habkost mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 637188ce01dSMax Filippov mc->init = xtfpga_lx200_init; 638174e09b7SMax Filippov mc->max_cpus = 32; 639f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 64059b5e9bbSMax Filippov mc->default_ram_size = 96 * MiB; 641e264d29dSEduardo Habkost } 642e264d29dSEduardo Habkost 643188ce01dSMax Filippov static const TypeInfo xtfpga_lx200_type = { 6448a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lx200"), 6458a661aeaSAndreas Färber .parent = TYPE_MACHINE, 646188ce01dSMax Filippov .class_init = xtfpga_lx200_class_init, 6478a661aeaSAndreas Färber }; 648e264d29dSEduardo Habkost 64985e2d8d5SMax Filippov static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 65085e2d8d5SMax Filippov { 65185e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 65285e2d8d5SMax Filippov 653a3c5e49dSMax Filippov mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 65485e2d8d5SMax Filippov mc->init = xtfpga_lx200_nommu_init; 655174e09b7SMax Filippov mc->max_cpus = 32; 656a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 65759b5e9bbSMax Filippov mc->default_ram_size = 96 * MiB; 65885e2d8d5SMax Filippov } 65985e2d8d5SMax Filippov 66085e2d8d5SMax Filippov static const TypeInfo xtfpga_lx200_nommu_type = { 66185e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("lx200-nommu"), 66285e2d8d5SMax Filippov .parent = TYPE_MACHINE, 66385e2d8d5SMax Filippov .class_init = xtfpga_lx200_nommu_class_init, 66485e2d8d5SMax Filippov }; 66585e2d8d5SMax Filippov 666188ce01dSMax Filippov static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 667e264d29dSEduardo Habkost { 6688a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 6698a661aeaSAndreas Färber 670e264d29dSEduardo Habkost mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 671188ce01dSMax Filippov mc->init = xtfpga_ml605_init; 672174e09b7SMax Filippov mc->max_cpus = 32; 673f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 67459b5e9bbSMax Filippov mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 675e264d29dSEduardo Habkost } 676e264d29dSEduardo Habkost 677188ce01dSMax Filippov static const TypeInfo xtfpga_ml605_type = { 6788a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("ml605"), 6798a661aeaSAndreas Färber .parent = TYPE_MACHINE, 680188ce01dSMax Filippov .class_init = xtfpga_ml605_class_init, 6818a661aeaSAndreas Färber }; 682e264d29dSEduardo Habkost 68385e2d8d5SMax Filippov static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 68485e2d8d5SMax Filippov { 68585e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 68685e2d8d5SMax Filippov 687a3c5e49dSMax Filippov mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 68885e2d8d5SMax Filippov mc->init = xtfpga_ml605_nommu_init; 689174e09b7SMax Filippov mc->max_cpus = 32; 690a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 69159b5e9bbSMax Filippov mc->default_ram_size = 256 * MiB; 69285e2d8d5SMax Filippov } 69385e2d8d5SMax Filippov 69485e2d8d5SMax Filippov static const TypeInfo xtfpga_ml605_nommu_type = { 69585e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("ml605-nommu"), 69685e2d8d5SMax Filippov .parent = TYPE_MACHINE, 69785e2d8d5SMax Filippov .class_init = xtfpga_ml605_nommu_class_init, 69885e2d8d5SMax Filippov }; 69985e2d8d5SMax Filippov 700188ce01dSMax Filippov static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 701e264d29dSEduardo Habkost { 7028a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 7038a661aeaSAndreas Färber 704e264d29dSEduardo Habkost mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 705188ce01dSMax Filippov mc->init = xtfpga_kc705_init; 706174e09b7SMax Filippov mc->max_cpus = 32; 707f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 70859b5e9bbSMax Filippov mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 709e264d29dSEduardo Habkost } 710e264d29dSEduardo Habkost 711188ce01dSMax Filippov static const TypeInfo xtfpga_kc705_type = { 7128a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("kc705"), 7138a661aeaSAndreas Färber .parent = TYPE_MACHINE, 714188ce01dSMax Filippov .class_init = xtfpga_kc705_class_init, 7158a661aeaSAndreas Färber }; 7168a661aeaSAndreas Färber 71785e2d8d5SMax Filippov static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 71885e2d8d5SMax Filippov { 71985e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 72085e2d8d5SMax Filippov 721a3c5e49dSMax Filippov mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 72285e2d8d5SMax Filippov mc->init = xtfpga_kc705_nommu_init; 723174e09b7SMax Filippov mc->max_cpus = 32; 724a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 72559b5e9bbSMax Filippov mc->default_ram_size = 256 * MiB; 72685e2d8d5SMax Filippov } 72785e2d8d5SMax Filippov 72885e2d8d5SMax Filippov static const TypeInfo xtfpga_kc705_nommu_type = { 72985e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("kc705-nommu"), 73085e2d8d5SMax Filippov .parent = TYPE_MACHINE, 73185e2d8d5SMax Filippov .class_init = xtfpga_kc705_nommu_class_init, 73285e2d8d5SMax Filippov }; 73385e2d8d5SMax Filippov 734188ce01dSMax Filippov static void xtfpga_machines_init(void) 7358a661aeaSAndreas Färber { 736188ce01dSMax Filippov type_register_static(&xtfpga_lx60_type); 737188ce01dSMax Filippov type_register_static(&xtfpga_lx200_type); 738188ce01dSMax Filippov type_register_static(&xtfpga_ml605_type); 739188ce01dSMax Filippov type_register_static(&xtfpga_kc705_type); 74085e2d8d5SMax Filippov type_register_static(&xtfpga_lx60_nommu_type); 74185e2d8d5SMax Filippov type_register_static(&xtfpga_lx200_nommu_type); 74285e2d8d5SMax Filippov type_register_static(&xtfpga_ml605_nommu_type); 74385e2d8d5SMax Filippov type_register_static(&xtfpga_kc705_nommu_type); 7448a661aeaSAndreas Färber } 7458a661aeaSAndreas Färber 746188ce01dSMax Filippov type_init(xtfpga_machines_init) 747