1b707ab75SMax Filippov /* 2b707ab75SMax Filippov * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab. 3b707ab75SMax Filippov * All rights reserved. 4b707ab75SMax Filippov * 5b707ab75SMax Filippov * Redistribution and use in source and binary forms, with or without 6b707ab75SMax Filippov * modification, are permitted provided that the following conditions are met: 7b707ab75SMax Filippov * * Redistributions of source code must retain the above copyright 8b707ab75SMax Filippov * notice, this list of conditions and the following disclaimer. 9b707ab75SMax Filippov * * Redistributions in binary form must reproduce the above copyright 10b707ab75SMax Filippov * notice, this list of conditions and the following disclaimer in the 11b707ab75SMax Filippov * documentation and/or other materials provided with the distribution. 12b707ab75SMax Filippov * * Neither the name of the Open Source and Linux Lab nor the 13b707ab75SMax Filippov * names of its contributors may be used to endorse or promote products 14b707ab75SMax Filippov * derived from this software without specific prior written permission. 15b707ab75SMax Filippov * 16b707ab75SMax Filippov * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17b707ab75SMax Filippov * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18b707ab75SMax Filippov * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19b707ab75SMax Filippov * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20b707ab75SMax Filippov * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21b707ab75SMax Filippov * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 22b707ab75SMax Filippov * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND 23b707ab75SMax Filippov * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24b707ab75SMax Filippov * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 25b707ab75SMax Filippov * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26b707ab75SMax Filippov */ 27b707ab75SMax Filippov 2809aae23dSPeter Maydell #include "qemu/osdep.h" 29b941329dSPhilippe Mathieu-Daudé #include "qemu/units.h" 30da34e65cSMarkus Armbruster #include "qapi/error.h" 314771d756SPaolo Bonzini #include "cpu.h" 32b707ab75SMax Filippov #include "sysemu/sysemu.h" 33b707ab75SMax Filippov #include "hw/boards.h" 34b707ab75SMax Filippov #include "hw/loader.h" 35a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 36b707ab75SMax Filippov #include "elf.h" 37b707ab75SMax Filippov #include "exec/memory.h" 38b707ab75SMax Filippov #include "hw/char/serial.h" 39b707ab75SMax Filippov #include "net/net.h" 40b707ab75SMax Filippov #include "hw/sysbus.h" 41b707ab75SMax Filippov #include "hw/block/flash.h" 428228e353SMarc-André Lureau #include "chardev/char.h" 43996dfe98SMax Filippov #include "sysemu/device_tree.h" 4471e8a915SMarkus Armbruster #include "sysemu/reset.h" 4554d31236SMarkus Armbruster #include "sysemu/runstate.h" 468488ab02SMax Filippov #include "qemu/error-report.h" 47922a01a0SMarkus Armbruster #include "qemu/option.h" 48b707ab75SMax Filippov #include "bootparam.h" 49e53fa62cSMax Filippov #include "xtensa_memory.h" 501acd90bfSMax Filippov #include "hw/xtensa/mx_pic.h" 51d6454270SMarkus Armbruster #include "migration/vmstate.h" 52b707ab75SMax Filippov 53740ad9f7SMax Filippov typedef struct XtfpgaFlashDesc { 54740ad9f7SMax Filippov hwaddr base; 55740ad9f7SMax Filippov size_t size; 56740ad9f7SMax Filippov size_t boot_base; 57740ad9f7SMax Filippov size_t sector_size; 58740ad9f7SMax Filippov } XtfpgaFlashDesc; 59740ad9f7SMax Filippov 60188ce01dSMax Filippov typedef struct XtfpgaBoardDesc { 61740ad9f7SMax Filippov const XtfpgaFlashDesc *flash; 62b707ab75SMax Filippov size_t sram_size; 6385e2d8d5SMax Filippov const hwaddr *io; 64188ce01dSMax Filippov } XtfpgaBoardDesc; 65b707ab75SMax Filippov 66188ce01dSMax Filippov typedef struct XtfpgaFpgaState { 67b707ab75SMax Filippov MemoryRegion iomem; 68fff7bf14SMax Filippov uint32_t freq; 69b707ab75SMax Filippov uint32_t leds; 70b707ab75SMax Filippov uint32_t switches; 71188ce01dSMax Filippov } XtfpgaFpgaState; 72b707ab75SMax Filippov 73188ce01dSMax Filippov static void xtfpga_fpga_reset(void *opaque) 74b707ab75SMax Filippov { 75188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 76b707ab75SMax Filippov 77b707ab75SMax Filippov s->leds = 0; 78b707ab75SMax Filippov s->switches = 0; 79b707ab75SMax Filippov } 80b707ab75SMax Filippov 81188ce01dSMax Filippov static uint64_t xtfpga_fpga_read(void *opaque, hwaddr addr, 82b707ab75SMax Filippov unsigned size) 83b707ab75SMax Filippov { 84188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 85b707ab75SMax Filippov 86b707ab75SMax Filippov switch (addr) { 87b707ab75SMax Filippov case 0x0: /*build date code*/ 88b707ab75SMax Filippov return 0x09272011; 89b707ab75SMax Filippov 90b707ab75SMax Filippov case 0x4: /*processor clock frequency, Hz*/ 91fff7bf14SMax Filippov return s->freq; 92b707ab75SMax Filippov 93b707ab75SMax Filippov case 0x8: /*LEDs (off = 0, on = 1)*/ 94b707ab75SMax Filippov return s->leds; 95b707ab75SMax Filippov 96b707ab75SMax Filippov case 0xc: /*DIP switches (off = 0, on = 1)*/ 97b707ab75SMax Filippov return s->switches; 98b707ab75SMax Filippov } 99b707ab75SMax Filippov return 0; 100b707ab75SMax Filippov } 101b707ab75SMax Filippov 102188ce01dSMax Filippov static void xtfpga_fpga_write(void *opaque, hwaddr addr, 103b707ab75SMax Filippov uint64_t val, unsigned size) 104b707ab75SMax Filippov { 105188ce01dSMax Filippov XtfpgaFpgaState *s = opaque; 106b707ab75SMax Filippov 107b707ab75SMax Filippov switch (addr) { 108b707ab75SMax Filippov case 0x8: /*LEDs (off = 0, on = 1)*/ 109b707ab75SMax Filippov s->leds = val; 110b707ab75SMax Filippov break; 111b707ab75SMax Filippov 112b707ab75SMax Filippov case 0x10: /*board reset*/ 113b707ab75SMax Filippov if (val == 0xdead) { 114cf83f140SEric Blake qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 115b707ab75SMax Filippov } 116b707ab75SMax Filippov break; 117b707ab75SMax Filippov } 118b707ab75SMax Filippov } 119b707ab75SMax Filippov 120188ce01dSMax Filippov static const MemoryRegionOps xtfpga_fpga_ops = { 121188ce01dSMax Filippov .read = xtfpga_fpga_read, 122188ce01dSMax Filippov .write = xtfpga_fpga_write, 123b707ab75SMax Filippov .endianness = DEVICE_NATIVE_ENDIAN, 124b707ab75SMax Filippov }; 125b707ab75SMax Filippov 126188ce01dSMax Filippov static XtfpgaFpgaState *xtfpga_fpga_init(MemoryRegion *address_space, 127fff7bf14SMax Filippov hwaddr base, uint32_t freq) 128b707ab75SMax Filippov { 129b21e2380SMarkus Armbruster XtfpgaFpgaState *s = g_new(XtfpgaFpgaState, 1); 130b707ab75SMax Filippov 131188ce01dSMax Filippov memory_region_init_io(&s->iomem, NULL, &xtfpga_fpga_ops, s, 132188ce01dSMax Filippov "xtfpga.fpga", 0x10000); 133b707ab75SMax Filippov memory_region_add_subregion(address_space, base, &s->iomem); 134fff7bf14SMax Filippov s->freq = freq; 135188ce01dSMax Filippov xtfpga_fpga_reset(s); 136188ce01dSMax Filippov qemu_register_reset(xtfpga_fpga_reset, s); 137b707ab75SMax Filippov return s; 138b707ab75SMax Filippov } 139b707ab75SMax Filippov 140188ce01dSMax Filippov static void xtfpga_net_init(MemoryRegion *address_space, 141b707ab75SMax Filippov hwaddr base, 142b707ab75SMax Filippov hwaddr descriptors, 143b707ab75SMax Filippov hwaddr buffers, 144b707ab75SMax Filippov qemu_irq irq, NICInfo *nd) 145b707ab75SMax Filippov { 146b707ab75SMax Filippov DeviceState *dev; 147b707ab75SMax Filippov SysBusDevice *s; 148b707ab75SMax Filippov MemoryRegion *ram; 149b707ab75SMax Filippov 1503e80f690SMarkus Armbruster dev = qdev_new("open_eth"); 151b707ab75SMax Filippov qdev_set_nic_properties(dev, nd); 152b707ab75SMax Filippov 153b707ab75SMax Filippov s = SYS_BUS_DEVICE(dev); 1543c6ef471SMarkus Armbruster sysbus_realize_and_unref(s, &error_fatal); 155b707ab75SMax Filippov sysbus_connect_irq(s, 0, irq); 156b707ab75SMax Filippov memory_region_add_subregion(address_space, base, 157b707ab75SMax Filippov sysbus_mmio_get_region(s, 0)); 158b707ab75SMax Filippov memory_region_add_subregion(address_space, descriptors, 159b707ab75SMax Filippov sysbus_mmio_get_region(s, 1)); 160b707ab75SMax Filippov 161b707ab75SMax Filippov ram = g_malloc(sizeof(*ram)); 162b941329dSPhilippe Mathieu-Daudé memory_region_init_ram_nomigrate(ram, OBJECT(s), "open_eth.ram", 16 * KiB, 163f8ed85acSMarkus Armbruster &error_fatal); 164b707ab75SMax Filippov vmstate_register_ram_global(ram); 165b707ab75SMax Filippov memory_region_add_subregion(address_space, buffers, ram); 166b707ab75SMax Filippov } 167b707ab75SMax Filippov 16816434065SMarkus Armbruster static PFlashCFI01 *xtfpga_flash_init(MemoryRegion *address_space, 169188ce01dSMax Filippov const XtfpgaBoardDesc *board, 17068931a40SMax Filippov DriveInfo *dinfo, int be) 17168931a40SMax Filippov { 17268931a40SMax Filippov SysBusDevice *s; 1733e80f690SMarkus Armbruster DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 17468931a40SMax Filippov 175934df912SMarkus Armbruster qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); 17668931a40SMax Filippov qdev_prop_set_uint32(dev, "num-blocks", 177740ad9f7SMax Filippov board->flash->size / board->flash->sector_size); 178740ad9f7SMax Filippov qdev_prop_set_uint64(dev, "sector-length", board->flash->sector_size); 179f9a555e4SMax Filippov qdev_prop_set_uint8(dev, "width", 2); 18068931a40SMax Filippov qdev_prop_set_bit(dev, "big-endian", be); 181188ce01dSMax Filippov qdev_prop_set_string(dev, "name", "xtfpga.io.flash"); 18268931a40SMax Filippov s = SYS_BUS_DEVICE(dev); 1833c6ef471SMarkus Armbruster sysbus_realize_and_unref(s, &error_fatal); 184740ad9f7SMax Filippov memory_region_add_subregion(address_space, board->flash->base, 18568931a40SMax Filippov sysbus_mmio_get_region(s, 0)); 18681c7db72SMarkus Armbruster return PFLASH_CFI01(dev); 18768931a40SMax Filippov } 18868931a40SMax Filippov 189b707ab75SMax Filippov static uint64_t translate_phys_addr(void *opaque, uint64_t addr) 190b707ab75SMax Filippov { 191b707ab75SMax Filippov XtensaCPU *cpu = opaque; 192b707ab75SMax Filippov 193b707ab75SMax Filippov return cpu_get_phys_page_debug(CPU(cpu), addr); 194b707ab75SMax Filippov } 195b707ab75SMax Filippov 196188ce01dSMax Filippov static void xtfpga_reset(void *opaque) 197b707ab75SMax Filippov { 198b707ab75SMax Filippov XtensaCPU *cpu = opaque; 199b707ab75SMax Filippov 200b707ab75SMax Filippov cpu_reset(CPU(cpu)); 201b707ab75SMax Filippov } 202b707ab75SMax Filippov 203188ce01dSMax Filippov static uint64_t xtfpga_io_read(void *opaque, hwaddr addr, 2048bb3b575SMax Filippov unsigned size) 2058bb3b575SMax Filippov { 2068bb3b575SMax Filippov return 0; 2078bb3b575SMax Filippov } 2088bb3b575SMax Filippov 209188ce01dSMax Filippov static void xtfpga_io_write(void *opaque, hwaddr addr, 2108bb3b575SMax Filippov uint64_t val, unsigned size) 2118bb3b575SMax Filippov { 2128bb3b575SMax Filippov } 2138bb3b575SMax Filippov 214188ce01dSMax Filippov static const MemoryRegionOps xtfpga_io_ops = { 215188ce01dSMax Filippov .read = xtfpga_io_read, 216188ce01dSMax Filippov .write = xtfpga_io_write, 2178bb3b575SMax Filippov .endianness = DEVICE_NATIVE_ENDIAN, 2188bb3b575SMax Filippov }; 2198bb3b575SMax Filippov 220188ce01dSMax Filippov static void xtfpga_init(const XtfpgaBoardDesc *board, MachineState *machine) 221b707ab75SMax Filippov { 222b707ab75SMax Filippov MemoryRegion *system_memory = get_system_memory(); 223b707ab75SMax Filippov XtensaCPU *cpu = NULL; 224b707ab75SMax Filippov CPUXtensaState *env = NULL; 225e53fa62cSMax Filippov MemoryRegion *system_io; 2261acd90bfSMax Filippov XtensaMxPic *mx_pic = NULL; 22766f03d7eSMax Filippov qemu_irq *extints; 228b707ab75SMax Filippov DriveInfo *dinfo; 22916434065SMarkus Armbruster PFlashCFI01 *flash = NULL; 230f2ce39b4SPaolo Bonzini const char *kernel_filename = machine->kernel_filename; 231f2ce39b4SPaolo Bonzini const char *kernel_cmdline = machine->kernel_cmdline; 232f2ce39b4SPaolo Bonzini const char *dtb_filename = machine->dtb; 233f2ce39b4SPaolo Bonzini const char *initrd_filename = machine->initrd_filename; 234b941329dSPhilippe Mathieu-Daudé const unsigned system_io_size = 224 * MiB; 235fff7bf14SMax Filippov uint32_t freq = 10000000; 236b707ab75SMax Filippov int n; 23733decbd2SLike Xu unsigned int smp_cpus = machine->smp.cpus; 238b707ab75SMax Filippov 2391acd90bfSMax Filippov if (smp_cpus > 1) { 2401acd90bfSMax Filippov mx_pic = xtensa_mx_pic_init(31); 2411acd90bfSMax Filippov qemu_register_reset(xtensa_mx_pic_reset, mx_pic); 2421acd90bfSMax Filippov } 243b707ab75SMax Filippov for (n = 0; n < smp_cpus; n++) { 244288a3f2eSMax Filippov CPUXtensaState *cenv = NULL; 245b707ab75SMax Filippov 246288a3f2eSMax Filippov cpu = XTENSA_CPU(cpu_create(machine->cpu_type)); 247288a3f2eSMax Filippov cenv = &cpu->env; 248288a3f2eSMax Filippov if (!env) { 249288a3f2eSMax Filippov env = cenv; 250fff7bf14SMax Filippov freq = env->config->clock_freq_khz * 1000; 251288a3f2eSMax Filippov } 252288a3f2eSMax Filippov 2531acd90bfSMax Filippov if (mx_pic) { 2541acd90bfSMax Filippov MemoryRegion *mx_eri; 2551acd90bfSMax Filippov 2561acd90bfSMax Filippov mx_eri = xtensa_mx_pic_register_cpu(mx_pic, 2571acd90bfSMax Filippov xtensa_get_extints(cenv), 2581acd90bfSMax Filippov xtensa_get_runstall(cenv)); 2591acd90bfSMax Filippov memory_region_add_subregion(xtensa_get_er_region(cenv), 2601acd90bfSMax Filippov 0, mx_eri); 2611acd90bfSMax Filippov } 262288a3f2eSMax Filippov cenv->sregs[PRID] = n; 2631acd90bfSMax Filippov xtensa_select_static_vectors(cenv, n != 0); 264188ce01dSMax Filippov qemu_register_reset(xtfpga_reset, cpu); 265b707ab75SMax Filippov /* Need MMU initialized prior to ELF loading, 266b707ab75SMax Filippov * so that ELF gets loaded into virtual addresses 267b707ab75SMax Filippov */ 268b707ab75SMax Filippov cpu_reset(CPU(cpu)); 269b707ab75SMax Filippov } 2701acd90bfSMax Filippov if (smp_cpus > 1) { 2711acd90bfSMax Filippov extints = xtensa_mx_pic_get_extints(mx_pic); 2721acd90bfSMax Filippov } else { 27366f03d7eSMax Filippov extints = xtensa_get_extints(env); 2741acd90bfSMax Filippov } 275b707ab75SMax Filippov 276e53fa62cSMax Filippov if (env) { 277e53fa62cSMax Filippov XtensaMemory sysram = env->config->sysram; 278e53fa62cSMax Filippov 279e53fa62cSMax Filippov sysram.location[0].size = machine->ram_size; 280e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->instrom, "xtensa.instrom", 281e53fa62cSMax Filippov system_memory); 282e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->instram, "xtensa.instram", 283e53fa62cSMax Filippov system_memory); 284e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->datarom, "xtensa.datarom", 285e53fa62cSMax Filippov system_memory); 286e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->dataram, "xtensa.dataram", 287e53fa62cSMax Filippov system_memory); 288e53fa62cSMax Filippov xtensa_create_memory_regions(&sysram, "xtensa.sysram", 289e53fa62cSMax Filippov system_memory); 290e53fa62cSMax Filippov } 291b707ab75SMax Filippov 292b707ab75SMax Filippov system_io = g_malloc(sizeof(*system_io)); 293188ce01dSMax Filippov memory_region_init_io(system_io, NULL, &xtfpga_io_ops, NULL, "xtfpga.io", 29485e2d8d5SMax Filippov system_io_size); 29585e2d8d5SMax Filippov memory_region_add_subregion(system_memory, board->io[0], system_io); 29685e2d8d5SMax Filippov if (board->io[1]) { 29785e2d8d5SMax Filippov MemoryRegion *io = g_malloc(sizeof(*io)); 29885e2d8d5SMax Filippov 29985e2d8d5SMax Filippov memory_region_init_alias(io, NULL, "xtfpga.io.cached", 30085e2d8d5SMax Filippov system_io, 0, system_io_size); 30185e2d8d5SMax Filippov memory_region_add_subregion(system_memory, board->io[1], io); 30285e2d8d5SMax Filippov } 303fff7bf14SMax Filippov xtfpga_fpga_init(system_io, 0x0d020000, freq); 304b707ab75SMax Filippov if (nd_table[0].used) { 305188ce01dSMax Filippov xtfpga_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000, 30666f03d7eSMax Filippov extints[1], nd_table); 307b707ab75SMax Filippov } 308b707ab75SMax Filippov 30966f03d7eSMax Filippov serial_mm_init(system_io, 0x0d050020, 2, extints[0], 3109bca0edbSPeter Maydell 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 311b707ab75SMax Filippov 312b707ab75SMax Filippov dinfo = drive_get(IF_PFLASH, 0, 0); 313b707ab75SMax Filippov if (dinfo) { 314ded625e7SThomas Huth flash = xtfpga_flash_init(system_io, board, dinfo, TARGET_BIG_ENDIAN); 315b707ab75SMax Filippov } 316b707ab75SMax Filippov 317b707ab75SMax Filippov /* Use presence of kernel file name as 'boot from SRAM' switch. */ 318b707ab75SMax Filippov if (kernel_filename) { 319364d4802SMax Filippov uint32_t entry_point = env->pc; 320b6edea8bSMax Filippov size_t bp_size = 3 * get_tag_size(0); /* first/last and memory tags */ 321e53fa62cSMax Filippov uint32_t tagptr = env->config->sysrom.location[0].addr + 322e53fa62cSMax Filippov board->sram_size; 323a9a28591SMax Filippov uint32_t cur_tagptr; 324b6edea8bSMax Filippov BpMemInfo memory_location = { 325b6edea8bSMax Filippov .type = tswap32(MEMORY_TYPE_CONVENTIONAL), 326e53fa62cSMax Filippov .start = tswap32(env->config->sysram.location[0].addr), 327e53fa62cSMax Filippov .end = tswap32(env->config->sysram.location[0].addr + 328e53fa62cSMax Filippov machine->ram_size), 329b6edea8bSMax Filippov }; 330996dfe98SMax Filippov uint32_t lowmem_end = machine->ram_size < 0x08000000 ? 331996dfe98SMax Filippov machine->ram_size : 0x08000000; 332996dfe98SMax Filippov uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096); 333a9a28591SMax Filippov 334e53fa62cSMax Filippov lowmem_end += env->config->sysram.location[0].addr; 335e53fa62cSMax Filippov cur_lowmem += env->config->sysram.location[0].addr; 336e53fa62cSMax Filippov 337e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 338e53fa62cSMax Filippov system_memory); 339b707ab75SMax Filippov 340b707ab75SMax Filippov if (kernel_cmdline) { 341a9a28591SMax Filippov bp_size += get_tag_size(strlen(kernel_cmdline) + 1); 342a9a28591SMax Filippov } 343996dfe98SMax Filippov if (dtb_filename) { 344996dfe98SMax Filippov bp_size += get_tag_size(sizeof(uint32_t)); 345996dfe98SMax Filippov } 346f55b32e7SMax Filippov if (initrd_filename) { 347f55b32e7SMax Filippov bp_size += get_tag_size(sizeof(BpMemInfo)); 348f55b32e7SMax Filippov } 349b707ab75SMax Filippov 350a9a28591SMax Filippov /* Put kernel bootparameters to the end of that SRAM */ 351a9a28591SMax Filippov tagptr = (tagptr - bp_size) & ~0xff; 352a9a28591SMax Filippov cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL); 353b6edea8bSMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY, 354b6edea8bSMax Filippov sizeof(memory_location), &memory_location); 355a9a28591SMax Filippov 356a9a28591SMax Filippov if (kernel_cmdline) { 357a9a28591SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE, 358a9a28591SMax Filippov strlen(kernel_cmdline) + 1, kernel_cmdline); 359a9a28591SMax Filippov } 3600e80359eSMax Filippov #ifdef CONFIG_FDT 361996dfe98SMax Filippov if (dtb_filename) { 362996dfe98SMax Filippov int fdt_size; 363996dfe98SMax Filippov void *fdt = load_device_tree(dtb_filename, &fdt_size); 364996dfe98SMax Filippov uint32_t dtb_addr = tswap32(cur_lowmem); 365996dfe98SMax Filippov 366996dfe98SMax Filippov if (!fdt) { 367ebbb419aSGonglei error_report("could not load DTB '%s'", dtb_filename); 368996dfe98SMax Filippov exit(EXIT_FAILURE); 369996dfe98SMax Filippov } 370996dfe98SMax Filippov 371996dfe98SMax Filippov cpu_physical_memory_write(cur_lowmem, fdt, fdt_size); 372996dfe98SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT, 373996dfe98SMax Filippov sizeof(dtb_addr), &dtb_addr); 374b941329dSPhilippe Mathieu-Daudé cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4 * KiB); 375d1cb6784SChen Qun g_free(fdt); 376996dfe98SMax Filippov } 3770e80359eSMax Filippov #else 3780e80359eSMax Filippov if (dtb_filename) { 3790e80359eSMax Filippov error_report("could not load DTB '%s': " 3800e80359eSMax Filippov "FDT support is not configured in QEMU", 3810e80359eSMax Filippov dtb_filename); 3820e80359eSMax Filippov exit(EXIT_FAILURE); 3830e80359eSMax Filippov } 3840e80359eSMax Filippov #endif 385f55b32e7SMax Filippov if (initrd_filename) { 386f55b32e7SMax Filippov BpMemInfo initrd_location = { 0 }; 387f55b32e7SMax Filippov int initrd_size = load_ramdisk(initrd_filename, cur_lowmem, 388f55b32e7SMax Filippov lowmem_end - cur_lowmem); 389f55b32e7SMax Filippov 390f55b32e7SMax Filippov if (initrd_size < 0) { 391f55b32e7SMax Filippov initrd_size = load_image_targphys(initrd_filename, 392f55b32e7SMax Filippov cur_lowmem, 393f55b32e7SMax Filippov lowmem_end - cur_lowmem); 394f55b32e7SMax Filippov } 395f55b32e7SMax Filippov if (initrd_size < 0) { 396ebbb419aSGonglei error_report("could not load initrd '%s'", initrd_filename); 397f55b32e7SMax Filippov exit(EXIT_FAILURE); 398f55b32e7SMax Filippov } 399f55b32e7SMax Filippov initrd_location.start = tswap32(cur_lowmem); 400f55b32e7SMax Filippov initrd_location.end = tswap32(cur_lowmem + initrd_size); 401f55b32e7SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD, 402f55b32e7SMax Filippov sizeof(initrd_location), &initrd_location); 403b941329dSPhilippe Mathieu-Daudé cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4 * KiB); 404f55b32e7SMax Filippov } 405a9a28591SMax Filippov cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL); 406b707ab75SMax Filippov env->regs[2] = tagptr; 407b707ab75SMax Filippov 408b707ab75SMax Filippov uint64_t elf_entry; 4094366e1dbSLiam Merwick int success = load_elf(kernel_filename, NULL, translate_phys_addr, cpu, 410ded625e7SThomas Huth &elf_entry, NULL, NULL, NULL, TARGET_BIG_ENDIAN, 411ded625e7SThomas Huth EM_XTENSA, 0, 0); 412b707ab75SMax Filippov if (success > 0) { 413364d4802SMax Filippov entry_point = elf_entry; 414364d4802SMax Filippov } else { 415364d4802SMax Filippov hwaddr ep; 416364d4802SMax Filippov int is_linux; 41725bda50aSMax Filippov success = load_uimage(kernel_filename, &ep, NULL, &is_linux, 4186d2e4530SMax Filippov translate_phys_addr, cpu); 419364d4802SMax Filippov if (success > 0 && is_linux) { 420364d4802SMax Filippov entry_point = ep; 421364d4802SMax Filippov } else { 422ebbb419aSGonglei error_report("could not load kernel '%s'", 423364d4802SMax Filippov kernel_filename); 424364d4802SMax Filippov exit(EXIT_FAILURE); 425364d4802SMax Filippov } 426364d4802SMax Filippov } 427364d4802SMax Filippov if (entry_point != env->pc) { 428339ef8fbSMax Filippov uint8_t boot[] = { 429ee3eb3a7SMarc-André Lureau #if TARGET_BIG_ENDIAN 430339ef8fbSMax Filippov 0x60, 0x00, 0x08, /* j 1f */ 431339ef8fbSMax Filippov 0x00, /* .literal_position */ 432339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 433339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 434339ef8fbSMax Filippov /* 1: */ 435339ef8fbSMax Filippov 0x10, 0xff, 0xfe, /* l32r a0, entry_pc */ 436339ef8fbSMax Filippov 0x12, 0xff, 0xfe, /* l32r a2, entry_a2 */ 437339ef8fbSMax Filippov 0x0a, 0x00, 0x00, /* jx a0 */ 438364d4802SMax Filippov #else 439339ef8fbSMax Filippov 0x06, 0x02, 0x00, /* j 1f */ 440339ef8fbSMax Filippov 0x00, /* .literal_position */ 441339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_pc */ 442339ef8fbSMax Filippov 0x00, 0x00, 0x00, 0x00, /* .literal entry_a2 */ 443339ef8fbSMax Filippov /* 1: */ 444339ef8fbSMax Filippov 0x01, 0xfe, 0xff, /* l32r a0, entry_pc */ 445339ef8fbSMax Filippov 0x21, 0xfe, 0xff, /* l32r a2, entry_a2 */ 446339ef8fbSMax Filippov 0xa0, 0x00, 0x00, /* jx a0 */ 447364d4802SMax Filippov #endif 448364d4802SMax Filippov }; 449339ef8fbSMax Filippov uint32_t entry_pc = tswap32(entry_point); 450339ef8fbSMax Filippov uint32_t entry_a2 = tswap32(tagptr); 451339ef8fbSMax Filippov 452339ef8fbSMax Filippov memcpy(boot + 4, &entry_pc, sizeof(entry_pc)); 453339ef8fbSMax Filippov memcpy(boot + 8, &entry_a2, sizeof(entry_a2)); 454339ef8fbSMax Filippov cpu_physical_memory_write(env->pc, boot, sizeof(boot)); 455b707ab75SMax Filippov } 456b707ab75SMax Filippov } else { 457b707ab75SMax Filippov if (flash) { 458b707ab75SMax Filippov MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash); 459b707ab75SMax Filippov MemoryRegion *flash_io = g_malloc(sizeof(*flash_io)); 460e53fa62cSMax Filippov uint32_t size = env->config->sysrom.location[0].size; 461e53fa62cSMax Filippov 462740ad9f7SMax Filippov if (board->flash->size - board->flash->boot_base < size) { 463740ad9f7SMax Filippov size = board->flash->size - board->flash->boot_base; 464e53fa62cSMax Filippov } 465b707ab75SMax Filippov 466188ce01dSMax Filippov memory_region_init_alias(flash_io, NULL, "xtfpga.flash", 467740ad9f7SMax Filippov flash_mr, board->flash->boot_base, size); 468e53fa62cSMax Filippov memory_region_add_subregion(system_memory, 469e53fa62cSMax Filippov env->config->sysrom.location[0].addr, 470b707ab75SMax Filippov flash_io); 471e53fa62cSMax Filippov } else { 472e53fa62cSMax Filippov xtensa_create_memory_regions(&env->config->sysrom, "xtensa.sysrom", 473e53fa62cSMax Filippov system_memory); 474b707ab75SMax Filippov } 475b707ab75SMax Filippov } 476b707ab75SMax Filippov } 477b707ab75SMax Filippov 47859b5e9bbSMax Filippov #define XTFPGA_MMU_RESERVED_MEMORY_SIZE (128 * MiB) 47959b5e9bbSMax Filippov 48085e2d8d5SMax Filippov static const hwaddr xtfpga_mmu_io[2] = { 48185e2d8d5SMax Filippov 0xf0000000, 48285e2d8d5SMax Filippov }; 48385e2d8d5SMax Filippov 48485e2d8d5SMax Filippov static const hwaddr xtfpga_nommu_io[2] = { 48585e2d8d5SMax Filippov 0x90000000, 48685e2d8d5SMax Filippov 0x70000000, 48785e2d8d5SMax Filippov }; 48885e2d8d5SMax Filippov 489740ad9f7SMax Filippov static const XtfpgaFlashDesc lx60_flash = { 490740ad9f7SMax Filippov .base = 0x08000000, 491740ad9f7SMax Filippov .size = 0x00400000, 492740ad9f7SMax Filippov .sector_size = 0x10000, 493740ad9f7SMax Filippov }; 494740ad9f7SMax Filippov 495188ce01dSMax Filippov static void xtfpga_lx60_init(MachineState *machine) 496b707ab75SMax Filippov { 497188ce01dSMax Filippov static const XtfpgaBoardDesc lx60_board = { 498740ad9f7SMax Filippov .flash = &lx60_flash, 499b707ab75SMax Filippov .sram_size = 0x20000, 50085e2d8d5SMax Filippov .io = xtfpga_mmu_io, 50185e2d8d5SMax Filippov }; 50285e2d8d5SMax Filippov xtfpga_init(&lx60_board, machine); 50385e2d8d5SMax Filippov } 50485e2d8d5SMax Filippov 50585e2d8d5SMax Filippov static void xtfpga_lx60_nommu_init(MachineState *machine) 50685e2d8d5SMax Filippov { 50785e2d8d5SMax Filippov static const XtfpgaBoardDesc lx60_board = { 50885e2d8d5SMax Filippov .flash = &lx60_flash, 50985e2d8d5SMax Filippov .sram_size = 0x20000, 51085e2d8d5SMax Filippov .io = xtfpga_nommu_io, 511b707ab75SMax Filippov }; 512188ce01dSMax Filippov xtfpga_init(&lx60_board, machine); 513b707ab75SMax Filippov } 514b707ab75SMax Filippov 515740ad9f7SMax Filippov static const XtfpgaFlashDesc lx200_flash = { 516740ad9f7SMax Filippov .base = 0x08000000, 517740ad9f7SMax Filippov .size = 0x01000000, 518740ad9f7SMax Filippov .sector_size = 0x20000, 519740ad9f7SMax Filippov }; 520740ad9f7SMax Filippov 521188ce01dSMax Filippov static void xtfpga_lx200_init(MachineState *machine) 522b707ab75SMax Filippov { 523188ce01dSMax Filippov static const XtfpgaBoardDesc lx200_board = { 524740ad9f7SMax Filippov .flash = &lx200_flash, 525b707ab75SMax Filippov .sram_size = 0x2000000, 52685e2d8d5SMax Filippov .io = xtfpga_mmu_io, 52785e2d8d5SMax Filippov }; 52885e2d8d5SMax Filippov xtfpga_init(&lx200_board, machine); 52985e2d8d5SMax Filippov } 53085e2d8d5SMax Filippov 53185e2d8d5SMax Filippov static void xtfpga_lx200_nommu_init(MachineState *machine) 53285e2d8d5SMax Filippov { 53385e2d8d5SMax Filippov static const XtfpgaBoardDesc lx200_board = { 53485e2d8d5SMax Filippov .flash = &lx200_flash, 53585e2d8d5SMax Filippov .sram_size = 0x2000000, 53685e2d8d5SMax Filippov .io = xtfpga_nommu_io, 537b707ab75SMax Filippov }; 538188ce01dSMax Filippov xtfpga_init(&lx200_board, machine); 539b707ab75SMax Filippov } 540b707ab75SMax Filippov 541740ad9f7SMax Filippov static const XtfpgaFlashDesc ml605_flash = { 542740ad9f7SMax Filippov .base = 0x08000000, 543740ad9f7SMax Filippov .size = 0x01000000, 544740ad9f7SMax Filippov .sector_size = 0x20000, 545740ad9f7SMax Filippov }; 546740ad9f7SMax Filippov 547188ce01dSMax Filippov static void xtfpga_ml605_init(MachineState *machine) 548b707ab75SMax Filippov { 549188ce01dSMax Filippov static const XtfpgaBoardDesc ml605_board = { 550740ad9f7SMax Filippov .flash = &ml605_flash, 551b707ab75SMax Filippov .sram_size = 0x2000000, 55285e2d8d5SMax Filippov .io = xtfpga_mmu_io, 55385e2d8d5SMax Filippov }; 55485e2d8d5SMax Filippov xtfpga_init(&ml605_board, machine); 55585e2d8d5SMax Filippov } 55685e2d8d5SMax Filippov 55785e2d8d5SMax Filippov static void xtfpga_ml605_nommu_init(MachineState *machine) 55885e2d8d5SMax Filippov { 55985e2d8d5SMax Filippov static const XtfpgaBoardDesc ml605_board = { 56085e2d8d5SMax Filippov .flash = &ml605_flash, 56185e2d8d5SMax Filippov .sram_size = 0x2000000, 56285e2d8d5SMax Filippov .io = xtfpga_nommu_io, 563b707ab75SMax Filippov }; 564188ce01dSMax Filippov xtfpga_init(&ml605_board, machine); 565b707ab75SMax Filippov } 566b707ab75SMax Filippov 567740ad9f7SMax Filippov static const XtfpgaFlashDesc kc705_flash = { 568740ad9f7SMax Filippov .base = 0x00000000, 569740ad9f7SMax Filippov .size = 0x08000000, 570740ad9f7SMax Filippov .boot_base = 0x06000000, 571740ad9f7SMax Filippov .sector_size = 0x20000, 572740ad9f7SMax Filippov }; 573740ad9f7SMax Filippov 574188ce01dSMax Filippov static void xtfpga_kc705_init(MachineState *machine) 575b707ab75SMax Filippov { 576188ce01dSMax Filippov static const XtfpgaBoardDesc kc705_board = { 577740ad9f7SMax Filippov .flash = &kc705_flash, 578b707ab75SMax Filippov .sram_size = 0x2000000, 57985e2d8d5SMax Filippov .io = xtfpga_mmu_io, 58085e2d8d5SMax Filippov }; 58185e2d8d5SMax Filippov xtfpga_init(&kc705_board, machine); 58285e2d8d5SMax Filippov } 58385e2d8d5SMax Filippov 58485e2d8d5SMax Filippov static void xtfpga_kc705_nommu_init(MachineState *machine) 58585e2d8d5SMax Filippov { 58685e2d8d5SMax Filippov static const XtfpgaBoardDesc kc705_board = { 58785e2d8d5SMax Filippov .flash = &kc705_flash, 58885e2d8d5SMax Filippov .sram_size = 0x2000000, 58985e2d8d5SMax Filippov .io = xtfpga_nommu_io, 590b707ab75SMax Filippov }; 591188ce01dSMax Filippov xtfpga_init(&kc705_board, machine); 592b707ab75SMax Filippov } 593b707ab75SMax Filippov 594188ce01dSMax Filippov static void xtfpga_lx60_class_init(ObjectClass *oc, void *data) 595b707ab75SMax Filippov { 5968a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 5978a661aeaSAndreas Färber 598e264d29dSEduardo Habkost mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 599188ce01dSMax Filippov mc->init = xtfpga_lx60_init; 600174e09b7SMax Filippov mc->max_cpus = 32; 601f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 60259b5e9bbSMax Filippov mc->default_ram_size = 64 * MiB; 603b707ab75SMax Filippov } 604b707ab75SMax Filippov 605188ce01dSMax Filippov static const TypeInfo xtfpga_lx60_type = { 6068a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lx60"), 6078a661aeaSAndreas Färber .parent = TYPE_MACHINE, 608188ce01dSMax Filippov .class_init = xtfpga_lx60_class_init, 6098a661aeaSAndreas Färber }; 610e264d29dSEduardo Habkost 61185e2d8d5SMax Filippov static void xtfpga_lx60_nommu_class_init(ObjectClass *oc, void *data) 61285e2d8d5SMax Filippov { 61385e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 61485e2d8d5SMax Filippov 615a3c5e49dSMax Filippov mc->desc = "lx60 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 61685e2d8d5SMax Filippov mc->init = xtfpga_lx60_nommu_init; 617174e09b7SMax Filippov mc->max_cpus = 32; 618a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 61959b5e9bbSMax Filippov mc->default_ram_size = 64 * MiB; 62085e2d8d5SMax Filippov } 62185e2d8d5SMax Filippov 62285e2d8d5SMax Filippov static const TypeInfo xtfpga_lx60_nommu_type = { 62385e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("lx60-nommu"), 62485e2d8d5SMax Filippov .parent = TYPE_MACHINE, 62585e2d8d5SMax Filippov .class_init = xtfpga_lx60_nommu_class_init, 62685e2d8d5SMax Filippov }; 62785e2d8d5SMax Filippov 628188ce01dSMax Filippov static void xtfpga_lx200_class_init(ObjectClass *oc, void *data) 629e264d29dSEduardo Habkost { 6308a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 6318a661aeaSAndreas Färber 632e264d29dSEduardo Habkost mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 633188ce01dSMax Filippov mc->init = xtfpga_lx200_init; 634174e09b7SMax Filippov mc->max_cpus = 32; 635f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 63659b5e9bbSMax Filippov mc->default_ram_size = 96 * MiB; 637e264d29dSEduardo Habkost } 638e264d29dSEduardo Habkost 639188ce01dSMax Filippov static const TypeInfo xtfpga_lx200_type = { 6408a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("lx200"), 6418a661aeaSAndreas Färber .parent = TYPE_MACHINE, 642188ce01dSMax Filippov .class_init = xtfpga_lx200_class_init, 6438a661aeaSAndreas Färber }; 644e264d29dSEduardo Habkost 64585e2d8d5SMax Filippov static void xtfpga_lx200_nommu_class_init(ObjectClass *oc, void *data) 64685e2d8d5SMax Filippov { 64785e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 64885e2d8d5SMax Filippov 649a3c5e49dSMax Filippov mc->desc = "lx200 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 65085e2d8d5SMax Filippov mc->init = xtfpga_lx200_nommu_init; 651174e09b7SMax Filippov mc->max_cpus = 32; 652a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 65359b5e9bbSMax Filippov mc->default_ram_size = 96 * MiB; 65485e2d8d5SMax Filippov } 65585e2d8d5SMax Filippov 65685e2d8d5SMax Filippov static const TypeInfo xtfpga_lx200_nommu_type = { 65785e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("lx200-nommu"), 65885e2d8d5SMax Filippov .parent = TYPE_MACHINE, 65985e2d8d5SMax Filippov .class_init = xtfpga_lx200_nommu_class_init, 66085e2d8d5SMax Filippov }; 66185e2d8d5SMax Filippov 662188ce01dSMax Filippov static void xtfpga_ml605_class_init(ObjectClass *oc, void *data) 663e264d29dSEduardo Habkost { 6648a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 6658a661aeaSAndreas Färber 666e264d29dSEduardo Habkost mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 667188ce01dSMax Filippov mc->init = xtfpga_ml605_init; 668174e09b7SMax Filippov mc->max_cpus = 32; 669f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 67059b5e9bbSMax Filippov mc->default_ram_size = 512 * MiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 671e264d29dSEduardo Habkost } 672e264d29dSEduardo Habkost 673188ce01dSMax Filippov static const TypeInfo xtfpga_ml605_type = { 6748a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("ml605"), 6758a661aeaSAndreas Färber .parent = TYPE_MACHINE, 676188ce01dSMax Filippov .class_init = xtfpga_ml605_class_init, 6778a661aeaSAndreas Färber }; 678e264d29dSEduardo Habkost 67985e2d8d5SMax Filippov static void xtfpga_ml605_nommu_class_init(ObjectClass *oc, void *data) 68085e2d8d5SMax Filippov { 68185e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 68285e2d8d5SMax Filippov 683a3c5e49dSMax Filippov mc->desc = "ml605 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 68485e2d8d5SMax Filippov mc->init = xtfpga_ml605_nommu_init; 685174e09b7SMax Filippov mc->max_cpus = 32; 686a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 68759b5e9bbSMax Filippov mc->default_ram_size = 256 * MiB; 68885e2d8d5SMax Filippov } 68985e2d8d5SMax Filippov 69085e2d8d5SMax Filippov static const TypeInfo xtfpga_ml605_nommu_type = { 69185e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("ml605-nommu"), 69285e2d8d5SMax Filippov .parent = TYPE_MACHINE, 69385e2d8d5SMax Filippov .class_init = xtfpga_ml605_nommu_class_init, 69485e2d8d5SMax Filippov }; 69585e2d8d5SMax Filippov 696188ce01dSMax Filippov static void xtfpga_kc705_class_init(ObjectClass *oc, void *data) 697e264d29dSEduardo Habkost { 6988a661aeaSAndreas Färber MachineClass *mc = MACHINE_CLASS(oc); 6998a661aeaSAndreas Färber 700e264d29dSEduardo Habkost mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")"; 701188ce01dSMax Filippov mc->init = xtfpga_kc705_init; 702174e09b7SMax Filippov mc->max_cpus = 32; 703f83eb10dSIgor Mammedov mc->default_cpu_type = XTENSA_DEFAULT_CPU_TYPE; 70459b5e9bbSMax Filippov mc->default_ram_size = 1 * GiB - XTFPGA_MMU_RESERVED_MEMORY_SIZE; 705e264d29dSEduardo Habkost } 706e264d29dSEduardo Habkost 707188ce01dSMax Filippov static const TypeInfo xtfpga_kc705_type = { 7088a661aeaSAndreas Färber .name = MACHINE_TYPE_NAME("kc705"), 7098a661aeaSAndreas Färber .parent = TYPE_MACHINE, 710188ce01dSMax Filippov .class_init = xtfpga_kc705_class_init, 7118a661aeaSAndreas Färber }; 7128a661aeaSAndreas Färber 71385e2d8d5SMax Filippov static void xtfpga_kc705_nommu_class_init(ObjectClass *oc, void *data) 71485e2d8d5SMax Filippov { 71585e2d8d5SMax Filippov MachineClass *mc = MACHINE_CLASS(oc); 71685e2d8d5SMax Filippov 717a3c5e49dSMax Filippov mc->desc = "kc705 noMMU EVB (" XTENSA_DEFAULT_CPU_NOMMU_MODEL ")"; 71885e2d8d5SMax Filippov mc->init = xtfpga_kc705_nommu_init; 719174e09b7SMax Filippov mc->max_cpus = 32; 720a3c5e49dSMax Filippov mc->default_cpu_type = XTENSA_DEFAULT_CPU_NOMMU_TYPE; 72159b5e9bbSMax Filippov mc->default_ram_size = 256 * MiB; 72285e2d8d5SMax Filippov } 72385e2d8d5SMax Filippov 72485e2d8d5SMax Filippov static const TypeInfo xtfpga_kc705_nommu_type = { 72585e2d8d5SMax Filippov .name = MACHINE_TYPE_NAME("kc705-nommu"), 72685e2d8d5SMax Filippov .parent = TYPE_MACHINE, 72785e2d8d5SMax Filippov .class_init = xtfpga_kc705_nommu_class_init, 72885e2d8d5SMax Filippov }; 72985e2d8d5SMax Filippov 730188ce01dSMax Filippov static void xtfpga_machines_init(void) 7318a661aeaSAndreas Färber { 732188ce01dSMax Filippov type_register_static(&xtfpga_lx60_type); 733188ce01dSMax Filippov type_register_static(&xtfpga_lx200_type); 734188ce01dSMax Filippov type_register_static(&xtfpga_ml605_type); 735188ce01dSMax Filippov type_register_static(&xtfpga_kc705_type); 73685e2d8d5SMax Filippov type_register_static(&xtfpga_lx60_nommu_type); 73785e2d8d5SMax Filippov type_register_static(&xtfpga_lx200_nommu_type); 73885e2d8d5SMax Filippov type_register_static(&xtfpga_ml605_nommu_type); 73985e2d8d5SMax Filippov type_register_static(&xtfpga_kc705_nommu_type); 7408a661aeaSAndreas Färber } 7418a661aeaSAndreas Färber 742188ce01dSMax Filippov type_init(xtfpga_machines_init) 743