1 /* 2 * defines common to all virtual CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_ALL_H 20 #define CPU_ALL_H 21 22 #include "exec/cpu-common.h" 23 #include "exec/memory.h" 24 #include "qemu/thread.h" 25 #include "hw/core/cpu.h" 26 #include "qemu/rcu.h" 27 28 #define EXCP_INTERRUPT 0x10000 /* async interruption */ 29 #define EXCP_HLT 0x10001 /* hlt instruction reached */ 30 #define EXCP_DEBUG 0x10002 /* cpu stopped after a breakpoint or singlestep */ 31 #define EXCP_HALTED 0x10003 /* cpu is halted (waiting for external event) */ 32 #define EXCP_YIELD 0x10004 /* cpu wants to yield timeslice to another */ 33 #define EXCP_ATOMIC 0x10005 /* stop-the-world and emulate atomic */ 34 35 /* some important defines: 36 * 37 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and 38 * otherwise little endian. 39 * 40 * TARGET_WORDS_BIGENDIAN : same for target cpu 41 */ 42 43 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) 44 #define BSWAP_NEEDED 45 #endif 46 47 #ifdef BSWAP_NEEDED 48 49 static inline uint16_t tswap16(uint16_t s) 50 { 51 return bswap16(s); 52 } 53 54 static inline uint32_t tswap32(uint32_t s) 55 { 56 return bswap32(s); 57 } 58 59 static inline uint64_t tswap64(uint64_t s) 60 { 61 return bswap64(s); 62 } 63 64 static inline void tswap16s(uint16_t *s) 65 { 66 *s = bswap16(*s); 67 } 68 69 static inline void tswap32s(uint32_t *s) 70 { 71 *s = bswap32(*s); 72 } 73 74 static inline void tswap64s(uint64_t *s) 75 { 76 *s = bswap64(*s); 77 } 78 79 #else 80 81 static inline uint16_t tswap16(uint16_t s) 82 { 83 return s; 84 } 85 86 static inline uint32_t tswap32(uint32_t s) 87 { 88 return s; 89 } 90 91 static inline uint64_t tswap64(uint64_t s) 92 { 93 return s; 94 } 95 96 static inline void tswap16s(uint16_t *s) 97 { 98 } 99 100 static inline void tswap32s(uint32_t *s) 101 { 102 } 103 104 static inline void tswap64s(uint64_t *s) 105 { 106 } 107 108 #endif 109 110 #if TARGET_LONG_SIZE == 4 111 #define tswapl(s) tswap32(s) 112 #define tswapls(s) tswap32s((uint32_t *)(s)) 113 #define bswaptls(s) bswap32s(s) 114 #else 115 #define tswapl(s) tswap64(s) 116 #define tswapls(s) tswap64s((uint64_t *)(s)) 117 #define bswaptls(s) bswap64s(s) 118 #endif 119 120 /* Target-endianness CPU memory access functions. These fit into the 121 * {ld,st}{type}{sign}{size}{endian}_p naming scheme described in bswap.h. 122 */ 123 #if defined(TARGET_WORDS_BIGENDIAN) 124 #define lduw_p(p) lduw_be_p(p) 125 #define ldsw_p(p) ldsw_be_p(p) 126 #define ldl_p(p) ldl_be_p(p) 127 #define ldq_p(p) ldq_be_p(p) 128 #define ldfl_p(p) ldfl_be_p(p) 129 #define ldfq_p(p) ldfq_be_p(p) 130 #define stw_p(p, v) stw_be_p(p, v) 131 #define stl_p(p, v) stl_be_p(p, v) 132 #define stq_p(p, v) stq_be_p(p, v) 133 #define stfl_p(p, v) stfl_be_p(p, v) 134 #define stfq_p(p, v) stfq_be_p(p, v) 135 #define ldn_p(p, sz) ldn_be_p(p, sz) 136 #define stn_p(p, sz, v) stn_be_p(p, sz, v) 137 #else 138 #define lduw_p(p) lduw_le_p(p) 139 #define ldsw_p(p) ldsw_le_p(p) 140 #define ldl_p(p) ldl_le_p(p) 141 #define ldq_p(p) ldq_le_p(p) 142 #define ldfl_p(p) ldfl_le_p(p) 143 #define ldfq_p(p) ldfq_le_p(p) 144 #define stw_p(p, v) stw_le_p(p, v) 145 #define stl_p(p, v) stl_le_p(p, v) 146 #define stq_p(p, v) stq_le_p(p, v) 147 #define stfl_p(p, v) stfl_le_p(p, v) 148 #define stfq_p(p, v) stfq_le_p(p, v) 149 #define ldn_p(p, sz) ldn_le_p(p, sz) 150 #define stn_p(p, sz, v) stn_le_p(p, sz, v) 151 #endif 152 153 /* MMU memory access macros */ 154 155 #if defined(CONFIG_USER_ONLY) 156 #include "exec/user/abitypes.h" 157 158 /* On some host systems the guest address space is reserved on the host. 159 * This allows the guest address space to be offset to a convenient location. 160 */ 161 extern unsigned long guest_base; 162 extern bool have_guest_base; 163 extern unsigned long reserved_va; 164 165 /* 166 * Limit the guest addresses as best we can. 167 * 168 * When not using -R reserved_va, we cannot really limit the guest 169 * to less address space than the host. For 32-bit guests, this 170 * acts as a sanity check that we're not giving the guest an address 171 * that it cannot even represent. For 64-bit guests... the address 172 * might not be what the real kernel would give, but it is at least 173 * representable in the guest. 174 * 175 * TODO: Improve address allocation to avoid this problem, and to 176 * avoid setting bits at the top of guest addresses that might need 177 * to be used for tags. 178 */ 179 #if MIN(TARGET_VIRT_ADDR_SPACE_BITS, TARGET_ABI_BITS) <= 32 180 # define GUEST_ADDR_MAX_ UINT32_MAX 181 #else 182 # define GUEST_ADDR_MAX_ (~0ul) 183 #endif 184 #define GUEST_ADDR_MAX (reserved_va ? reserved_va - 1 : GUEST_ADDR_MAX_) 185 186 #else 187 188 #include "exec/hwaddr.h" 189 190 #define SUFFIX 191 #define ARG1 as 192 #define ARG1_DECL AddressSpace *as 193 #define TARGET_ENDIANNESS 194 #include "exec/memory_ldst.inc.h" 195 196 #define SUFFIX _cached_slow 197 #define ARG1 cache 198 #define ARG1_DECL MemoryRegionCache *cache 199 #define TARGET_ENDIANNESS 200 #include "exec/memory_ldst.inc.h" 201 202 static inline void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val) 203 { 204 address_space_stl_notdirty(as, addr, val, 205 MEMTXATTRS_UNSPECIFIED, NULL); 206 } 207 208 #define SUFFIX 209 #define ARG1 as 210 #define ARG1_DECL AddressSpace *as 211 #define TARGET_ENDIANNESS 212 #include "exec/memory_ldst_phys.inc.h" 213 214 /* Inline fast path for direct RAM access. */ 215 #define ENDIANNESS 216 #include "exec/memory_ldst_cached.inc.h" 217 218 #define SUFFIX _cached 219 #define ARG1 cache 220 #define ARG1_DECL MemoryRegionCache *cache 221 #define TARGET_ENDIANNESS 222 #include "exec/memory_ldst_phys.inc.h" 223 #endif 224 225 /* page related stuff */ 226 227 #ifdef TARGET_PAGE_BITS_VARY 228 typedef struct { 229 bool decided; 230 int bits; 231 target_long mask; 232 } TargetPageBits; 233 #if defined(CONFIG_ATTRIBUTE_ALIAS) || !defined(IN_EXEC_VARY) 234 extern const TargetPageBits target_page; 235 #else 236 extern TargetPageBits target_page; 237 #endif 238 #ifdef CONFIG_DEBUG_TCG 239 #define TARGET_PAGE_BITS ({ assert(target_page.decided); target_page.bits; }) 240 #define TARGET_PAGE_MASK ({ assert(target_page.decided); target_page.mask; }) 241 #else 242 #define TARGET_PAGE_BITS target_page.bits 243 #define TARGET_PAGE_MASK target_page.mask 244 #endif 245 #define TARGET_PAGE_SIZE (-(int)TARGET_PAGE_MASK) 246 #else 247 #define TARGET_PAGE_BITS_MIN TARGET_PAGE_BITS 248 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS) 249 #define TARGET_PAGE_MASK ((target_long)-1 << TARGET_PAGE_BITS) 250 #endif 251 252 #define TARGET_PAGE_ALIGN(addr) ROUND_UP((addr), TARGET_PAGE_SIZE) 253 254 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 255 * when intptr_t is 32-bit and we are aligning a long long. 256 */ 257 extern uintptr_t qemu_host_page_size; 258 extern intptr_t qemu_host_page_mask; 259 260 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 261 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size) 262 263 /* same as PROT_xxx */ 264 #define PAGE_READ 0x0001 265 #define PAGE_WRITE 0x0002 266 #define PAGE_EXEC 0x0004 267 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC) 268 #define PAGE_VALID 0x0008 269 /* original state of the write flag (used when tracking self-modifying 270 code */ 271 #define PAGE_WRITE_ORG 0x0010 272 /* Invalidate the TLB entry immediately, helpful for s390x 273 * Low-Address-Protection. Used with PAGE_WRITE in tlb_set_page_with_attrs() */ 274 #define PAGE_WRITE_INV 0x0040 275 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) 276 /* FIXME: Code that sets/uses this is broken and needs to go away. */ 277 #define PAGE_RESERVED 0x0020 278 #endif 279 280 #if defined(CONFIG_USER_ONLY) 281 void page_dump(FILE *f); 282 283 typedef int (*walk_memory_regions_fn)(void *, target_ulong, 284 target_ulong, unsigned long); 285 int walk_memory_regions(void *, walk_memory_regions_fn); 286 287 int page_get_flags(target_ulong address); 288 void page_set_flags(target_ulong start, target_ulong end, int flags); 289 int page_check_range(target_ulong start, target_ulong len, int flags); 290 #endif 291 292 CPUArchState *cpu_copy(CPUArchState *env); 293 294 /* Flags for use in ENV->INTERRUPT_PENDING. 295 296 The numbers assigned here are non-sequential in order to preserve 297 binary compatibility with the vmstate dump. Bit 0 (0x0001) was 298 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading 299 the vmstate dump. */ 300 301 /* External hardware interrupt pending. This is typically used for 302 interrupts from devices. */ 303 #define CPU_INTERRUPT_HARD 0x0002 304 305 /* Exit the current TB. This is typically used when some system-level device 306 makes some change to the memory mapping. E.g. the a20 line change. */ 307 #define CPU_INTERRUPT_EXITTB 0x0004 308 309 /* Halt the CPU. */ 310 #define CPU_INTERRUPT_HALT 0x0020 311 312 /* Debug event pending. */ 313 #define CPU_INTERRUPT_DEBUG 0x0080 314 315 /* Reset signal. */ 316 #define CPU_INTERRUPT_RESET 0x0400 317 318 /* Several target-specific external hardware interrupts. Each target/cpu.h 319 should define proper names based on these defines. */ 320 #define CPU_INTERRUPT_TGT_EXT_0 0x0008 321 #define CPU_INTERRUPT_TGT_EXT_1 0x0010 322 #define CPU_INTERRUPT_TGT_EXT_2 0x0040 323 #define CPU_INTERRUPT_TGT_EXT_3 0x0200 324 #define CPU_INTERRUPT_TGT_EXT_4 0x1000 325 326 /* Several target-specific internal interrupts. These differ from the 327 preceding target-specific interrupts in that they are intended to 328 originate from within the cpu itself, typically in response to some 329 instruction being executed. These, therefore, are not masked while 330 single-stepping within the debugger. */ 331 #define CPU_INTERRUPT_TGT_INT_0 0x0100 332 #define CPU_INTERRUPT_TGT_INT_1 0x0800 333 #define CPU_INTERRUPT_TGT_INT_2 0x2000 334 335 /* First unused bit: 0x4000. */ 336 337 /* The set of all bits that should be masked when single-stepping. */ 338 #define CPU_INTERRUPT_SSTEP_MASK \ 339 (CPU_INTERRUPT_HARD \ 340 | CPU_INTERRUPT_TGT_EXT_0 \ 341 | CPU_INTERRUPT_TGT_EXT_1 \ 342 | CPU_INTERRUPT_TGT_EXT_2 \ 343 | CPU_INTERRUPT_TGT_EXT_3 \ 344 | CPU_INTERRUPT_TGT_EXT_4) 345 346 #ifdef CONFIG_USER_ONLY 347 348 /* 349 * Allow some level of source compatibility with softmmu. We do not 350 * support any of the more exotic features, so only invalid pages may 351 * be signaled by probe_access_flags(). 352 */ 353 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 354 #define TLB_MMIO 0 355 #define TLB_WATCHPOINT 0 356 357 #else 358 359 /* 360 * Flags stored in the low bits of the TLB virtual address. 361 * These are defined so that fast path ram access is all zeros. 362 * The flags all must be between TARGET_PAGE_BITS and 363 * maximum address alignment bit. 364 * 365 * Use TARGET_PAGE_BITS_MIN so that these bits are constant 366 * when TARGET_PAGE_BITS_VARY is in effect. 367 */ 368 /* Zero if TLB entry is valid. */ 369 #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) 370 /* Set if TLB entry references a clean RAM page. The iotlb entry will 371 contain the page physical address. */ 372 #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) 373 /* Set if TLB entry is an IO callback. */ 374 #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) 375 /* Set if TLB entry contains a watchpoint. */ 376 #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) 377 /* Set if TLB entry requires byte swap. */ 378 #define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) 379 /* Set if TLB entry writes ignored. */ 380 #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) 381 382 /* Use this mask to check interception with an alignment mask 383 * in a TCG backend. 384 */ 385 #define TLB_FLAGS_MASK \ 386 (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ 387 | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) 388 389 /** 390 * tlb_hit_page: return true if page aligned @addr is a hit against the 391 * TLB entry @tlb_addr 392 * 393 * @addr: virtual address to test (must be page aligned) 394 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 395 */ 396 static inline bool tlb_hit_page(target_ulong tlb_addr, target_ulong addr) 397 { 398 return addr == (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK)); 399 } 400 401 /** 402 * tlb_hit: return true if @addr is a hit against the TLB entry @tlb_addr 403 * 404 * @addr: virtual address to test (need not be page aligned) 405 * @tlb_addr: TLB entry address (a CPUTLBEntry addr_read/write/code value) 406 */ 407 static inline bool tlb_hit(target_ulong tlb_addr, target_ulong addr) 408 { 409 return tlb_hit_page(tlb_addr, addr & TARGET_PAGE_MASK); 410 } 411 412 void dump_exec_info(void); 413 void dump_opcount_info(void); 414 #endif /* !CONFIG_USER_ONLY */ 415 416 int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, 417 void *ptr, target_ulong len, bool is_write); 418 419 int cpu_exec(CPUState *cpu); 420 421 /** 422 * cpu_set_cpustate_pointers(cpu) 423 * @cpu: The cpu object 424 * 425 * Set the generic pointers in CPUState into the outer object. 426 */ 427 static inline void cpu_set_cpustate_pointers(ArchCPU *cpu) 428 { 429 cpu->parent_obj.env_ptr = &cpu->env; 430 cpu->parent_obj.icount_decr_ptr = &cpu->neg.icount_decr; 431 } 432 433 /** 434 * env_archcpu(env) 435 * @env: The architecture environment 436 * 437 * Return the ArchCPU associated with the environment. 438 */ 439 static inline ArchCPU *env_archcpu(CPUArchState *env) 440 { 441 return container_of(env, ArchCPU, env); 442 } 443 444 /** 445 * env_cpu(env) 446 * @env: The architecture environment 447 * 448 * Return the CPUState associated with the environment. 449 */ 450 static inline CPUState *env_cpu(CPUArchState *env) 451 { 452 return &env_archcpu(env)->parent_obj; 453 } 454 455 /** 456 * env_neg(env) 457 * @env: The architecture environment 458 * 459 * Return the CPUNegativeOffsetState associated with the environment. 460 */ 461 static inline CPUNegativeOffsetState *env_neg(CPUArchState *env) 462 { 463 ArchCPU *arch_cpu = container_of(env, ArchCPU, env); 464 return &arch_cpu->neg; 465 } 466 467 /** 468 * cpu_neg(cpu) 469 * @cpu: The generic CPUState 470 * 471 * Return the CPUNegativeOffsetState associated with the cpu. 472 */ 473 static inline CPUNegativeOffsetState *cpu_neg(CPUState *cpu) 474 { 475 ArchCPU *arch_cpu = container_of(cpu, ArchCPU, parent_obj); 476 return &arch_cpu->neg; 477 } 478 479 /** 480 * env_tlb(env) 481 * @env: The architecture environment 482 * 483 * Return the CPUTLB state associated with the environment. 484 */ 485 static inline CPUTLB *env_tlb(CPUArchState *env) 486 { 487 return &env_neg(env)->tlb; 488 } 489 490 #endif /* CPU_ALL_H */ 491