1 #ifndef CPU_COMMON_H 2 #define CPU_COMMON_H 3 4 /* CPU interfaces that are target independent. */ 5 6 #ifndef CONFIG_USER_ONLY 7 #include "exec/hwaddr.h" 8 #endif 9 10 /** 11 * vaddr: 12 * Type wide enough to contain any #target_ulong virtual address. 13 */ 14 typedef uint64_t vaddr; 15 #define VADDR_PRId PRId64 16 #define VADDR_PRIu PRIu64 17 #define VADDR_PRIo PRIo64 18 #define VADDR_PRIx PRIx64 19 #define VADDR_PRIX PRIX64 20 #define VADDR_MAX UINT64_MAX 21 22 /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even 23 * when intptr_t is 32-bit and we are aligning a long long. 24 */ 25 extern uintptr_t qemu_host_page_size; 26 extern intptr_t qemu_host_page_mask; 27 28 #define HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_host_page_size) 29 #define REAL_HOST_PAGE_ALIGN(addr) ROUND_UP((addr), qemu_real_host_page_size) 30 31 /* The CPU list lock nests outside page_(un)lock or mmap_(un)lock */ 32 void qemu_init_cpu_list(void); 33 void cpu_list_lock(void); 34 void cpu_list_unlock(void); 35 36 void tcg_flush_softmmu_tlb(CPUState *cs); 37 38 void tcg_iommu_init_notifier_list(CPUState *cpu); 39 void tcg_iommu_free_notifier_list(CPUState *cpu); 40 41 #if !defined(CONFIG_USER_ONLY) 42 43 enum device_endian { 44 DEVICE_NATIVE_ENDIAN, 45 DEVICE_BIG_ENDIAN, 46 DEVICE_LITTLE_ENDIAN, 47 }; 48 49 #if HOST_BIG_ENDIAN 50 #define DEVICE_HOST_ENDIAN DEVICE_BIG_ENDIAN 51 #else 52 #define DEVICE_HOST_ENDIAN DEVICE_LITTLE_ENDIAN 53 #endif 54 55 /* address in the RAM (different from a physical address) */ 56 #if defined(CONFIG_XEN_BACKEND) 57 typedef uint64_t ram_addr_t; 58 # define RAM_ADDR_MAX UINT64_MAX 59 # define RAM_ADDR_FMT "%" PRIx64 60 #else 61 typedef uintptr_t ram_addr_t; 62 # define RAM_ADDR_MAX UINTPTR_MAX 63 # define RAM_ADDR_FMT "%" PRIxPTR 64 #endif 65 66 /* memory API */ 67 68 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length); 69 /* This should not be used by devices. */ 70 ram_addr_t qemu_ram_addr_from_host(void *ptr); 71 RAMBlock *qemu_ram_block_by_name(const char *name); 72 RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset, 73 ram_addr_t *offset); 74 ram_addr_t qemu_ram_block_host_offset(RAMBlock *rb, void *host); 75 void qemu_ram_set_idstr(RAMBlock *block, const char *name, DeviceState *dev); 76 void qemu_ram_unset_idstr(RAMBlock *block); 77 const char *qemu_ram_get_idstr(RAMBlock *rb); 78 void *qemu_ram_get_host_addr(RAMBlock *rb); 79 ram_addr_t qemu_ram_get_offset(RAMBlock *rb); 80 ram_addr_t qemu_ram_get_used_length(RAMBlock *rb); 81 ram_addr_t qemu_ram_get_max_length(RAMBlock *rb); 82 bool qemu_ram_is_shared(RAMBlock *rb); 83 bool qemu_ram_is_noreserve(RAMBlock *rb); 84 bool qemu_ram_is_uf_zeroable(RAMBlock *rb); 85 void qemu_ram_set_uf_zeroable(RAMBlock *rb); 86 bool qemu_ram_is_migratable(RAMBlock *rb); 87 void qemu_ram_set_migratable(RAMBlock *rb); 88 void qemu_ram_unset_migratable(RAMBlock *rb); 89 90 size_t qemu_ram_pagesize(RAMBlock *block); 91 size_t qemu_ram_pagesize_largest(void); 92 93 /** 94 * cpu_address_space_init: 95 * @cpu: CPU to add this address space to 96 * @asidx: integer index of this address space 97 * @prefix: prefix to be used as name of address space 98 * @mr: the root memory region of address space 99 * 100 * Add the specified address space to the CPU's cpu_ases list. 101 * The address space added with @asidx 0 is the one used for the 102 * convenience pointer cpu->as. 103 * The target-specific code which registers ASes is responsible 104 * for defining what semantics address space 0, 1, 2, etc have. 105 * 106 * Before the first call to this function, the caller must set 107 * cpu->num_ases to the total number of address spaces it needs 108 * to support. 109 * 110 * Note that with KVM only one address space is supported. 111 */ 112 void cpu_address_space_init(CPUState *cpu, int asidx, 113 const char *prefix, MemoryRegion *mr); 114 115 void cpu_physical_memory_rw(hwaddr addr, void *buf, 116 hwaddr len, bool is_write); 117 static inline void cpu_physical_memory_read(hwaddr addr, 118 void *buf, hwaddr len) 119 { 120 cpu_physical_memory_rw(addr, buf, len, false); 121 } 122 static inline void cpu_physical_memory_write(hwaddr addr, 123 const void *buf, hwaddr len) 124 { 125 cpu_physical_memory_rw(addr, (void *)buf, len, true); 126 } 127 void cpu_reloading_memory_map(void); 128 void *cpu_physical_memory_map(hwaddr addr, 129 hwaddr *plen, 130 bool is_write); 131 void cpu_physical_memory_unmap(void *buffer, hwaddr len, 132 bool is_write, hwaddr access_len); 133 void cpu_register_map_client(QEMUBH *bh); 134 void cpu_unregister_map_client(QEMUBH *bh); 135 136 bool cpu_physical_memory_is_io(hwaddr phys_addr); 137 138 /* Coalesced MMIO regions are areas where write operations can be reordered. 139 * This usually implies that write operations are side-effect free. This allows 140 * batching which can make a major impact on performance when using 141 * virtualization. 142 */ 143 void qemu_flush_coalesced_mmio_buffer(void); 144 145 void cpu_flush_icache_range(hwaddr start, hwaddr len); 146 147 typedef int (RAMBlockIterFunc)(RAMBlock *rb, void *opaque); 148 149 int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque); 150 int ram_block_discard_range(RAMBlock *rb, uint64_t start, size_t length); 151 152 #endif 153 154 /* Returns: 0 on success, -1 on error */ 155 int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, 156 void *ptr, size_t len, bool is_write); 157 158 /* vl.c */ 159 extern int singlestep; 160 161 void list_cpus(const char *optarg); 162 163 #endif /* CPU_COMMON_H */ 164