1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #include "qemu/queue.h" 29 #ifdef CONFIG_TCG 30 #include "tcg-target.h" 31 #endif 32 #ifndef CONFIG_USER_ONLY 33 #include "exec/hwaddr.h" 34 #endif 35 #include "exec/memattrs.h" 36 #include "qom/cpu.h" 37 38 #include "cpu-param.h" 39 40 #ifndef TARGET_LONG_BITS 41 # error TARGET_LONG_BITS must be defined in cpu-param.h 42 #endif 43 #ifndef NB_MMU_MODES 44 # error NB_MMU_MODES must be defined in cpu-param.h 45 #endif 46 #ifndef TARGET_PHYS_ADDR_SPACE_BITS 47 # error TARGET_PHYS_ADDR_SPACE_BITS must be defined in cpu-param.h 48 #endif 49 #ifndef TARGET_VIRT_ADDR_SPACE_BITS 50 # error TARGET_VIRT_ADDR_SPACE_BITS must be defined in cpu-param.h 51 #endif 52 #ifndef TARGET_PAGE_BITS 53 # ifdef TARGET_PAGE_BITS_VARY 54 # ifndef TARGET_PAGE_BITS_MIN 55 # error TARGET_PAGE_BITS_MIN must be defined in cpu-param.h 56 # endif 57 # else 58 # error TARGET_PAGE_BITS must be defined in cpu-param.h 59 # endif 60 #endif 61 62 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 63 64 /* target_ulong is the type of a virtual address */ 65 #if TARGET_LONG_SIZE == 4 66 typedef int32_t target_long; 67 typedef uint32_t target_ulong; 68 #define TARGET_FMT_lx "%08x" 69 #define TARGET_FMT_ld "%d" 70 #define TARGET_FMT_lu "%u" 71 #elif TARGET_LONG_SIZE == 8 72 typedef int64_t target_long; 73 typedef uint64_t target_ulong; 74 #define TARGET_FMT_lx "%016" PRIx64 75 #define TARGET_FMT_ld "%" PRId64 76 #define TARGET_FMT_lu "%" PRIu64 77 #else 78 #error TARGET_LONG_SIZE undefined 79 #endif 80 81 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 82 83 /* use a fully associative victim tlb of 8 entries */ 84 #define CPU_VTLB_SIZE 8 85 86 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 87 #define CPU_TLB_ENTRY_BITS 4 88 #else 89 #define CPU_TLB_ENTRY_BITS 5 90 #endif 91 92 #define CPU_TLB_DYN_MIN_BITS 6 93 #define CPU_TLB_DYN_DEFAULT_BITS 8 94 95 # if HOST_LONG_BITS == 32 96 /* Make sure we do not require a double-word shift for the TLB load */ 97 # define CPU_TLB_DYN_MAX_BITS (32 - TARGET_PAGE_BITS) 98 # else /* HOST_LONG_BITS == 64 */ 99 /* 100 * Assuming TARGET_PAGE_BITS==12, with 2**22 entries we can cover 2**(22+12) == 101 * 2**34 == 16G of address space. This is roughly what one would expect a 102 * TLB to cover in a modern (as of 2018) x86_64 CPU. For instance, Intel 103 * Skylake's Level-2 STLB has 16 1G entries. 104 * Also, make sure we do not size the TLB past the guest's address space. 105 */ 106 # define CPU_TLB_DYN_MAX_BITS \ 107 MIN(22, TARGET_VIRT_ADDR_SPACE_BITS - TARGET_PAGE_BITS) 108 # endif 109 110 typedef struct CPUTLBEntry { 111 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 112 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 113 go directly to ram. 114 bit 3 : indicates that the entry is invalid 115 bit 2..0 : zero 116 */ 117 union { 118 struct { 119 target_ulong addr_read; 120 target_ulong addr_write; 121 target_ulong addr_code; 122 /* Addend to virtual address to get host address. IO accesses 123 use the corresponding iotlb value. */ 124 uintptr_t addend; 125 }; 126 /* padding to get a power of two size */ 127 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 128 }; 129 } CPUTLBEntry; 130 131 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 132 133 /* The IOTLB is not accessed directly inline by generated TCG code, 134 * so the CPUIOTLBEntry layout is not as critical as that of the 135 * CPUTLBEntry. (This is also why we don't want to combine the two 136 * structs into one.) 137 */ 138 typedef struct CPUIOTLBEntry { 139 /* 140 * @addr contains: 141 * - in the lower TARGET_PAGE_BITS, a physical section number 142 * - with the lower TARGET_PAGE_BITS masked off, an offset which 143 * must be added to the virtual address to obtain: 144 * + the ram_addr_t of the target RAM (if the physical section 145 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 146 * + the offset within the target MemoryRegion (otherwise) 147 */ 148 hwaddr addr; 149 MemTxAttrs attrs; 150 } CPUIOTLBEntry; 151 152 /* 153 * Data elements that are per MMU mode, minus the bits accessed by 154 * the TCG fast path. 155 */ 156 typedef struct CPUTLBDesc { 157 /* 158 * Describe a region covering all of the large pages allocated 159 * into the tlb. When any page within this region is flushed, 160 * we must flush the entire tlb. The region is matched if 161 * (addr & large_page_mask) == large_page_addr. 162 */ 163 target_ulong large_page_addr; 164 target_ulong large_page_mask; 165 /* host time (in ns) at the beginning of the time window */ 166 int64_t window_begin_ns; 167 /* maximum number of entries observed in the window */ 168 size_t window_max_entries; 169 size_t n_used_entries; 170 /* The next index to use in the tlb victim table. */ 171 size_t vindex; 172 /* The tlb victim table, in two parts. */ 173 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 174 CPUIOTLBEntry viotlb[CPU_VTLB_SIZE]; 175 /* The iotlb. */ 176 CPUIOTLBEntry *iotlb; 177 } CPUTLBDesc; 178 179 /* 180 * Data elements that are per MMU mode, accessed by the fast path. 181 * The structure is aligned to aid loading the pair with one insn. 182 */ 183 typedef struct CPUTLBDescFast { 184 /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ 185 uintptr_t mask; 186 /* The array of tlb entries itself. */ 187 CPUTLBEntry *table; 188 } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); 189 190 /* 191 * Data elements that are shared between all MMU modes. 192 */ 193 typedef struct CPUTLBCommon { 194 /* Serialize updates to f.table and d.vtable, and others as noted. */ 195 QemuSpin lock; 196 /* 197 * Within dirty, for each bit N, modifications have been made to 198 * mmu_idx N since the last time that mmu_idx was flushed. 199 * Protected by tlb_c.lock. 200 */ 201 uint16_t dirty; 202 /* 203 * Statistics. These are not lock protected, but are read and 204 * written atomically. This allows the monitor to print a snapshot 205 * of the stats without interfering with the cpu. 206 */ 207 size_t full_flush_count; 208 size_t part_flush_count; 209 size_t elide_flush_count; 210 } CPUTLBCommon; 211 212 /* 213 * The entire softmmu tlb, for all MMU modes. 214 * The meaning of each of the MMU modes is defined in the target code. 215 * Since this is placed within CPUNegativeOffsetState, the smallest 216 * negative offsets are at the end of the struct. 217 */ 218 typedef struct CPUTLB { 219 CPUTLBCommon c; 220 CPUTLBDesc d[NB_MMU_MODES]; 221 CPUTLBDescFast f[NB_MMU_MODES]; 222 } CPUTLB; 223 224 /* This will be used by TCG backends to compute offsets. */ 225 #define TLB_MASK_TABLE_OFS(IDX) \ 226 ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) 227 228 #else 229 230 typedef struct CPUTLB { } CPUTLB; 231 232 #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ 233 234 /* 235 * This structure must be placed in ArchCPU immedately 236 * before CPUArchState, as a field named "neg". 237 */ 238 typedef struct CPUNegativeOffsetState { 239 CPUTLB tlb; 240 IcountDecr icount_decr; 241 } CPUNegativeOffsetState; 242 243 #endif 244