1 /* 2 * common defines for all CPUs 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 #ifndef CPU_DEFS_H 20 #define CPU_DEFS_H 21 22 #ifndef NEED_CPU_H 23 #error cpu.h included from common code 24 #endif 25 26 #include "qemu/host-utils.h" 27 #include "qemu/thread.h" 28 #include "qemu/queue.h" 29 #ifdef CONFIG_TCG 30 #include "tcg-target.h" 31 #endif 32 #ifndef CONFIG_USER_ONLY 33 #include "exec/hwaddr.h" 34 #endif 35 #include "exec/memattrs.h" 36 37 #ifndef TARGET_LONG_BITS 38 #error TARGET_LONG_BITS must be defined before including this header 39 #endif 40 41 #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) 42 43 /* target_ulong is the type of a virtual address */ 44 #if TARGET_LONG_SIZE == 4 45 typedef int32_t target_long; 46 typedef uint32_t target_ulong; 47 #define TARGET_FMT_lx "%08x" 48 #define TARGET_FMT_ld "%d" 49 #define TARGET_FMT_lu "%u" 50 #elif TARGET_LONG_SIZE == 8 51 typedef int64_t target_long; 52 typedef uint64_t target_ulong; 53 #define TARGET_FMT_lx "%016" PRIx64 54 #define TARGET_FMT_ld "%" PRId64 55 #define TARGET_FMT_lu "%" PRIu64 56 #else 57 #error TARGET_LONG_SIZE undefined 58 #endif 59 60 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 61 /* use a fully associative victim tlb of 8 entries */ 62 #define CPU_VTLB_SIZE 8 63 64 #if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 65 #define CPU_TLB_ENTRY_BITS 4 66 #else 67 #define CPU_TLB_ENTRY_BITS 5 68 #endif 69 70 /* TCG_TARGET_TLB_DISPLACEMENT_BITS is used in CPU_TLB_BITS to ensure that 71 * the TLB is not unnecessarily small, but still small enough for the 72 * TLB lookup instruction sequence used by the TCG target. 73 * 74 * TCG will have to generate an operand as large as the distance between 75 * env and the tlb_table[NB_MMU_MODES - 1][0].addend. For simplicity, 76 * the TCG targets just round everything up to the next power of two, and 77 * count bits. This works because: 1) the size of each TLB is a largish 78 * power of two, 2) and because the limit of the displacement is really close 79 * to a power of two, 3) the offset of tlb_table[0][0] inside env is smaller 80 * than the size of a TLB. 81 * 82 * For example, the maximum displacement 0xFFF0 on PPC and MIPS, but TCG 83 * just says "the displacement is 16 bits". TCG_TARGET_TLB_DISPLACEMENT_BITS 84 * then ensures that tlb_table at least 0x8000 bytes large ("not unnecessarily 85 * small": 2^15). The operand then will come up smaller than 0xFFF0 without 86 * any particular care, because the TLB for a single MMU mode is larger than 87 * 0x10000-0xFFF0=16 bytes. In the end, the maximum value of the operand 88 * could be something like 0xC000 (the offset of the last TLB table) plus 89 * 0x18 (the offset of the addend field in each TLB entry) plus the offset 90 * of tlb_table inside env (which is non-trivial but not huge). 91 */ 92 #define CPU_TLB_BITS \ 93 MIN(8, \ 94 TCG_TARGET_TLB_DISPLACEMENT_BITS - CPU_TLB_ENTRY_BITS - \ 95 (NB_MMU_MODES <= 1 ? 0 : \ 96 NB_MMU_MODES <= 2 ? 1 : \ 97 NB_MMU_MODES <= 4 ? 2 : \ 98 NB_MMU_MODES <= 8 ? 3 : 4)) 99 100 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) 101 102 typedef struct CPUTLBEntry { 103 /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address 104 bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not 105 go directly to ram. 106 bit 3 : indicates that the entry is invalid 107 bit 2..0 : zero 108 */ 109 union { 110 struct { 111 target_ulong addr_read; 112 target_ulong addr_write; 113 target_ulong addr_code; 114 /* Addend to virtual address to get host address. IO accesses 115 use the corresponding iotlb value. */ 116 uintptr_t addend; 117 }; 118 /* padding to get a power of two size */ 119 uint8_t dummy[1 << CPU_TLB_ENTRY_BITS]; 120 }; 121 } CPUTLBEntry; 122 123 QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); 124 125 /* The IOTLB is not accessed directly inline by generated TCG code, 126 * so the CPUIOTLBEntry layout is not as critical as that of the 127 * CPUTLBEntry. (This is also why we don't want to combine the two 128 * structs into one.) 129 */ 130 typedef struct CPUIOTLBEntry { 131 /* 132 * @addr contains: 133 * - in the lower TARGET_PAGE_BITS, a physical section number 134 * - with the lower TARGET_PAGE_BITS masked off, an offset which 135 * must be added to the virtual address to obtain: 136 * + the ram_addr_t of the target RAM (if the physical section 137 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 138 * + the offset within the target MemoryRegion (otherwise) 139 */ 140 hwaddr addr; 141 MemTxAttrs attrs; 142 } CPUIOTLBEntry; 143 144 #define CPU_COMMON_TLB \ 145 /* The meaning of the MMU modes is defined in the target code. */ \ 146 /* tlb_lock serializes updates to tlb_table and tlb_v_table */ \ 147 QemuSpin tlb_lock; \ 148 CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ 149 CPUTLBEntry tlb_v_table[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 150 CPUIOTLBEntry iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ 151 CPUIOTLBEntry iotlb_v[NB_MMU_MODES][CPU_VTLB_SIZE]; \ 152 size_t tlb_flush_count; \ 153 target_ulong tlb_flush_addr; \ 154 target_ulong tlb_flush_mask; \ 155 target_ulong vtlb_index; \ 156 157 #else 158 159 #define CPU_COMMON_TLB 160 161 #endif 162 163 164 #define CPU_COMMON \ 165 /* soft mmu support */ \ 166 CPU_COMMON_TLB \ 167 168 #endif 169