1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2.1 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef EXEC_ALL_H 21 #define EXEC_ALL_H 22 23 #include "cpu.h" 24 #ifdef CONFIG_TCG 25 #include "exec/cpu_ldst.h" 26 #endif 27 #include "qemu/interval-tree.h" 28 #include "qemu/clang-tsa.h" 29 30 /* Page tracking code uses ram addresses in system mode, and virtual 31 addresses in userspace mode. Define tb_page_addr_t to be an appropriate 32 type. */ 33 #if defined(CONFIG_USER_ONLY) 34 typedef abi_ulong tb_page_addr_t; 35 #define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx 36 #else 37 typedef ram_addr_t tb_page_addr_t; 38 #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT 39 #endif 40 41 /** 42 * cpu_unwind_state_data: 43 * @cpu: the cpu context 44 * @host_pc: the host pc within the translation 45 * @data: output data 46 * 47 * Attempt to load the the unwind state for a host pc occurring in 48 * translated code. If @host_pc is not in translated code, the 49 * function returns false; otherwise @data is loaded. 50 * This is the same unwind info as given to restore_state_to_opc. 51 */ 52 bool cpu_unwind_state_data(CPUState *cpu, uintptr_t host_pc, uint64_t *data); 53 54 /** 55 * cpu_restore_state: 56 * @cpu: the cpu context 57 * @host_pc: the host pc within the translation 58 * @return: true if state was restored, false otherwise 59 * 60 * Attempt to restore the state for a fault occurring in translated 61 * code. If @host_pc is not in translated code no state is 62 * restored and the function returns false. 63 */ 64 bool cpu_restore_state(CPUState *cpu, uintptr_t host_pc); 65 66 G_NORETURN void cpu_loop_exit_noexc(CPUState *cpu); 67 G_NORETURN void cpu_loop_exit(CPUState *cpu); 68 G_NORETURN void cpu_loop_exit_restore(CPUState *cpu, uintptr_t pc); 69 G_NORETURN void cpu_loop_exit_atomic(CPUState *cpu, uintptr_t pc); 70 71 /** 72 * cpu_loop_exit_requested: 73 * @cpu: The CPU state to be tested 74 * 75 * Indicate if somebody asked for a return of the CPU to the main loop 76 * (e.g., via cpu_exit() or cpu_interrupt()). 77 * 78 * This is helpful for architectures that support interruptible 79 * instructions. After writing back all state to registers/memory, this 80 * call can be used to check if it makes sense to return to the main loop 81 * or to continue executing the interruptible instruction. 82 */ 83 static inline bool cpu_loop_exit_requested(CPUState *cpu) 84 { 85 return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0; 86 } 87 88 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) 89 /* cputlb.c */ 90 /** 91 * tlb_init - initialize a CPU's TLB 92 * @cpu: CPU whose TLB should be initialized 93 */ 94 void tlb_init(CPUState *cpu); 95 /** 96 * tlb_destroy - destroy a CPU's TLB 97 * @cpu: CPU whose TLB should be destroyed 98 */ 99 void tlb_destroy(CPUState *cpu); 100 /** 101 * tlb_flush_page: 102 * @cpu: CPU whose TLB should be flushed 103 * @addr: virtual address of page to be flushed 104 * 105 * Flush one page from the TLB of the specified CPU, for all 106 * MMU indexes. 107 */ 108 void tlb_flush_page(CPUState *cpu, target_ulong addr); 109 /** 110 * tlb_flush_page_all_cpus: 111 * @cpu: src CPU of the flush 112 * @addr: virtual address of page to be flushed 113 * 114 * Flush one page from the TLB of the specified CPU, for all 115 * MMU indexes. 116 */ 117 void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr); 118 /** 119 * tlb_flush_page_all_cpus_synced: 120 * @cpu: src CPU of the flush 121 * @addr: virtual address of page to be flushed 122 * 123 * Flush one page from the TLB of the specified CPU, for all MMU 124 * indexes like tlb_flush_page_all_cpus except the source vCPUs work 125 * is scheduled as safe work meaning all flushes will be complete once 126 * the source vCPUs safe work is complete. This will depend on when 127 * the guests translation ends the TB. 128 */ 129 void tlb_flush_page_all_cpus_synced(CPUState *src, target_ulong addr); 130 /** 131 * tlb_flush: 132 * @cpu: CPU whose TLB should be flushed 133 * 134 * Flush the entire TLB for the specified CPU. Most CPU architectures 135 * allow the implementation to drop entries from the TLB at any time 136 * so this is generally safe. If more selective flushing is required 137 * use one of the other functions for efficiency. 138 */ 139 void tlb_flush(CPUState *cpu); 140 /** 141 * tlb_flush_all_cpus: 142 * @cpu: src CPU of the flush 143 */ 144 void tlb_flush_all_cpus(CPUState *src_cpu); 145 /** 146 * tlb_flush_all_cpus_synced: 147 * @cpu: src CPU of the flush 148 * 149 * Like tlb_flush_all_cpus except this except the source vCPUs work is 150 * scheduled as safe work meaning all flushes will be complete once 151 * the source vCPUs safe work is complete. This will depend on when 152 * the guests translation ends the TB. 153 */ 154 void tlb_flush_all_cpus_synced(CPUState *src_cpu); 155 /** 156 * tlb_flush_page_by_mmuidx: 157 * @cpu: CPU whose TLB should be flushed 158 * @addr: virtual address of page to be flushed 159 * @idxmap: bitmap of MMU indexes to flush 160 * 161 * Flush one page from the TLB of the specified CPU, for the specified 162 * MMU indexes. 163 */ 164 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, 165 uint16_t idxmap); 166 /** 167 * tlb_flush_page_by_mmuidx_all_cpus: 168 * @cpu: Originating CPU of the flush 169 * @addr: virtual address of page to be flushed 170 * @idxmap: bitmap of MMU indexes to flush 171 * 172 * Flush one page from the TLB of all CPUs, for the specified 173 * MMU indexes. 174 */ 175 void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 176 uint16_t idxmap); 177 /** 178 * tlb_flush_page_by_mmuidx_all_cpus_synced: 179 * @cpu: Originating CPU of the flush 180 * @addr: virtual address of page to be flushed 181 * @idxmap: bitmap of MMU indexes to flush 182 * 183 * Flush one page from the TLB of all CPUs, for the specified MMU 184 * indexes like tlb_flush_page_by_mmuidx_all_cpus except the source 185 * vCPUs work is scheduled as safe work meaning all flushes will be 186 * complete once the source vCPUs safe work is complete. This will 187 * depend on when the guests translation ends the TB. 188 */ 189 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, 190 uint16_t idxmap); 191 /** 192 * tlb_flush_by_mmuidx: 193 * @cpu: CPU whose TLB should be flushed 194 * @wait: If true ensure synchronisation by exiting the cpu_loop 195 * @idxmap: bitmap of MMU indexes to flush 196 * 197 * Flush all entries from the TLB of the specified CPU, for the specified 198 * MMU indexes. 199 */ 200 void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); 201 /** 202 * tlb_flush_by_mmuidx_all_cpus: 203 * @cpu: Originating CPU of the flush 204 * @idxmap: bitmap of MMU indexes to flush 205 * 206 * Flush all entries from all TLBs of all CPUs, for the specified 207 * MMU indexes. 208 */ 209 void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap); 210 /** 211 * tlb_flush_by_mmuidx_all_cpus_synced: 212 * @cpu: Originating CPU of the flush 213 * @idxmap: bitmap of MMU indexes to flush 214 * 215 * Flush all entries from all TLBs of all CPUs, for the specified 216 * MMU indexes like tlb_flush_by_mmuidx_all_cpus except except the source 217 * vCPUs work is scheduled as safe work meaning all flushes will be 218 * complete once the source vCPUs safe work is complete. This will 219 * depend on when the guests translation ends the TB. 220 */ 221 void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); 222 223 /** 224 * tlb_flush_page_bits_by_mmuidx 225 * @cpu: CPU whose TLB should be flushed 226 * @addr: virtual address of page to be flushed 227 * @idxmap: bitmap of mmu indexes to flush 228 * @bits: number of significant bits in address 229 * 230 * Similar to tlb_flush_page_mask, but with a bitmap of indexes. 231 */ 232 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, target_ulong addr, 233 uint16_t idxmap, unsigned bits); 234 235 /* Similarly, with broadcast and syncing. */ 236 void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 237 uint16_t idxmap, unsigned bits); 238 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced 239 (CPUState *cpu, target_ulong addr, uint16_t idxmap, unsigned bits); 240 241 /** 242 * tlb_flush_range_by_mmuidx 243 * @cpu: CPU whose TLB should be flushed 244 * @addr: virtual address of the start of the range to be flushed 245 * @len: length of range to be flushed 246 * @idxmap: bitmap of mmu indexes to flush 247 * @bits: number of significant bits in address 248 * 249 * For each mmuidx in @idxmap, flush all pages within [@addr,@addr+@len), 250 * comparing only the low @bits worth of each virtual page. 251 */ 252 void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, 253 target_ulong len, uint16_t idxmap, 254 unsigned bits); 255 256 /* Similarly, with broadcast and syncing. */ 257 void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, target_ulong addr, 258 target_ulong len, uint16_t idxmap, 259 unsigned bits); 260 void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, 261 target_ulong addr, 262 target_ulong len, 263 uint16_t idxmap, 264 unsigned bits); 265 266 /** 267 * tlb_set_page_full: 268 * @cpu: CPU context 269 * @mmu_idx: mmu index of the tlb to modify 270 * @vaddr: virtual address of the entry to add 271 * @full: the details of the tlb entry 272 * 273 * Add an entry to @cpu tlb index @mmu_idx. All of the fields of 274 * @full must be filled, except for xlat_section, and constitute 275 * the complete description of the translated page. 276 * 277 * This is generally called by the target tlb_fill function after 278 * having performed a successful page table walk to find the physical 279 * address and attributes for the translation. 280 * 281 * At most one entry for a given virtual address is permitted. Only a 282 * single TARGET_PAGE_SIZE region is mapped; @full->lg_page_size is only 283 * used by tlb_flush_page. 284 */ 285 void tlb_set_page_full(CPUState *cpu, int mmu_idx, target_ulong vaddr, 286 CPUTLBEntryFull *full); 287 288 /** 289 * tlb_set_page_with_attrs: 290 * @cpu: CPU to add this TLB entry for 291 * @vaddr: virtual address of page to add entry for 292 * @paddr: physical address of the page 293 * @attrs: memory transaction attributes 294 * @prot: access permissions (PAGE_READ/PAGE_WRITE/PAGE_EXEC bits) 295 * @mmu_idx: MMU index to insert TLB entry for 296 * @size: size of the page in bytes 297 * 298 * Add an entry to this CPU's TLB (a mapping from virtual address 299 * @vaddr to physical address @paddr) with the specified memory 300 * transaction attributes. This is generally called by the target CPU 301 * specific code after it has been called through the tlb_fill() 302 * entry point and performed a successful page table walk to find 303 * the physical address and attributes for the virtual address 304 * which provoked the TLB miss. 305 * 306 * At most one entry for a given virtual address is permitted. Only a 307 * single TARGET_PAGE_SIZE region is mapped; the supplied @size is only 308 * used by tlb_flush_page. 309 */ 310 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, 311 hwaddr paddr, MemTxAttrs attrs, 312 int prot, int mmu_idx, target_ulong size); 313 /* tlb_set_page: 314 * 315 * This function is equivalent to calling tlb_set_page_with_attrs() 316 * with an @attrs argument of MEMTXATTRS_UNSPECIFIED. It's provided 317 * as a convenience for CPUs which don't use memory transaction attributes. 318 */ 319 void tlb_set_page(CPUState *cpu, target_ulong vaddr, 320 hwaddr paddr, int prot, 321 int mmu_idx, target_ulong size); 322 #else 323 static inline void tlb_init(CPUState *cpu) 324 { 325 } 326 static inline void tlb_destroy(CPUState *cpu) 327 { 328 } 329 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 330 { 331 } 332 static inline void tlb_flush_page_all_cpus(CPUState *src, target_ulong addr) 333 { 334 } 335 static inline void tlb_flush_page_all_cpus_synced(CPUState *src, 336 target_ulong addr) 337 { 338 } 339 static inline void tlb_flush(CPUState *cpu) 340 { 341 } 342 static inline void tlb_flush_all_cpus(CPUState *src_cpu) 343 { 344 } 345 static inline void tlb_flush_all_cpus_synced(CPUState *src_cpu) 346 { 347 } 348 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, 349 target_ulong addr, uint16_t idxmap) 350 { 351 } 352 353 static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) 354 { 355 } 356 static inline void tlb_flush_page_by_mmuidx_all_cpus(CPUState *cpu, 357 target_ulong addr, 358 uint16_t idxmap) 359 { 360 } 361 static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, 362 target_ulong addr, 363 uint16_t idxmap) 364 { 365 } 366 static inline void tlb_flush_by_mmuidx_all_cpus(CPUState *cpu, uint16_t idxmap) 367 { 368 } 369 370 static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, 371 uint16_t idxmap) 372 { 373 } 374 static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, 375 target_ulong addr, 376 uint16_t idxmap, 377 unsigned bits) 378 { 379 } 380 static inline void tlb_flush_page_bits_by_mmuidx_all_cpus(CPUState *cpu, 381 target_ulong addr, 382 uint16_t idxmap, 383 unsigned bits) 384 { 385 } 386 static inline void 387 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, target_ulong addr, 388 uint16_t idxmap, unsigned bits) 389 { 390 } 391 static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, target_ulong addr, 392 target_ulong len, uint16_t idxmap, 393 unsigned bits) 394 { 395 } 396 static inline void tlb_flush_range_by_mmuidx_all_cpus(CPUState *cpu, 397 target_ulong addr, 398 target_ulong len, 399 uint16_t idxmap, 400 unsigned bits) 401 { 402 } 403 static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, 404 target_ulong addr, 405 target_long len, 406 uint16_t idxmap, 407 unsigned bits) 408 { 409 } 410 #endif 411 /** 412 * probe_access: 413 * @env: CPUArchState 414 * @addr: guest virtual address to look up 415 * @size: size of the access 416 * @access_type: read, write or execute permission 417 * @mmu_idx: MMU index to use for lookup 418 * @retaddr: return address for unwinding 419 * 420 * Look up the guest virtual address @addr. Raise an exception if the 421 * page does not satisfy @access_type. Raise an exception if the 422 * access (@addr, @size) hits a watchpoint. For writes, mark a clean 423 * page as dirty. 424 * 425 * Finally, return the host address for a page that is backed by RAM, 426 * or NULL if the page requires I/O. 427 */ 428 void *probe_access(CPUArchState *env, target_ulong addr, int size, 429 MMUAccessType access_type, int mmu_idx, uintptr_t retaddr); 430 431 static inline void *probe_write(CPUArchState *env, target_ulong addr, int size, 432 int mmu_idx, uintptr_t retaddr) 433 { 434 return probe_access(env, addr, size, MMU_DATA_STORE, mmu_idx, retaddr); 435 } 436 437 static inline void *probe_read(CPUArchState *env, target_ulong addr, int size, 438 int mmu_idx, uintptr_t retaddr) 439 { 440 return probe_access(env, addr, size, MMU_DATA_LOAD, mmu_idx, retaddr); 441 } 442 443 /** 444 * probe_access_flags: 445 * @env: CPUArchState 446 * @addr: guest virtual address to look up 447 * @size: size of the access 448 * @access_type: read, write or execute permission 449 * @mmu_idx: MMU index to use for lookup 450 * @nonfault: suppress the fault 451 * @phost: return value for host address 452 * @retaddr: return address for unwinding 453 * 454 * Similar to probe_access, loosely returning the TLB_FLAGS_MASK for 455 * the page, and storing the host address for RAM in @phost. 456 * 457 * If @nonfault is set, do not raise an exception but return TLB_INVALID_MASK. 458 * Do not handle watchpoints, but include TLB_WATCHPOINT in the returned flags. 459 * Do handle clean pages, so exclude TLB_NOTDIRY from the returned flags. 460 * For simplicity, all "mmio-like" flags are folded to TLB_MMIO. 461 */ 462 int probe_access_flags(CPUArchState *env, target_ulong addr, int size, 463 MMUAccessType access_type, int mmu_idx, 464 bool nonfault, void **phost, uintptr_t retaddr); 465 466 #ifndef CONFIG_USER_ONLY 467 /** 468 * probe_access_full: 469 * Like probe_access_flags, except also return into @pfull. 470 * 471 * The CPUTLBEntryFull structure returned via @pfull is transient 472 * and must be consumed or copied immediately, before any further 473 * access or changes to TLB @mmu_idx. 474 */ 475 int probe_access_full(CPUArchState *env, target_ulong addr, int size, 476 MMUAccessType access_type, int mmu_idx, 477 bool nonfault, void **phost, 478 CPUTLBEntryFull **pfull, uintptr_t retaddr); 479 #endif 480 481 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 482 483 /* Estimated block size for TB allocation. */ 484 /* ??? The following is based on a 2015 survey of x86_64 host output. 485 Better would seem to be some sort of dynamically sized TB array, 486 adapting to the block sizes actually being produced. */ 487 #if defined(CONFIG_SOFTMMU) 488 #define CODE_GEN_AVG_BLOCK_SIZE 400 489 #else 490 #define CODE_GEN_AVG_BLOCK_SIZE 150 491 #endif 492 493 /* 494 * Translation Cache-related fields of a TB. 495 * This struct exists just for convenience; we keep track of TB's in a binary 496 * search tree, and the only fields needed to compare TB's in the tree are 497 * @ptr and @size. 498 * Note: the address of search data can be obtained by adding @size to @ptr. 499 */ 500 struct tb_tc { 501 const void *ptr; /* pointer to the translated code */ 502 size_t size; 503 }; 504 505 struct TranslationBlock { 506 /* 507 * Guest PC corresponding to this block. This must be the true 508 * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and 509 * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or 510 * privilege, must store those bits elsewhere. 511 * 512 * If CF_PCREL, the opcodes for the TranslationBlock are written 513 * such that the TB is associated only with the physical page and 514 * may be run in any virtual address context. In this case, PC 515 * must always be taken from ENV in a target-specific manner. 516 * Unwind information is taken as offsets from the page, to be 517 * deposited into the "current" PC. 518 */ 519 target_ulong pc; 520 521 /* 522 * Target-specific data associated with the TranslationBlock, e.g.: 523 * x86: the original user, the Code Segment virtual base, 524 * arm: an extension of tb->flags, 525 * s390x: instruction data for EXECUTE, 526 * sparc: the next pc of the instruction queue (for delay slots). 527 */ 528 target_ulong cs_base; 529 530 uint32_t flags; /* flags defining in which context the code was generated */ 531 uint32_t cflags; /* compile flags */ 532 533 /* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ 534 #define CF_COUNT_MASK 0x000001ff 535 #define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ 536 #define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ 537 #define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ 538 #define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ 539 #define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ 540 #define CF_USE_ICOUNT 0x00020000 541 #define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ 542 #define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ 543 #define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ 544 #define CF_PCREL 0x00200000 /* Opcodes in TB are PC-relative */ 545 #define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ 546 #define CF_CLUSTER_SHIFT 24 547 548 /* Per-vCPU dynamic tracing state used to generate this TB */ 549 uint32_t trace_vcpu_dstate; 550 551 /* 552 * Above fields used for comparing 553 */ 554 555 /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ 556 uint16_t size; 557 uint16_t icount; 558 559 struct tb_tc tc; 560 561 /* 562 * Track tb_page_addr_t intervals that intersect this TB. 563 * For user-only, the virtual addresses are always contiguous, 564 * and we use a unified interval tree. For system, we use a 565 * linked list headed in each PageDesc. Within the list, the lsb 566 * of the previous pointer tells the index of page_next[], and the 567 * list is protected by the PageDesc lock(s). 568 */ 569 #ifdef CONFIG_USER_ONLY 570 IntervalTreeNode itree; 571 #else 572 uintptr_t page_next[2]; 573 tb_page_addr_t page_addr[2]; 574 #endif 575 576 /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */ 577 QemuSpin jmp_lock; 578 579 /* The following data are used to directly call another TB from 580 * the code of this one. This can be done either by emitting direct or 581 * indirect native jump instructions. These jumps are reset so that the TB 582 * just continues its execution. The TB can be linked to another one by 583 * setting one of the jump targets (or patching the jump instruction). Only 584 * two of such jumps are supported. 585 */ 586 #define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */ 587 uint16_t jmp_reset_offset[2]; /* offset of original jump target */ 588 uint16_t jmp_insn_offset[2]; /* offset of direct jump insn */ 589 uintptr_t jmp_target_addr[2]; /* target address */ 590 591 /* 592 * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps. 593 * Each TB can have two outgoing jumps, and therefore can participate 594 * in two lists. The list entries are kept in jmp_list_next[2]. The least 595 * significant bit (LSB) of the pointers in these lists is used to encode 596 * which of the two list entries is to be used in the pointed TB. 597 * 598 * List traversals are protected by jmp_lock. The destination TB of each 599 * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock 600 * can be acquired from any origin TB. 601 * 602 * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is 603 * being invalidated, so that no further outgoing jumps from it can be set. 604 * 605 * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained 606 * to a destination TB that has CF_INVALID set. 607 */ 608 uintptr_t jmp_list_head; 609 uintptr_t jmp_list_next[2]; 610 uintptr_t jmp_dest[2]; 611 }; 612 613 /* Hide the qatomic_read to make code a little easier on the eyes */ 614 static inline uint32_t tb_cflags(const TranslationBlock *tb) 615 { 616 return qatomic_read(&tb->cflags); 617 } 618 619 static inline tb_page_addr_t tb_page_addr0(const TranslationBlock *tb) 620 { 621 #ifdef CONFIG_USER_ONLY 622 return tb->itree.start; 623 #else 624 return tb->page_addr[0]; 625 #endif 626 } 627 628 static inline tb_page_addr_t tb_page_addr1(const TranslationBlock *tb) 629 { 630 #ifdef CONFIG_USER_ONLY 631 tb_page_addr_t next = tb->itree.last & TARGET_PAGE_MASK; 632 return next == (tb->itree.start & TARGET_PAGE_MASK) ? -1 : next; 633 #else 634 return tb->page_addr[1]; 635 #endif 636 } 637 638 static inline void tb_set_page_addr0(TranslationBlock *tb, 639 tb_page_addr_t addr) 640 { 641 #ifdef CONFIG_USER_ONLY 642 tb->itree.start = addr; 643 /* 644 * To begin, we record an interval of one byte. When the translation 645 * loop encounters a second page, the interval will be extended to 646 * include the first byte of the second page, which is sufficient to 647 * allow tb_page_addr1() above to work properly. The final corrected 648 * interval will be set by tb_page_add() from tb->size before the 649 * node is added to the interval tree. 650 */ 651 tb->itree.last = addr; 652 #else 653 tb->page_addr[0] = addr; 654 #endif 655 } 656 657 static inline void tb_set_page_addr1(TranslationBlock *tb, 658 tb_page_addr_t addr) 659 { 660 #ifdef CONFIG_USER_ONLY 661 /* Extend the interval to the first byte of the second page. See above. */ 662 tb->itree.last = addr; 663 #else 664 tb->page_addr[1] = addr; 665 #endif 666 } 667 668 /* current cflags for hashing/comparison */ 669 uint32_t curr_cflags(CPUState *cpu); 670 671 /* TranslationBlock invalidate API */ 672 #if defined(CONFIG_USER_ONLY) 673 void tb_invalidate_phys_addr(target_ulong addr); 674 #else 675 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs); 676 #endif 677 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 678 void tb_invalidate_phys_range(tb_page_addr_t start, tb_page_addr_t last); 679 void tb_set_jmp_target(TranslationBlock *tb, int n, uintptr_t addr); 680 681 /* GETPC is the true target of the return instruction that we'll execute. */ 682 #if defined(CONFIG_TCG_INTERPRETER) 683 extern __thread uintptr_t tci_tb_ptr; 684 # define GETPC() tci_tb_ptr 685 #else 686 # define GETPC() \ 687 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 688 #endif 689 690 /* The true return address will often point to a host insn that is part of 691 the next translated guest insn. Adjust the address backward to point to 692 the middle of the call insn. Subtracting one would do the job except for 693 several compressed mode architectures (arm, mips) which set the low bit 694 to indicate the compressed mode; subtracting two works around that. It 695 is also the case that there are no host isas that contain a call insn 696 smaller than 4 bytes, so we don't worry about special-casing this. */ 697 #define GETPC_ADJ 2 698 699 #if !defined(CONFIG_USER_ONLY) 700 701 /** 702 * iotlb_to_section: 703 * @cpu: CPU performing the access 704 * @index: TCG CPU IOTLB entry 705 * 706 * Given a TCG CPU IOTLB entry, return the MemoryRegionSection that 707 * it refers to. @index will have been initially created and returned 708 * by memory_region_section_get_iotlb(). 709 */ 710 struct MemoryRegionSection *iotlb_to_section(CPUState *cpu, 711 hwaddr index, MemTxAttrs attrs); 712 #endif 713 714 /** 715 * get_page_addr_code_hostp() 716 * @env: CPUArchState 717 * @addr: guest virtual address of guest code 718 * 719 * See get_page_addr_code() (full-system version) for documentation on the 720 * return value. 721 * 722 * Sets *@hostp (when @hostp is non-NULL) as follows. 723 * If the return value is -1, sets *@hostp to NULL. Otherwise, sets *@hostp 724 * to the host address where @addr's content is kept. 725 * 726 * Note: this function can trigger an exception. 727 */ 728 tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, 729 void **hostp); 730 731 /** 732 * get_page_addr_code() 733 * @env: CPUArchState 734 * @addr: guest virtual address of guest code 735 * 736 * If we cannot translate and execute from the entire RAM page, or if 737 * the region is not backed by RAM, returns -1. Otherwise, returns the 738 * ram_addr_t corresponding to the guest code at @addr. 739 * 740 * Note: this function can trigger an exception. 741 */ 742 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env, 743 target_ulong addr) 744 { 745 return get_page_addr_code_hostp(env, addr, NULL); 746 } 747 748 #if defined(CONFIG_USER_ONLY) 749 void TSA_NO_TSA mmap_lock(void); 750 void TSA_NO_TSA mmap_unlock(void); 751 bool have_mmap_lock(void); 752 753 /** 754 * adjust_signal_pc: 755 * @pc: raw pc from the host signal ucontext_t. 756 * @is_write: host memory operation was write, or read-modify-write. 757 * 758 * Alter @pc as required for unwinding. Return the type of the 759 * guest memory access -- host reads may be for guest execution. 760 */ 761 MMUAccessType adjust_signal_pc(uintptr_t *pc, bool is_write); 762 763 /** 764 * handle_sigsegv_accerr_write: 765 * @cpu: the cpu context 766 * @old_set: the sigset_t from the signal ucontext_t 767 * @host_pc: the host pc, adjusted for the signal 768 * @host_addr: the host address of the fault 769 * 770 * Return true if the write fault has been handled, and should be re-tried. 771 */ 772 bool handle_sigsegv_accerr_write(CPUState *cpu, sigset_t *old_set, 773 uintptr_t host_pc, abi_ptr guest_addr); 774 775 /** 776 * cpu_loop_exit_sigsegv: 777 * @cpu: the cpu context 778 * @addr: the guest address of the fault 779 * @access_type: access was read/write/execute 780 * @maperr: true for invalid page, false for permission fault 781 * @ra: host pc for unwinding 782 * 783 * Use the TCGCPUOps hook to record cpu state, do guest operating system 784 * specific things to raise SIGSEGV, and jump to the main cpu loop. 785 */ 786 G_NORETURN void cpu_loop_exit_sigsegv(CPUState *cpu, target_ulong addr, 787 MMUAccessType access_type, 788 bool maperr, uintptr_t ra); 789 790 /** 791 * cpu_loop_exit_sigbus: 792 * @cpu: the cpu context 793 * @addr: the guest address of the alignment fault 794 * @access_type: access was read/write/execute 795 * @ra: host pc for unwinding 796 * 797 * Use the TCGCPUOps hook to record cpu state, do guest operating system 798 * specific things to raise SIGBUS, and jump to the main cpu loop. 799 */ 800 G_NORETURN void cpu_loop_exit_sigbus(CPUState *cpu, target_ulong addr, 801 MMUAccessType access_type, 802 uintptr_t ra); 803 804 #else 805 static inline void mmap_lock(void) {} 806 static inline void mmap_unlock(void) {} 807 808 void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length); 809 void tlb_set_dirty(CPUState *cpu, target_ulong vaddr); 810 811 MemoryRegionSection * 812 address_space_translate_for_iotlb(CPUState *cpu, int asidx, hwaddr addr, 813 hwaddr *xlat, hwaddr *plen, 814 MemTxAttrs attrs, int *prot); 815 hwaddr memory_region_section_get_iotlb(CPUState *cpu, 816 MemoryRegionSection *section); 817 #endif 818 819 #endif 820