1 /* 2 * internal execution defines for qemu 3 * 4 * Copyright (c) 2003 Fabrice Bellard 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef _EXEC_ALL_H_ 21 #define _EXEC_ALL_H_ 22 23 #include "qemu-common.h" 24 25 /* allow to see translation results - the slowdown should be negligible, so we leave it */ 26 #define DEBUG_DISAS 27 28 /* Page tracking code uses ram addresses in system mode, and virtual 29 addresses in userspace mode. Define tb_page_addr_t to be an appropriate 30 type. */ 31 #if defined(CONFIG_USER_ONLY) 32 typedef abi_ulong tb_page_addr_t; 33 #else 34 typedef ram_addr_t tb_page_addr_t; 35 #endif 36 37 /* is_jmp field values */ 38 #define DISAS_NEXT 0 /* next instruction can be analyzed */ 39 #define DISAS_JUMP 1 /* only pc was modified dynamically */ 40 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */ 41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */ 42 43 struct TranslationBlock; 44 typedef struct TranslationBlock TranslationBlock; 45 46 /* XXX: make safe guess about sizes */ 47 #define MAX_OP_PER_INSTR 266 48 49 #if HOST_LONG_BITS == 32 50 #define MAX_OPC_PARAM_PER_ARG 2 51 #else 52 #define MAX_OPC_PARAM_PER_ARG 1 53 #endif 54 #define MAX_OPC_PARAM_IARGS 5 55 #define MAX_OPC_PARAM_OARGS 1 56 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS) 57 58 /* A Call op needs up to 4 + 2N parameters on 32-bit archs, 59 * and up to 4 + N parameters on 64-bit archs 60 * (N = number of input arguments + output arguments). */ 61 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS)) 62 #define OPC_BUF_SIZE 640 63 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR) 64 65 /* Maximum size a TCG op can expand to. This is complicated because a 66 single op may require several host instructions and register reloads. 67 For now take a wild guess at 192 bytes, which should allow at least 68 a couple of fixup instructions per argument. */ 69 #define TCG_MAX_OP_SIZE 192 70 71 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) 72 73 #include "qemu/log.h" 74 75 void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); 76 void gen_intermediate_code_pc(CPUArchState *env, struct TranslationBlock *tb); 77 void restore_state_to_opc(CPUArchState *env, struct TranslationBlock *tb, 78 int pc_pos); 79 80 void cpu_gen_init(void); 81 int cpu_gen_code(CPUArchState *env, struct TranslationBlock *tb, 82 int *gen_code_size_ptr); 83 bool cpu_restore_state(CPUState *cpu, uintptr_t searched_pc); 84 void page_size_init(void); 85 86 void QEMU_NORETURN cpu_resume_from_signal(CPUState *cpu, void *puc); 87 void QEMU_NORETURN cpu_io_recompile(CPUState *cpu, uintptr_t retaddr); 88 TranslationBlock *tb_gen_code(CPUState *cpu, 89 target_ulong pc, target_ulong cs_base, int flags, 90 int cflags); 91 void cpu_exec_init(CPUState *cpu, Error **errp); 92 void QEMU_NORETURN cpu_loop_exit(CPUState *cpu); 93 94 #if !defined(CONFIG_USER_ONLY) 95 bool qemu_in_vcpu_thread(void); 96 void cpu_reload_memory_map(CPUState *cpu); 97 void tcg_cpu_address_space_init(CPUState *cpu, AddressSpace *as); 98 /* cputlb.c */ 99 /** 100 * tlb_flush_page: 101 * @cpu: CPU whose TLB should be flushed 102 * @addr: virtual address of page to be flushed 103 * 104 * Flush one page from the TLB of the specified CPU, for all 105 * MMU indexes. 106 */ 107 void tlb_flush_page(CPUState *cpu, target_ulong addr); 108 /** 109 * tlb_flush: 110 * @cpu: CPU whose TLB should be flushed 111 * @flush_global: ignored 112 * 113 * Flush the entire TLB for the specified CPU. 114 * The flush_global flag is in theory an indicator of whether the whole 115 * TLB should be flushed, or only those entries not marked global. 116 * In practice QEMU does not implement any global/not global flag for 117 * TLB entries, and the argument is ignored. 118 */ 119 void tlb_flush(CPUState *cpu, int flush_global); 120 /** 121 * tlb_flush_page_by_mmuidx: 122 * @cpu: CPU whose TLB should be flushed 123 * @addr: virtual address of page to be flushed 124 * @...: list of MMU indexes to flush, terminated by a negative value 125 * 126 * Flush one page from the TLB of the specified CPU, for the specified 127 * MMU indexes. 128 */ 129 void tlb_flush_page_by_mmuidx(CPUState *cpu, target_ulong addr, ...); 130 /** 131 * tlb_flush_by_mmuidx: 132 * @cpu: CPU whose TLB should be flushed 133 * @...: list of MMU indexes to flush, terminated by a negative value 134 * 135 * Flush all entries from the TLB of the specified CPU, for the specified 136 * MMU indexes. 137 */ 138 void tlb_flush_by_mmuidx(CPUState *cpu, ...); 139 void tlb_set_page(CPUState *cpu, target_ulong vaddr, 140 hwaddr paddr, int prot, 141 int mmu_idx, target_ulong size); 142 void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr, 143 hwaddr paddr, MemTxAttrs attrs, 144 int prot, int mmu_idx, target_ulong size); 145 void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr); 146 void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, 147 uintptr_t retaddr); 148 #else 149 static inline void tlb_flush_page(CPUState *cpu, target_ulong addr) 150 { 151 } 152 153 static inline void tlb_flush(CPUState *cpu, int flush_global) 154 { 155 } 156 157 static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, 158 target_ulong addr, ...) 159 { 160 } 161 162 static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) 163 { 164 } 165 #endif 166 167 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ 168 169 #define CODE_GEN_PHYS_HASH_BITS 15 170 #define CODE_GEN_PHYS_HASH_SIZE (1 << CODE_GEN_PHYS_HASH_BITS) 171 172 /* estimated block size for TB allocation */ 173 /* XXX: use a per code average code fragment size and modulate it 174 according to the host CPU */ 175 #if defined(CONFIG_SOFTMMU) 176 #define CODE_GEN_AVG_BLOCK_SIZE 128 177 #else 178 #define CODE_GEN_AVG_BLOCK_SIZE 64 179 #endif 180 181 #if defined(__arm__) || defined(_ARCH_PPC) \ 182 || defined(__x86_64__) || defined(__i386__) \ 183 || defined(__sparc__) || defined(__aarch64__) \ 184 || defined(__s390x__) || defined(__mips__) \ 185 || defined(CONFIG_TCG_INTERPRETER) 186 #define USE_DIRECT_JUMP 187 #endif 188 189 struct TranslationBlock { 190 target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ 191 target_ulong cs_base; /* CS base for this block */ 192 uint64_t flags; /* flags defining in which context the code was generated */ 193 uint16_t size; /* size of target code for this block (1 <= 194 size <= TARGET_PAGE_SIZE) */ 195 uint16_t icount; 196 uint32_t cflags; /* compile flags */ 197 #define CF_COUNT_MASK 0x7fff 198 #define CF_LAST_IO 0x8000 /* Last insn may be an IO access. */ 199 #define CF_NOCACHE 0x10000 /* To be freed after execution */ 200 #define CF_USE_ICOUNT 0x20000 201 202 void *tc_ptr; /* pointer to the translated code */ 203 /* next matching tb for physical address. */ 204 struct TranslationBlock *phys_hash_next; 205 /* original tb when cflags has CF_NOCACHE */ 206 struct TranslationBlock *orig_tb; 207 /* first and second physical page containing code. The lower bit 208 of the pointer tells the index in page_next[] */ 209 struct TranslationBlock *page_next[2]; 210 tb_page_addr_t page_addr[2]; 211 212 /* the following data are used to directly call another TB from 213 the code of this one. */ 214 uint16_t tb_next_offset[2]; /* offset of original jump target */ 215 #ifdef USE_DIRECT_JUMP 216 uint16_t tb_jmp_offset[2]; /* offset of jump instruction */ 217 #else 218 uintptr_t tb_next[2]; /* address of jump generated code */ 219 #endif 220 /* list of TBs jumping to this one. This is a circular list using 221 the two least significant bits of the pointers to tell what is 222 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 = 223 jmp_first */ 224 struct TranslationBlock *jmp_next[2]; 225 struct TranslationBlock *jmp_first; 226 }; 227 228 #include "exec/spinlock.h" 229 230 typedef struct TBContext TBContext; 231 232 struct TBContext { 233 234 TranslationBlock *tbs; 235 TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE]; 236 int nb_tbs; 237 /* any access to the tbs or the page table must use this lock */ 238 spinlock_t tb_lock; 239 240 /* statistics */ 241 int tb_flush_count; 242 int tb_phys_invalidate_count; 243 244 int tb_invalidated_flag; 245 }; 246 247 void tb_free(TranslationBlock *tb); 248 void tb_flush(CPUState *cpu); 249 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr); 250 251 #if defined(USE_DIRECT_JUMP) 252 253 #if defined(CONFIG_TCG_INTERPRETER) 254 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 255 { 256 /* patch the branch destination */ 257 *(uint32_t *)jmp_addr = addr - (jmp_addr + 4); 258 /* no need to flush icache explicitly */ 259 } 260 #elif defined(_ARCH_PPC) 261 void ppc_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); 262 #define tb_set_jmp_target1 ppc_tb_set_jmp_target 263 #elif defined(__i386__) || defined(__x86_64__) 264 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 265 { 266 /* patch the branch destination */ 267 stl_le_p((void*)jmp_addr, addr - (jmp_addr + 4)); 268 /* no need to flush icache explicitly */ 269 } 270 #elif defined(__s390x__) 271 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 272 { 273 /* patch the branch destination */ 274 intptr_t disp = addr - (jmp_addr - 2); 275 stl_be_p((void*)jmp_addr, disp / 2); 276 /* no need to flush icache explicitly */ 277 } 278 #elif defined(__aarch64__) 279 void aarch64_tb_set_jmp_target(uintptr_t jmp_addr, uintptr_t addr); 280 #define tb_set_jmp_target1 aarch64_tb_set_jmp_target 281 #elif defined(__arm__) 282 static inline void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr) 283 { 284 #if !QEMU_GNUC_PREREQ(4, 1) 285 register unsigned long _beg __asm ("a1"); 286 register unsigned long _end __asm ("a2"); 287 register unsigned long _flg __asm ("a3"); 288 #endif 289 290 /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */ 291 *(uint32_t *)jmp_addr = 292 (*(uint32_t *)jmp_addr & ~0xffffff) 293 | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff); 294 295 #if QEMU_GNUC_PREREQ(4, 1) 296 __builtin___clear_cache((char *) jmp_addr, (char *) jmp_addr + 4); 297 #else 298 /* flush icache */ 299 _beg = jmp_addr; 300 _end = jmp_addr + 4; 301 _flg = 0; 302 __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg)); 303 #endif 304 } 305 #elif defined(__sparc__) || defined(__mips__) 306 void tb_set_jmp_target1(uintptr_t jmp_addr, uintptr_t addr); 307 #else 308 #error tb_set_jmp_target1 is missing 309 #endif 310 311 static inline void tb_set_jmp_target(TranslationBlock *tb, 312 int n, uintptr_t addr) 313 { 314 uint16_t offset = tb->tb_jmp_offset[n]; 315 tb_set_jmp_target1((uintptr_t)(tb->tc_ptr + offset), addr); 316 } 317 318 #else 319 320 /* set the jump target */ 321 static inline void tb_set_jmp_target(TranslationBlock *tb, 322 int n, uintptr_t addr) 323 { 324 tb->tb_next[n] = addr; 325 } 326 327 #endif 328 329 static inline void tb_add_jump(TranslationBlock *tb, int n, 330 TranslationBlock *tb_next) 331 { 332 /* NOTE: this test is only needed for thread safety */ 333 if (!tb->jmp_next[n]) { 334 /* patch the native jump address */ 335 tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr); 336 337 /* add in TB jmp circular list */ 338 tb->jmp_next[n] = tb_next->jmp_first; 339 tb_next->jmp_first = (TranslationBlock *)((uintptr_t)(tb) | (n)); 340 } 341 } 342 343 /* GETRA is the true target of the return instruction that we'll execute, 344 defined here for simplicity of defining the follow-up macros. */ 345 #if defined(CONFIG_TCG_INTERPRETER) 346 extern uintptr_t tci_tb_ptr; 347 # define GETRA() tci_tb_ptr 348 #else 349 # define GETRA() \ 350 ((uintptr_t)__builtin_extract_return_addr(__builtin_return_address(0))) 351 #endif 352 353 /* The true return address will often point to a host insn that is part of 354 the next translated guest insn. Adjust the address backward to point to 355 the middle of the call insn. Subtracting one would do the job except for 356 several compressed mode architectures (arm, mips) which set the low bit 357 to indicate the compressed mode; subtracting two works around that. It 358 is also the case that there are no host isas that contain a call insn 359 smaller than 4 bytes, so we don't worry about special-casing this. */ 360 #define GETPC_ADJ 2 361 362 #define GETPC() (GETRA() - GETPC_ADJ) 363 364 #if !defined(CONFIG_USER_ONLY) 365 366 void phys_mem_set_alloc(void *(*alloc)(size_t, uint64_t *align)); 367 368 struct MemoryRegion *iotlb_to_region(CPUState *cpu, 369 hwaddr index); 370 371 void tlb_fill(CPUState *cpu, target_ulong addr, int is_write, int mmu_idx, 372 uintptr_t retaddr); 373 374 #endif 375 376 #if defined(CONFIG_USER_ONLY) 377 static inline tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr) 378 { 379 return addr; 380 } 381 #else 382 /* cputlb.c */ 383 tb_page_addr_t get_page_addr_code(CPUArchState *env1, target_ulong addr); 384 #endif 385 386 /* vl.c */ 387 extern int singlestep; 388 389 /* cpu-exec.c */ 390 extern volatile sig_atomic_t exit_request; 391 392 #if !defined(CONFIG_USER_ONLY) 393 void migration_bitmap_extend(ram_addr_t old, ram_addr_t new); 394 #endif 395 #endif 396