1 /* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License as published by 4 * the Free Software Foundation; either version 2 of the License, or 5 * (at your option) any later version. 6 7 * This program is distributed in the hope that it will be useful, 8 * but WITHOUT ANY WARRANTY; without even the implied warranty of 9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 10 * GNU General Public License for more details. 11 12 * You should have received a copy of the GNU General Public License along 13 * with this program; if not, see <http://www.gnu.org/licenses/>. 14 */ 15 #ifndef QEMU_ACPI_DEFS_H 16 #define QEMU_ACPI_DEFS_H 17 18 enum { 19 ACPI_FADT_F_WBINVD, 20 ACPI_FADT_F_WBINVD_FLUSH, 21 ACPI_FADT_F_PROC_C1, 22 ACPI_FADT_F_P_LVL2_UP, 23 ACPI_FADT_F_PWR_BUTTON, 24 ACPI_FADT_F_SLP_BUTTON, 25 ACPI_FADT_F_FIX_RTC, 26 ACPI_FADT_F_RTC_S4, 27 ACPI_FADT_F_TMR_VAL_EXT, 28 ACPI_FADT_F_DCK_CAP, 29 ACPI_FADT_F_RESET_REG_SUP, 30 ACPI_FADT_F_SEALED_CASE, 31 ACPI_FADT_F_HEADLESS, 32 ACPI_FADT_F_CPU_SW_SLP, 33 ACPI_FADT_F_PCI_EXP_WAK, 34 ACPI_FADT_F_USE_PLATFORM_CLOCK, 35 ACPI_FADT_F_S4_RTC_STS_VALID, 36 ACPI_FADT_F_REMOTE_POWER_ON_CAPABLE, 37 ACPI_FADT_F_FORCE_APIC_CLUSTER_MODEL, 38 ACPI_FADT_F_FORCE_APIC_PHYSICAL_DESTINATION_MODE, 39 ACPI_FADT_F_HW_REDUCED_ACPI, 40 ACPI_FADT_F_LOW_POWER_S0_IDLE_CAPABLE, 41 }; 42 43 /* 44 * ACPI 2.0 Generic Address Space definition. 45 */ 46 struct Acpi20GenericAddress { 47 uint8_t address_space_id; 48 uint8_t register_bit_width; 49 uint8_t register_bit_offset; 50 uint8_t reserved; 51 uint64_t address; 52 } QEMU_PACKED; 53 typedef struct Acpi20GenericAddress Acpi20GenericAddress; 54 55 struct AcpiRsdpDescriptor { /* Root System Descriptor Pointer */ 56 uint64_t signature; /* ACPI signature, contains "RSD PTR " */ 57 uint8_t checksum; /* To make sum of struct == 0 */ 58 uint8_t oem_id [6]; /* OEM identification */ 59 uint8_t revision; /* Must be 0 for 1.0, 2 for 2.0 */ 60 uint32_t rsdt_physical_address; /* 32-bit physical address of RSDT */ 61 uint32_t length; /* XSDT Length in bytes including hdr */ 62 uint64_t xsdt_physical_address; /* 64-bit physical address of XSDT */ 63 uint8_t extended_checksum; /* Checksum of entire table */ 64 uint8_t reserved [3]; /* Reserved field must be 0 */ 65 } QEMU_PACKED; 66 typedef struct AcpiRsdpDescriptor AcpiRsdpDescriptor; 67 68 /* Table structure from Linux kernel (the ACPI tables are under the 69 BSD license) */ 70 71 72 #define ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ 73 uint32_t signature; /* ACPI signature (4 ASCII characters) */ \ 74 uint32_t length; /* Length of table, in bytes, including header */ \ 75 uint8_t revision; /* ACPI Specification minor version # */ \ 76 uint8_t checksum; /* To make sum of entire table == 0 */ \ 77 uint8_t oem_id [6]; /* OEM identification */ \ 78 uint8_t oem_table_id [8]; /* OEM table identification */ \ 79 uint32_t oem_revision; /* OEM revision number */ \ 80 uint8_t asl_compiler_id [4]; /* ASL compiler vendor ID */ \ 81 uint32_t asl_compiler_revision; /* ASL compiler revision number */ 82 83 84 struct AcpiTableHeader /* ACPI common table header */ 85 { 86 ACPI_TABLE_HEADER_DEF 87 } QEMU_PACKED; 88 typedef struct AcpiTableHeader AcpiTableHeader; 89 90 /* 91 * ACPI Fixed ACPI Description Table (FADT) 92 */ 93 #define ACPI_FADT_COMMON_DEF /* FADT common definition */ \ 94 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ \ 95 uint32_t firmware_ctrl; /* Physical address of FACS */ \ 96 uint32_t dsdt; /* Physical address of DSDT */ \ 97 uint8_t model; /* System Interrupt Model */ \ 98 uint8_t reserved1; /* Reserved */ \ 99 uint16_t sci_int; /* System vector of SCI interrupt */ \ 100 uint32_t smi_cmd; /* Port address of SMI command port */ \ 101 uint8_t acpi_enable; /* Value to write to smi_cmd to enable ACPI */ \ 102 uint8_t acpi_disable; /* Value to write to smi_cmd to disable ACPI */ \ 103 /* Value to write to SMI CMD to enter S4BIOS state */ \ 104 uint8_t S4bios_req; \ 105 uint8_t reserved2; /* Reserved - must be zero */ \ 106 /* Port address of Power Mgt 1a acpi_event Reg Blk */ \ 107 uint32_t pm1a_evt_blk; \ 108 /* Port address of Power Mgt 1b acpi_event Reg Blk */ \ 109 uint32_t pm1b_evt_blk; \ 110 uint32_t pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */ \ 111 uint32_t pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */ \ 112 uint32_t pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */ \ 113 uint32_t pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */ \ 114 /* Port addr of General Purpose acpi_event 0 Reg Blk */ \ 115 uint32_t gpe0_blk; \ 116 /* Port addr of General Purpose acpi_event 1 Reg Blk */ \ 117 uint32_t gpe1_blk; \ 118 uint8_t pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */ \ 119 uint8_t pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */ \ 120 uint8_t pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */ \ 121 uint8_t pm_tmr_len; /* Byte Length of ports at pm_tm_blk */ \ 122 uint8_t gpe0_blk_len; /* Byte Length of ports at gpe0_blk */ \ 123 uint8_t gpe1_blk_len; /* Byte Length of ports at gpe1_blk */ \ 124 uint8_t gpe1_base; /* Offset in gpe model where gpe1 events start */ \ 125 uint8_t reserved3; /* Reserved */ \ 126 uint16_t plvl2_lat; /* Worst case HW latency to enter/exit C2 state */ \ 127 uint16_t plvl3_lat; /* Worst case HW latency to enter/exit C3 state */ \ 128 uint16_t flush_size; /* Size of area read to flush caches */ \ 129 uint16_t flush_stride; /* Stride used in flushing caches */ \ 130 uint8_t duty_offset; /* Bit location of duty cycle field in p_cnt reg */ \ 131 uint8_t duty_width; /* Bit width of duty cycle field in p_cnt reg */ \ 132 uint8_t day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */ \ 133 uint8_t mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */ \ 134 uint8_t century; /* Index to century in RTC CMOS RAM */ 135 136 struct AcpiFadtDescriptorRev1 137 { 138 ACPI_FADT_COMMON_DEF 139 uint8_t reserved4; /* Reserved */ 140 uint8_t reserved4a; /* Reserved */ 141 uint8_t reserved4b; /* Reserved */ 142 uint32_t flags; 143 } QEMU_PACKED; 144 typedef struct AcpiFadtDescriptorRev1 AcpiFadtDescriptorRev1; 145 146 struct AcpiGenericAddress { 147 uint8_t space_id; /* Address space where struct or register exists */ 148 uint8_t bit_width; /* Size in bits of given register */ 149 uint8_t bit_offset; /* Bit offset within the register */ 150 uint8_t access_width; /* Minimum Access size (ACPI 3.0) */ 151 uint64_t address; /* 64-bit address of struct or register */ 152 } QEMU_PACKED; 153 154 struct AcpiFadtDescriptorRev5_1 { 155 ACPI_FADT_COMMON_DEF 156 /* IA-PC Boot Architecture Flags (see below for individual flags) */ 157 uint16_t boot_flags; 158 uint8_t reserved; /* Reserved, must be zero */ 159 /* Miscellaneous flag bits (see below for individual flags) */ 160 uint32_t flags; 161 /* 64-bit address of the Reset register */ 162 struct AcpiGenericAddress reset_register; 163 /* Value to write to the reset_register port to reset the system */ 164 uint8_t reset_value; 165 /* ARM-Specific Boot Flags (see below for individual flags) (ACPI 5.1) */ 166 uint16_t arm_boot_flags; 167 uint8_t minor_revision; /* FADT Minor Revision (ACPI 5.1) */ 168 uint64_t Xfacs; /* 64-bit physical address of FACS */ 169 uint64_t Xdsdt; /* 64-bit physical address of DSDT */ 170 /* 64-bit Extended Power Mgt 1a Event Reg Blk address */ 171 struct AcpiGenericAddress xpm1a_event_block; 172 /* 64-bit Extended Power Mgt 1b Event Reg Blk address */ 173 struct AcpiGenericAddress xpm1b_event_block; 174 /* 64-bit Extended Power Mgt 1a Control Reg Blk address */ 175 struct AcpiGenericAddress xpm1a_control_block; 176 /* 64-bit Extended Power Mgt 1b Control Reg Blk address */ 177 struct AcpiGenericAddress xpm1b_control_block; 178 /* 64-bit Extended Power Mgt 2 Control Reg Blk address */ 179 struct AcpiGenericAddress xpm2_control_block; 180 /* 64-bit Extended Power Mgt Timer Ctrl Reg Blk address */ 181 struct AcpiGenericAddress xpm_timer_block; 182 /* 64-bit Extended General Purpose Event 0 Reg Blk address */ 183 struct AcpiGenericAddress xgpe0_block; 184 /* 64-bit Extended General Purpose Event 1 Reg Blk address */ 185 struct AcpiGenericAddress xgpe1_block; 186 /* 64-bit Sleep Control register (ACPI 5.0) */ 187 struct AcpiGenericAddress sleep_control; 188 /* 64-bit Sleep Status register (ACPI 5.0) */ 189 struct AcpiGenericAddress sleep_status; 190 } QEMU_PACKED; 191 192 typedef struct AcpiFadtDescriptorRev5_1 AcpiFadtDescriptorRev5_1; 193 194 enum { 195 ACPI_FADT_ARM_USE_PSCI_G_0_2 = 0, 196 ACPI_FADT_ARM_PSCI_USE_HVC = 1, 197 }; 198 199 /* 200 * Serial Port Console Redirection Table (SPCR), Rev. 1.02 201 * 202 * For .interface_type see Debug Port Table 2 (DBG2) serial port 203 * subtypes in Table 3, Rev. May 22, 2012 204 */ 205 struct AcpiSerialPortConsoleRedirection { 206 ACPI_TABLE_HEADER_DEF 207 uint8_t interface_type; 208 uint8_t reserved1[3]; 209 struct AcpiGenericAddress base_address; 210 uint8_t interrupt_types; 211 uint8_t irq; 212 uint32_t gsi; 213 uint8_t baud; 214 uint8_t parity; 215 uint8_t stopbits; 216 uint8_t flowctrl; 217 uint8_t term_type; 218 uint8_t reserved2; 219 uint16_t pci_device_id; 220 uint16_t pci_vendor_id; 221 uint8_t pci_bus; 222 uint8_t pci_slot; 223 uint8_t pci_func; 224 uint32_t pci_flags; 225 uint8_t pci_seg; 226 uint32_t reserved3; 227 } QEMU_PACKED; 228 typedef struct AcpiSerialPortConsoleRedirection 229 AcpiSerialPortConsoleRedirection; 230 231 /* 232 * ACPI 1.0 Root System Description Table (RSDT) 233 */ 234 struct AcpiRsdtDescriptorRev1 235 { 236 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 237 uint32_t table_offset_entry[0]; /* Array of pointers to other */ 238 /* ACPI tables */ 239 } QEMU_PACKED; 240 typedef struct AcpiRsdtDescriptorRev1 AcpiRsdtDescriptorRev1; 241 242 /* 243 * ACPI 1.0 Firmware ACPI Control Structure (FACS) 244 */ 245 struct AcpiFacsDescriptorRev1 246 { 247 uint32_t signature; /* ACPI Signature */ 248 uint32_t length; /* Length of structure, in bytes */ 249 uint32_t hardware_signature; /* Hardware configuration signature */ 250 uint32_t firmware_waking_vector; /* ACPI OS waking vector */ 251 uint32_t global_lock; /* Global Lock */ 252 uint32_t flags; 253 uint8_t resverved3 [40]; /* Reserved - must be zero */ 254 } QEMU_PACKED; 255 typedef struct AcpiFacsDescriptorRev1 AcpiFacsDescriptorRev1; 256 257 /* 258 * Differentiated System Description Table (DSDT) 259 */ 260 261 /* 262 * MADT values and structures 263 */ 264 265 /* Values for MADT PCATCompat */ 266 267 #define ACPI_DUAL_PIC 0 268 #define ACPI_MULTIPLE_APIC 1 269 270 /* Master MADT */ 271 272 struct AcpiMultipleApicTable 273 { 274 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 275 uint32_t local_apic_address; /* Physical address of local APIC */ 276 uint32_t flags; 277 } QEMU_PACKED; 278 typedef struct AcpiMultipleApicTable AcpiMultipleApicTable; 279 280 /* Values for Type in APIC sub-headers */ 281 282 #define ACPI_APIC_PROCESSOR 0 283 #define ACPI_APIC_IO 1 284 #define ACPI_APIC_XRUPT_OVERRIDE 2 285 #define ACPI_APIC_NMI 3 286 #define ACPI_APIC_LOCAL_NMI 4 287 #define ACPI_APIC_ADDRESS_OVERRIDE 5 288 #define ACPI_APIC_IO_SAPIC 6 289 #define ACPI_APIC_LOCAL_SAPIC 7 290 #define ACPI_APIC_XRUPT_SOURCE 8 291 #define ACPI_APIC_LOCAL_X2APIC 9 292 #define ACPI_APIC_LOCAL_X2APIC_NMI 10 293 #define ACPI_APIC_GENERIC_INTERRUPT 11 294 #define ACPI_APIC_GENERIC_DISTRIBUTOR 12 295 #define ACPI_APIC_GENERIC_MSI_FRAME 13 296 #define ACPI_APIC_GENERIC_REDISTRIBUTOR 14 297 #define ACPI_APIC_GENERIC_TRANSLATOR 15 298 #define ACPI_APIC_RESERVED 16 /* 16 and greater are reserved */ 299 300 /* 301 * MADT sub-structures (Follow MULTIPLE_APIC_DESCRIPTION_TABLE) 302 */ 303 #define ACPI_SUB_HEADER_DEF /* Common ACPI sub-structure header */\ 304 uint8_t type; \ 305 uint8_t length; 306 307 /* Sub-structures for MADT */ 308 309 struct AcpiMadtProcessorApic 310 { 311 ACPI_SUB_HEADER_DEF 312 uint8_t processor_id; /* ACPI processor id */ 313 uint8_t local_apic_id; /* Processor's local APIC id */ 314 uint32_t flags; 315 } QEMU_PACKED; 316 typedef struct AcpiMadtProcessorApic AcpiMadtProcessorApic; 317 318 struct AcpiMadtIoApic 319 { 320 ACPI_SUB_HEADER_DEF 321 uint8_t io_apic_id; /* I/O APIC ID */ 322 uint8_t reserved; /* Reserved - must be zero */ 323 uint32_t address; /* APIC physical address */ 324 uint32_t interrupt; /* Global system interrupt where INTI 325 * lines start */ 326 } QEMU_PACKED; 327 typedef struct AcpiMadtIoApic AcpiMadtIoApic; 328 329 struct AcpiMadtIntsrcovr { 330 ACPI_SUB_HEADER_DEF 331 uint8_t bus; 332 uint8_t source; 333 uint32_t gsi; 334 uint16_t flags; 335 } QEMU_PACKED; 336 typedef struct AcpiMadtIntsrcovr AcpiMadtIntsrcovr; 337 338 struct AcpiMadtLocalNmi { 339 ACPI_SUB_HEADER_DEF 340 uint8_t processor_id; /* ACPI processor id */ 341 uint16_t flags; /* MPS INTI flags */ 342 uint8_t lint; /* Local APIC LINT# */ 343 } QEMU_PACKED; 344 typedef struct AcpiMadtLocalNmi AcpiMadtLocalNmi; 345 346 struct AcpiMadtProcessorX2Apic { 347 ACPI_SUB_HEADER_DEF 348 uint16_t reserved; 349 uint32_t x2apic_id; /* Processor's local x2APIC ID */ 350 uint32_t flags; 351 uint32_t uid; /* Processor object _UID */ 352 } QEMU_PACKED; 353 typedef struct AcpiMadtProcessorX2Apic AcpiMadtProcessorX2Apic; 354 355 struct AcpiMadtLocalX2ApicNmi { 356 ACPI_SUB_HEADER_DEF 357 uint16_t flags; /* MPS INTI flags */ 358 uint32_t uid; /* Processor object _UID */ 359 uint8_t lint; /* Local APIC LINT# */ 360 uint8_t reserved[3]; /* Local APIC LINT# */ 361 } QEMU_PACKED; 362 typedef struct AcpiMadtLocalX2ApicNmi AcpiMadtLocalX2ApicNmi; 363 364 struct AcpiMadtGenericInterrupt { 365 ACPI_SUB_HEADER_DEF 366 uint16_t reserved; 367 uint32_t cpu_interface_number; 368 uint32_t uid; 369 uint32_t flags; 370 uint32_t parking_version; 371 uint32_t performance_interrupt; 372 uint64_t parked_address; 373 uint64_t base_address; 374 uint64_t gicv_base_address; 375 uint64_t gich_base_address; 376 uint32_t vgic_interrupt; 377 uint64_t gicr_base_address; 378 uint64_t arm_mpidr; 379 } QEMU_PACKED; 380 381 typedef struct AcpiMadtGenericInterrupt AcpiMadtGenericInterrupt; 382 383 struct AcpiMadtGenericDistributor { 384 ACPI_SUB_HEADER_DEF 385 uint16_t reserved; 386 uint32_t gic_id; 387 uint64_t base_address; 388 uint32_t global_irq_base; 389 /* ACPI 5.1 Errata 1228 Present GIC version in MADT table */ 390 uint8_t version; 391 uint8_t reserved2[3]; 392 } QEMU_PACKED; 393 394 typedef struct AcpiMadtGenericDistributor AcpiMadtGenericDistributor; 395 396 struct AcpiMadtGenericMsiFrame { 397 ACPI_SUB_HEADER_DEF 398 uint16_t reserved; 399 uint32_t gic_msi_frame_id; 400 uint64_t base_address; 401 uint32_t flags; 402 uint16_t spi_count; 403 uint16_t spi_base; 404 } QEMU_PACKED; 405 406 typedef struct AcpiMadtGenericMsiFrame AcpiMadtGenericMsiFrame; 407 408 struct AcpiMadtGenericRedistributor { 409 ACPI_SUB_HEADER_DEF 410 uint16_t reserved; 411 uint64_t base_address; 412 uint32_t range_length; 413 } QEMU_PACKED; 414 415 typedef struct AcpiMadtGenericRedistributor AcpiMadtGenericRedistributor; 416 417 struct AcpiMadtGenericTranslator { 418 ACPI_SUB_HEADER_DEF 419 uint16_t reserved; 420 uint32_t translation_id; 421 uint64_t base_address; 422 uint32_t reserved2; 423 } QEMU_PACKED; 424 425 typedef struct AcpiMadtGenericTranslator AcpiMadtGenericTranslator; 426 427 /* 428 * Generic Timer Description Table (GTDT) 429 */ 430 431 #define ACPI_GTDT_INTERRUPT_MODE (1 << 0) 432 #define ACPI_GTDT_INTERRUPT_POLARITY (1 << 1) 433 #define ACPI_GTDT_ALWAYS_ON (1 << 2) 434 435 /* Triggering */ 436 437 #define ACPI_LEVEL_SENSITIVE ((uint8_t) 0x00) 438 #define ACPI_EDGE_SENSITIVE ((uint8_t) 0x01) 439 440 /* Polarity */ 441 442 #define ACPI_ACTIVE_HIGH ((uint8_t) 0x00) 443 #define ACPI_ACTIVE_LOW ((uint8_t) 0x01) 444 #define ACPI_ACTIVE_BOTH ((uint8_t) 0x02) 445 446 struct AcpiGenericTimerTable { 447 ACPI_TABLE_HEADER_DEF 448 uint64_t counter_block_addresss; 449 uint32_t reserved; 450 uint32_t secure_el1_interrupt; 451 uint32_t secure_el1_flags; 452 uint32_t non_secure_el1_interrupt; 453 uint32_t non_secure_el1_flags; 454 uint32_t virtual_timer_interrupt; 455 uint32_t virtual_timer_flags; 456 uint32_t non_secure_el2_interrupt; 457 uint32_t non_secure_el2_flags; 458 uint64_t counter_read_block_address; 459 uint32_t platform_timer_count; 460 uint32_t platform_timer_offset; 461 } QEMU_PACKED; 462 typedef struct AcpiGenericTimerTable AcpiGenericTimerTable; 463 464 /* 465 * HPET Description Table 466 */ 467 struct Acpi20Hpet { 468 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 469 uint32_t timer_block_id; 470 Acpi20GenericAddress addr; 471 uint8_t hpet_number; 472 uint16_t min_tick; 473 uint8_t page_protect; 474 } QEMU_PACKED; 475 typedef struct Acpi20Hpet Acpi20Hpet; 476 477 /* 478 * SRAT (NUMA topology description) table 479 */ 480 481 struct AcpiSystemResourceAffinityTable 482 { 483 ACPI_TABLE_HEADER_DEF 484 uint32_t reserved1; 485 uint32_t reserved2[2]; 486 } QEMU_PACKED; 487 typedef struct AcpiSystemResourceAffinityTable AcpiSystemResourceAffinityTable; 488 489 #define ACPI_SRAT_PROCESSOR_APIC 0 490 #define ACPI_SRAT_MEMORY 1 491 #define ACPI_SRAT_PROCESSOR_x2APIC 2 492 #define ACPI_SRAT_PROCESSOR_GICC 3 493 494 struct AcpiSratProcessorAffinity 495 { 496 ACPI_SUB_HEADER_DEF 497 uint8_t proximity_lo; 498 uint8_t local_apic_id; 499 uint32_t flags; 500 uint8_t local_sapic_eid; 501 uint8_t proximity_hi[3]; 502 uint32_t reserved; 503 } QEMU_PACKED; 504 typedef struct AcpiSratProcessorAffinity AcpiSratProcessorAffinity; 505 506 struct AcpiSratProcessorX2ApicAffinity { 507 ACPI_SUB_HEADER_DEF 508 uint16_t reserved; 509 uint32_t proximity_domain; 510 uint32_t x2apic_id; 511 uint32_t flags; 512 uint32_t clk_domain; 513 uint32_t reserved2; 514 } QEMU_PACKED; 515 typedef struct AcpiSratProcessorX2ApicAffinity AcpiSratProcessorX2ApicAffinity; 516 517 struct AcpiSratMemoryAffinity 518 { 519 ACPI_SUB_HEADER_DEF 520 uint32_t proximity; 521 uint16_t reserved1; 522 uint64_t base_addr; 523 uint64_t range_length; 524 uint32_t reserved2; 525 uint32_t flags; 526 uint32_t reserved3[2]; 527 } QEMU_PACKED; 528 typedef struct AcpiSratMemoryAffinity AcpiSratMemoryAffinity; 529 530 struct AcpiSratProcessorGiccAffinity 531 { 532 ACPI_SUB_HEADER_DEF 533 uint32_t proximity; 534 uint32_t acpi_processor_uid; 535 uint32_t flags; 536 uint32_t clock_domain; 537 } QEMU_PACKED; 538 539 typedef struct AcpiSratProcessorGiccAffinity AcpiSratProcessorGiccAffinity; 540 541 /* PCI fw r3.0 MCFG table. */ 542 /* Subtable */ 543 struct AcpiMcfgAllocation { 544 uint64_t address; /* Base address, processor-relative */ 545 uint16_t pci_segment; /* PCI segment group number */ 546 uint8_t start_bus_number; /* Starting PCI Bus number */ 547 uint8_t end_bus_number; /* Final PCI Bus number */ 548 uint32_t reserved; 549 } QEMU_PACKED; 550 typedef struct AcpiMcfgAllocation AcpiMcfgAllocation; 551 552 struct AcpiTableMcfg { 553 ACPI_TABLE_HEADER_DEF; 554 uint8_t reserved[8]; 555 AcpiMcfgAllocation allocation[0]; 556 } QEMU_PACKED; 557 typedef struct AcpiTableMcfg AcpiTableMcfg; 558 559 /* 560 * TCPA Description Table 561 * 562 * Following Level 00, Rev 00.37 of specs: 563 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 564 */ 565 struct Acpi20Tcpa { 566 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 567 uint16_t platform_class; 568 uint32_t log_area_minimum_length; 569 uint64_t log_area_start_address; 570 } QEMU_PACKED; 571 typedef struct Acpi20Tcpa Acpi20Tcpa; 572 573 /* 574 * TPM2 575 * 576 * Following Level 00, Rev 00.37 of specs: 577 * http://www.trustedcomputinggroup.org/resources/tcg_acpi_specification 578 */ 579 struct Acpi20TPM2 { 580 ACPI_TABLE_HEADER_DEF 581 uint16_t platform_class; 582 uint16_t reserved; 583 uint64_t control_area_address; 584 uint32_t start_method; 585 } QEMU_PACKED; 586 typedef struct Acpi20TPM2 Acpi20TPM2; 587 588 /* DMAR - DMA Remapping table r2.2 */ 589 struct AcpiTableDmar { 590 ACPI_TABLE_HEADER_DEF 591 uint8_t host_address_width; /* Maximum DMA physical addressability */ 592 uint8_t flags; 593 uint8_t reserved[10]; 594 } QEMU_PACKED; 595 typedef struct AcpiTableDmar AcpiTableDmar; 596 597 /* Masks for Flags field above */ 598 #define ACPI_DMAR_INTR_REMAP 1 599 #define ACPI_DMAR_X2APIC_OPT_OUT (1 << 1) 600 601 /* Values for sub-structure type for DMAR */ 602 enum { 603 ACPI_DMAR_TYPE_HARDWARE_UNIT = 0, /* DRHD */ 604 ACPI_DMAR_TYPE_RESERVED_MEMORY = 1, /* RMRR */ 605 ACPI_DMAR_TYPE_ATSR = 2, /* ATSR */ 606 ACPI_DMAR_TYPE_HARDWARE_AFFINITY = 3, /* RHSR */ 607 ACPI_DMAR_TYPE_ANDD = 4, /* ANDD */ 608 ACPI_DMAR_TYPE_RESERVED = 5 /* Reserved for furture use */ 609 }; 610 611 /* 612 * Sub-structures for DMAR 613 */ 614 615 /* Device scope structure for DRHD. */ 616 struct AcpiDmarDeviceScope { 617 uint8_t entry_type; 618 uint8_t length; 619 uint16_t reserved; 620 uint8_t enumeration_id; 621 uint8_t bus; 622 uint16_t path[0]; /* list of dev:func pairs */ 623 } QEMU_PACKED; 624 typedef struct AcpiDmarDeviceScope AcpiDmarDeviceScope; 625 626 /* Type 0: Hardware Unit Definition */ 627 struct AcpiDmarHardwareUnit { 628 uint16_t type; 629 uint16_t length; 630 uint8_t flags; 631 uint8_t reserved; 632 uint16_t pci_segment; /* The PCI Segment associated with this unit */ 633 uint64_t address; /* Base address of remapping hardware register-set */ 634 AcpiDmarDeviceScope scope[0]; 635 } QEMU_PACKED; 636 typedef struct AcpiDmarHardwareUnit AcpiDmarHardwareUnit; 637 638 /* Masks for Flags field above */ 639 #define ACPI_DMAR_INCLUDE_PCI_ALL 1 640 641 /* 642 * Input Output Remapping Table (IORT) 643 * Conforms to "IO Remapping Table System Software on ARM Platforms", 644 * Document number: ARM DEN 0049B, October 2015 645 */ 646 647 struct AcpiIortTable { 648 ACPI_TABLE_HEADER_DEF /* ACPI common table header */ 649 uint32_t node_count; 650 uint32_t node_offset; 651 uint32_t reserved; 652 } QEMU_PACKED; 653 typedef struct AcpiIortTable AcpiIortTable; 654 655 /* 656 * IORT node types 657 */ 658 659 #define ACPI_IORT_NODE_HEADER_DEF /* Node format common fields */ \ 660 uint8_t type; \ 661 uint16_t length; \ 662 uint8_t revision; \ 663 uint32_t reserved; \ 664 uint32_t mapping_count; \ 665 uint32_t mapping_offset; 666 667 /* Values for node Type above */ 668 enum { 669 ACPI_IORT_NODE_ITS_GROUP = 0x00, 670 ACPI_IORT_NODE_NAMED_COMPONENT = 0x01, 671 ACPI_IORT_NODE_PCI_ROOT_COMPLEX = 0x02, 672 ACPI_IORT_NODE_SMMU = 0x03, 673 ACPI_IORT_NODE_SMMU_V3 = 0x04 674 }; 675 676 struct AcpiIortIdMapping { 677 uint32_t input_base; 678 uint32_t id_count; 679 uint32_t output_base; 680 uint32_t output_reference; 681 uint32_t flags; 682 } QEMU_PACKED; 683 typedef struct AcpiIortIdMapping AcpiIortIdMapping; 684 685 struct AcpiIortMemoryAccess { 686 uint32_t cache_coherency; 687 uint8_t hints; 688 uint16_t reserved; 689 uint8_t memory_flags; 690 } QEMU_PACKED; 691 typedef struct AcpiIortMemoryAccess AcpiIortMemoryAccess; 692 693 struct AcpiIortItsGroup { 694 ACPI_IORT_NODE_HEADER_DEF 695 uint32_t its_count; 696 uint32_t identifiers[0]; 697 } QEMU_PACKED; 698 typedef struct AcpiIortItsGroup AcpiIortItsGroup; 699 700 struct AcpiIortRC { 701 ACPI_IORT_NODE_HEADER_DEF 702 AcpiIortMemoryAccess memory_properties; 703 uint32_t ats_attribute; 704 uint32_t pci_segment_number; 705 AcpiIortIdMapping id_mapping_array[0]; 706 } QEMU_PACKED; 707 typedef struct AcpiIortRC AcpiIortRC; 708 709 #endif 710