10553d895SMarkus Armbruster #ifndef HW_ARM_ALLWINNER_A10_H 20553d895SMarkus Armbruster #define HW_ARM_ALLWINNER_A10_H 39158fa54Sliguang 49158fa54Sliguang #include "qemu/error-report.h" 59158fa54Sliguang #include "hw/char/serial.h" 612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 79158fa54Sliguang #include "hw/timer/allwinner-a10-pit.h" 89158fa54Sliguang #include "hw/intc/allwinner-a10-pic.h" 9db7dfd4cSBeniamino Galvani #include "hw/net/allwinner_emac.h" 10dca62576SPeter Crosthwaite #include "hw/ide/pci.h" 11dca62576SPeter Crosthwaite #include "hw/ide/ahci.h" 129158fa54Sliguang 139158fa54Sliguang #include "sysemu/sysemu.h" 14*ec150c7eSMarkus Armbruster #include "target/arm/cpu.h" 159158fa54Sliguang 169158fa54Sliguang 179158fa54Sliguang #define AW_A10_PIC_REG_BASE 0x01c20400 189158fa54Sliguang #define AW_A10_PIT_REG_BASE 0x01c20c00 199158fa54Sliguang #define AW_A10_UART0_REG_BASE 0x01c28000 20db7dfd4cSBeniamino Galvani #define AW_A10_EMAC_BASE 0x01c0b000 21dca62576SPeter Crosthwaite #define AW_A10_SATA_BASE 0x01c18000 229158fa54Sliguang 239158fa54Sliguang #define AW_A10_SDRAM_BASE 0x40000000 249158fa54Sliguang 259158fa54Sliguang #define TYPE_AW_A10 "allwinner-a10" 269158fa54Sliguang #define AW_A10(obj) OBJECT_CHECK(AwA10State, (obj), TYPE_AW_A10) 279158fa54Sliguang 289158fa54Sliguang typedef struct AwA10State { 299158fa54Sliguang /*< private >*/ 309158fa54Sliguang DeviceState parent_obj; 319158fa54Sliguang /*< public >*/ 329158fa54Sliguang 339158fa54Sliguang ARMCPU cpu; 349158fa54Sliguang qemu_irq irq[AW_A10_PIC_INT_NR]; 359158fa54Sliguang AwA10PITState timer; 369158fa54Sliguang AwA10PICState intc; 37db7dfd4cSBeniamino Galvani AwEmacState emac; 38dca62576SPeter Crosthwaite AllwinnerAHCIState sata; 39ead07aa4SPhilippe Mathieu-Daudé MemoryRegion sram_a; 409158fa54Sliguang } AwA10State; 419158fa54Sliguang 429158fa54Sliguang #endif 43