10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * Samsung exynos4210 SoC emulation 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 50d09e41aSPaolo Bonzini * Maksim Kozlov <m.kozlov@samsung.com> 60d09e41aSPaolo Bonzini * Evgeny Voevodin <e.voevodin@samsung.com> 70d09e41aSPaolo Bonzini * Igor Mitsyanko <i.mitsyanko@samsung.com> 80d09e41aSPaolo Bonzini * 90d09e41aSPaolo Bonzini * 100d09e41aSPaolo Bonzini * This program is free software; you can redistribute it and/or modify it 110d09e41aSPaolo Bonzini * under the terms of the GNU General Public License as published by the 120d09e41aSPaolo Bonzini * Free Software Foundation; either version 2 of the License, or 130d09e41aSPaolo Bonzini * (at your option) any later version. 140d09e41aSPaolo Bonzini * 150d09e41aSPaolo Bonzini * This program is distributed in the hope that it will be useful, but WITHOUT 160d09e41aSPaolo Bonzini * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 170d09e41aSPaolo Bonzini * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 180d09e41aSPaolo Bonzini * for more details. 190d09e41aSPaolo Bonzini * 200d09e41aSPaolo Bonzini * You should have received a copy of the GNU General Public License along 210d09e41aSPaolo Bonzini * with this program; if not, see <http://www.gnu.org/licenses/>. 220d09e41aSPaolo Bonzini */ 230d09e41aSPaolo Bonzini 242a6a4076SMarkus Armbruster #ifndef EXYNOS4210_H 252a6a4076SMarkus Armbruster #define EXYNOS4210_H 260d09e41aSPaolo Bonzini 27dab15fbeSGuenter Roeck #include "hw/or-irq.h" 28ec150c7eSMarkus Armbruster #include "hw/sysbus.h" 295b241728SPeter Maydell #include "hw/cpu/a9mpcore.h" 3078cb12a9SPeter Maydell #include "hw/intc/exynos4210_gic.h" 31cebef07dSPeter Maydell #include "hw/intc/exynos4210_combiner.h" 327582d930SPeter Maydell #include "hw/core/split-irq.h" 3385c90d45SPhilippe Mathieu-Daudé #include "hw/arm/boot.h" 34db1015e9SEduardo Habkost #include "qom/object.h" 350d09e41aSPaolo Bonzini 360d09e41aSPaolo Bonzini #define EXYNOS4210_NCPUS 2 370d09e41aSPaolo Bonzini 380d09e41aSPaolo Bonzini #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000 390d09e41aSPaolo Bonzini #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000 400d09e41aSPaolo Bonzini #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */ 410d09e41aSPaolo Bonzini 420d09e41aSPaolo Bonzini #define EXYNOS4210_IROM_BASE_ADDR 0x00000000 430d09e41aSPaolo Bonzini #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */ 440d09e41aSPaolo Bonzini #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000 450d09e41aSPaolo Bonzini #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */ 460d09e41aSPaolo Bonzini 470d09e41aSPaolo Bonzini #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000 480d09e41aSPaolo Bonzini #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */ 490d09e41aSPaolo Bonzini 500d09e41aSPaolo Bonzini /* Secondary CPU startup code is in IROM memory */ 510d09e41aSPaolo Bonzini #define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR 520d09e41aSPaolo Bonzini #define EXYNOS4210_SMP_BOOT_SIZE 0x1000 530d09e41aSPaolo Bonzini #define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR 540d09e41aSPaolo Bonzini /* Secondary CPU polling address to get loader start from */ 550d09e41aSPaolo Bonzini #define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814 560d09e41aSPaolo Bonzini 570d09e41aSPaolo Bonzini #define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000 580d09e41aSPaolo Bonzini #define EXYNOS4210_L2X0_BASE_ADDR 0x10502000 590d09e41aSPaolo Bonzini 600d09e41aSPaolo Bonzini /* 610d09e41aSPaolo Bonzini * exynos4210 IRQ subsystem stub definitions. 620d09e41aSPaolo Bonzini */ 630d09e41aSPaolo Bonzini #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */ 640d09e41aSPaolo Bonzini 650d09e41aSPaolo Bonzini #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64 660d09e41aSPaolo Bonzini #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16 670d09e41aSPaolo Bonzini #define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \ 680d09e41aSPaolo Bonzini (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8) 690d09e41aSPaolo Bonzini #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ 700d09e41aSPaolo Bonzini (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) 710d09e41aSPaolo Bonzini 720d09e41aSPaolo Bonzini #define EXYNOS4210_I2C_NUMBER 9 730d09e41aSPaolo Bonzini 74dab15fbeSGuenter Roeck #define EXYNOS4210_NUM_DMA 3 75dab15fbeSGuenter Roeck 767582d930SPeter Maydell /* 777582d930SPeter Maydell * We need one splitter for every external combiner input, plus 7876621953SPeter Maydell * one for every non-zero entry in combiner_grp_to_gic_id[], 7976621953SPeter Maydell * minus one for every external combiner ID in second or later 8076621953SPeter Maydell * places in a combinermap[] line. 817582d930SPeter Maydell * We'll assert in exynos4210_init_board_irqs() if this is wrong. 827582d930SPeter Maydell */ 8376621953SPeter Maydell #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) 847582d930SPeter Maydell 85db1015e9SEduardo Habkost struct Exynos4210State { 8698e4f4fdSPhilippe Mathieu-Daudé /*< private >*/ 8798e4f4fdSPhilippe Mathieu-Daudé SysBusDevice parent_obj; 8898e4f4fdSPhilippe Mathieu-Daudé /*< public >*/ 890d09e41aSPaolo Bonzini ARMCPU *cpu[EXYNOS4210_NCPUS]; 90771dee52SPeter Maydell qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; 910d09e41aSPaolo Bonzini 920d09e41aSPaolo Bonzini MemoryRegion chipid_mem; 930d09e41aSPaolo Bonzini MemoryRegion iram_mem; 940d09e41aSPaolo Bonzini MemoryRegion irom_mem; 950d09e41aSPaolo Bonzini MemoryRegion irom_alias_mem; 960d09e41aSPaolo Bonzini MemoryRegion boot_secondary; 970d09e41aSPaolo Bonzini MemoryRegion bootreg_mem; 98a5c82852SAndreas Färber I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; 99e844f0c5SPhilippe Mathieu-Daudé OrIRQState pl330_irq_orgate[EXYNOS4210_NUM_DMA]; 100e844f0c5SPhilippe Mathieu-Daudé OrIRQState cpu_irq_orgate[EXYNOS4210_NCPUS]; 1015b241728SPeter Maydell A9MPPrivState a9mpcore; 10278cb12a9SPeter Maydell Exynos4210GicState ext_gic; 103cebef07dSPeter Maydell Exynos4210CombinerState int_combiner; 104cebef07dSPeter Maydell Exynos4210CombinerState ext_combiner; 1057582d930SPeter Maydell SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; 106db1015e9SEduardo Habkost }; 1070d09e41aSPaolo Bonzini 10898e4f4fdSPhilippe Mathieu-Daudé #define TYPE_EXYNOS4210_SOC "exynos4210" 1098063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210_SOC) 11098e4f4fdSPhilippe Mathieu-Daudé 1110d09e41aSPaolo Bonzini void exynos4210_write_secondary(ARMCPU *cpu, 1120d09e41aSPaolo Bonzini const struct arm_boot_info *info); 1130d09e41aSPaolo Bonzini 1140d09e41aSPaolo Bonzini /* Get IRQ number from exynos4210 IRQ subsystem stub. 1150d09e41aSPaolo Bonzini * To identify IRQ source use internal combiner group and bit number 1160d09e41aSPaolo Bonzini * grp - group number 1170d09e41aSPaolo Bonzini * bit - bit number inside group */ 1180d09e41aSPaolo Bonzini uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); 1190d09e41aSPaolo Bonzini 1200d09e41aSPaolo Bonzini /* 1210d09e41aSPaolo Bonzini * exynos4210 UART 1220d09e41aSPaolo Bonzini */ 1230d09e41aSPaolo Bonzini DeviceState *exynos4210_uart_create(hwaddr addr, 1240d09e41aSPaolo Bonzini int fifo_size, 1250d09e41aSPaolo Bonzini int channel, 1260ec7b3e7SMarc-André Lureau Chardev *chr, 1270d09e41aSPaolo Bonzini qemu_irq irq); 1280d09e41aSPaolo Bonzini 1292a6a4076SMarkus Armbruster #endif /* EXYNOS4210_H */ 130