1 /* 2 * Samsung exynos4210 SoC emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. All rights reserved. 5 * Maksim Kozlov <m.kozlov@samsung.com> 6 * Evgeny Voevodin <e.voevodin@samsung.com> 7 * Igor Mitsyanko <i.mitsyanko@samsung.com> 8 * 9 * 10 * This program is free software; you can redistribute it and/or modify it 11 * under the terms of the GNU General Public License as published by the 12 * Free Software Foundation; either version 2 of the License, or 13 * (at your option) any later version. 14 * 15 * This program is distributed in the hope that it will be useful, but WITHOUT 16 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 * for more details. 19 * 20 * You should have received a copy of the GNU General Public License along 21 * with this program; if not, see <http://www.gnu.org/licenses/>. 22 */ 23 24 #ifndef EXYNOS4210_H 25 #define EXYNOS4210_H 26 27 #include "hw/or-irq.h" 28 #include "hw/sysbus.h" 29 #include "target/arm/cpu-qom.h" 30 31 #define EXYNOS4210_NCPUS 2 32 33 #define EXYNOS4210_DRAM0_BASE_ADDR 0x40000000 34 #define EXYNOS4210_DRAM1_BASE_ADDR 0xa0000000 35 #define EXYNOS4210_DRAM_MAX_SIZE 0x60000000 /* 1.5 GB */ 36 37 #define EXYNOS4210_IROM_BASE_ADDR 0x00000000 38 #define EXYNOS4210_IROM_SIZE 0x00010000 /* 64 KB */ 39 #define EXYNOS4210_IROM_MIRROR_BASE_ADDR 0x02000000 40 #define EXYNOS4210_IROM_MIRROR_SIZE 0x00010000 /* 64 KB */ 41 42 #define EXYNOS4210_IRAM_BASE_ADDR 0x02020000 43 #define EXYNOS4210_IRAM_SIZE 0x00020000 /* 128 KB */ 44 45 /* Secondary CPU startup code is in IROM memory */ 46 #define EXYNOS4210_SMP_BOOT_ADDR EXYNOS4210_IROM_BASE_ADDR 47 #define EXYNOS4210_SMP_BOOT_SIZE 0x1000 48 #define EXYNOS4210_BASE_BOOT_ADDR EXYNOS4210_DRAM0_BASE_ADDR 49 /* Secondary CPU polling address to get loader start from */ 50 #define EXYNOS4210_SECOND_CPU_BOOTREG 0x10020814 51 52 #define EXYNOS4210_SMP_PRIVATE_BASE_ADDR 0x10500000 53 #define EXYNOS4210_L2X0_BASE_ADDR 0x10502000 54 55 /* 56 * exynos4210 IRQ subsystem stub definitions. 57 */ 58 #define EXYNOS4210_IRQ_GATE_NINPUTS 2 /* Internal and External GIC */ 59 60 #define EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ 64 61 #define EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ 16 62 #define EXYNOS4210_MAX_INT_COMBINER_IN_IRQ \ 63 (EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ * 8) 64 #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ 65 (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) 66 67 #define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) 68 #define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) 69 #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ 70 ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) 71 72 /* IRQs number for external and internal GIC */ 73 #define EXYNOS4210_EXT_GIC_NIRQ (160-32) 74 #define EXYNOS4210_INT_GIC_NIRQ 64 75 76 #define EXYNOS4210_I2C_NUMBER 9 77 78 #define EXYNOS4210_NUM_DMA 3 79 80 typedef struct Exynos4210Irq { 81 qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; 82 qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; 83 qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; 84 qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; 85 qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; 86 } Exynos4210Irq; 87 88 typedef struct Exynos4210State { 89 /*< private >*/ 90 SysBusDevice parent_obj; 91 /*< public >*/ 92 ARMCPU *cpu[EXYNOS4210_NCPUS]; 93 Exynos4210Irq irqs; 94 qemu_irq *irq_table; 95 96 MemoryRegion chipid_mem; 97 MemoryRegion iram_mem; 98 MemoryRegion irom_mem; 99 MemoryRegion irom_alias_mem; 100 MemoryRegion boot_secondary; 101 MemoryRegion bootreg_mem; 102 I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; 103 qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; 104 } Exynos4210State; 105 106 #define TYPE_EXYNOS4210_SOC "exynos4210" 107 #define EXYNOS4210_SOC(obj) \ 108 OBJECT_CHECK(Exynos4210State, obj, TYPE_EXYNOS4210_SOC) 109 110 void exynos4210_write_secondary(ARMCPU *cpu, 111 const struct arm_boot_info *info); 112 113 /* Initialize exynos4210 IRQ subsystem stub */ 114 qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); 115 116 /* Initialize board IRQs. 117 * These IRQs contain splitted Int/External Combiner and External Gic IRQs */ 118 void exynos4210_init_board_irqs(Exynos4210Irq *s); 119 120 /* Get IRQ number from exynos4210 IRQ subsystem stub. 121 * To identify IRQ source use internal combiner group and bit number 122 * grp - group number 123 * bit - bit number inside group */ 124 uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); 125 126 /* 127 * Get Combiner input GPIO into irqs structure 128 */ 129 void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, 130 int ext); 131 132 /* 133 * exynos4210 UART 134 */ 135 DeviceState *exynos4210_uart_create(hwaddr addr, 136 int fifo_size, 137 int channel, 138 Chardev *chr, 139 qemu_irq irq); 140 141 #endif /* EXYNOS4210_H */ 142