10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * Intel XScale PXA255/270 processor support. 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (c) 2006 Openedhand Ltd. 50d09e41aSPaolo Bonzini * Written by Andrzej Zaborowski <balrog@zabor.org> 60d09e41aSPaolo Bonzini * 70d09e41aSPaolo Bonzini * This code is licensed under the GNU GPL v2. 80d09e41aSPaolo Bonzini */ 9175de524SMarkus Armbruster 100d09e41aSPaolo Bonzini #ifndef PXA_H 11175de524SMarkus Armbruster #define PXA_H 120d09e41aSPaolo Bonzini 130d09e41aSPaolo Bonzini #include "exec/memory.h" 14fcf5ef2aSThomas Huth #include "target/arm/cpu-qom.h" 152274e7ddSPhilippe Mathieu-Daudé #include "hw/pcmcia.h" 16db1015e9SEduardo Habkost #include "qom/object.h" 170d09e41aSPaolo Bonzini 180d09e41aSPaolo Bonzini /* Interrupt numbers */ 190d09e41aSPaolo Bonzini # define PXA2XX_PIC_SSP3 0 200d09e41aSPaolo Bonzini # define PXA2XX_PIC_USBH2 2 210d09e41aSPaolo Bonzini # define PXA2XX_PIC_USBH1 3 220d09e41aSPaolo Bonzini # define PXA2XX_PIC_KEYPAD 4 230d09e41aSPaolo Bonzini # define PXA2XX_PIC_PWRI2C 6 240d09e41aSPaolo Bonzini # define PXA25X_PIC_HWUART 7 250d09e41aSPaolo Bonzini # define PXA27X_PIC_OST_4_11 7 260d09e41aSPaolo Bonzini # define PXA2XX_PIC_GPIO_0 8 270d09e41aSPaolo Bonzini # define PXA2XX_PIC_GPIO_1 9 280d09e41aSPaolo Bonzini # define PXA2XX_PIC_GPIO_X 10 290d09e41aSPaolo Bonzini # define PXA2XX_PIC_I2S 13 300d09e41aSPaolo Bonzini # define PXA26X_PIC_ASSP 15 310d09e41aSPaolo Bonzini # define PXA25X_PIC_NSSP 16 320d09e41aSPaolo Bonzini # define PXA27X_PIC_SSP2 16 330d09e41aSPaolo Bonzini # define PXA2XX_PIC_LCD 17 340d09e41aSPaolo Bonzini # define PXA2XX_PIC_I2C 18 350d09e41aSPaolo Bonzini # define PXA2XX_PIC_ICP 19 360d09e41aSPaolo Bonzini # define PXA2XX_PIC_STUART 20 370d09e41aSPaolo Bonzini # define PXA2XX_PIC_BTUART 21 380d09e41aSPaolo Bonzini # define PXA2XX_PIC_FFUART 22 390d09e41aSPaolo Bonzini # define PXA2XX_PIC_MMC 23 400d09e41aSPaolo Bonzini # define PXA2XX_PIC_SSP 24 410d09e41aSPaolo Bonzini # define PXA2XX_PIC_DMA 25 420d09e41aSPaolo Bonzini # define PXA2XX_PIC_OST_0 26 430d09e41aSPaolo Bonzini # define PXA2XX_PIC_RTC1HZ 30 440d09e41aSPaolo Bonzini # define PXA2XX_PIC_RTCALARM 31 450d09e41aSPaolo Bonzini 460d09e41aSPaolo Bonzini /* DMA requests */ 470d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_I2S 2 480d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_I2S 3 490d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_BTUART 4 500d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_BTUART 5 510d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_FFUART 6 520d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_FFUART 7 530d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_SSP1 13 540d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_SSP1 14 550d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_SSP2 15 560d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_SSP2 16 570d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_ICP 17 580d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_ICP 18 590d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_STUART 19 600d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_STUART 20 610d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_MMCI 21 620d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_MMCI 22 630d09e41aSPaolo Bonzini # define PXA2XX_USB_RQ(x) ((x) + 24) 640d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_SSP3 66 650d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_SSP3 67 660d09e41aSPaolo Bonzini 670d09e41aSPaolo Bonzini # define PXA2XX_SDRAM_BASE 0xa0000000 680d09e41aSPaolo Bonzini # define PXA2XX_INTERNAL_BASE 0x5c000000 690d09e41aSPaolo Bonzini # define PXA2XX_INTERNAL_SIZE 0x40000 700d09e41aSPaolo Bonzini 710d09e41aSPaolo Bonzini /* pxa2xx_pic.c */ 720d09e41aSPaolo Bonzini DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu); 730d09e41aSPaolo Bonzini 740d09e41aSPaolo Bonzini /* pxa2xx_gpio.c */ 750d09e41aSPaolo Bonzini DeviceState *pxa2xx_gpio_init(hwaddr base, 760d09e41aSPaolo Bonzini ARMCPU *cpu, DeviceState *pic, int lines); 770d09e41aSPaolo Bonzini void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); 780d09e41aSPaolo Bonzini 790d09e41aSPaolo Bonzini /* pxa2xx_dma.c */ 800d09e41aSPaolo Bonzini DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq); 810d09e41aSPaolo Bonzini DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq); 820d09e41aSPaolo Bonzini 830d09e41aSPaolo Bonzini /* pxa2xx_lcd.c */ 840d09e41aSPaolo Bonzini typedef struct PXA2xxLCDState PXA2xxLCDState; 850d09e41aSPaolo Bonzini PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, 860d09e41aSPaolo Bonzini hwaddr base, qemu_irq irq); 870d09e41aSPaolo Bonzini void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); 880d09e41aSPaolo Bonzini 890d09e41aSPaolo Bonzini /* pxa2xx_mmci.c */ 902d8eb5f8SEduardo Habkost #define TYPE_PXA2XX_MMCI "pxa2xx-mmci" 918063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxMMCIState, PXA2XX_MMCI) 922d8eb5f8SEduardo Habkost 930d09e41aSPaolo Bonzini PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, 940d09e41aSPaolo Bonzini hwaddr base, 95d7ebca74SPhilippe Mathieu-Daudé qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma); 960d09e41aSPaolo Bonzini void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, 970d09e41aSPaolo Bonzini qemu_irq coverswitch); 980d09e41aSPaolo Bonzini 990d09e41aSPaolo Bonzini /* pxa2xx_pcmcia.c */ 1002d8eb5f8SEduardo Habkost #define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia" 1018063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxPCMCIAState, PXA2XX_PCMCIA) 1022d8eb5f8SEduardo Habkost 1030d09e41aSPaolo Bonzini int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); 104853ca11dSAndreas Färber int pxa2xx_pcmcia_detach(void *opaque); 1050d09e41aSPaolo Bonzini void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); 1060d09e41aSPaolo Bonzini 1070d09e41aSPaolo Bonzini /* pxa2xx_keypad.c */ 1080d09e41aSPaolo Bonzini struct keymap { 109f57d6693SStefan Weil int8_t column; 110f57d6693SStefan Weil int8_t row; 1110d09e41aSPaolo Bonzini }; 1120d09e41aSPaolo Bonzini typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; 1130d09e41aSPaolo Bonzini PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem, 1140d09e41aSPaolo Bonzini hwaddr base, 1150d09e41aSPaolo Bonzini qemu_irq irq); 11652975c31SStefan Weil void pxa27x_register_keypad(PXA2xxKeyPadState *kp, 11752975c31SStefan Weil const struct keymap *map, int size); 1180d09e41aSPaolo Bonzini 1190d09e41aSPaolo Bonzini /* pxa2xx.c */ 120*c4d15af1SPhilippe Mathieu-Daudé #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 121*c4d15af1SPhilippe Mathieu-Daudé OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxI2CState, PXA2XX_I2C) 122*c4d15af1SPhilippe Mathieu-Daudé 1230d09e41aSPaolo Bonzini PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1240d09e41aSPaolo Bonzini qemu_irq irq, uint32_t page_size); 125a5c82852SAndreas Färber I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s); 1260d09e41aSPaolo Bonzini 1270d09e41aSPaolo Bonzini typedef struct PXA2xxI2SState PXA2xxI2SState; 1282d8eb5f8SEduardo Habkost 1292d8eb5f8SEduardo Habkost #define TYPE_PXA2XX_FIR "pxa2xx-fir" 1308063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(PXA2xxFIrState, PXA2XX_FIR) 1310d09e41aSPaolo Bonzini 1320d09e41aSPaolo Bonzini typedef struct { 1330d09e41aSPaolo Bonzini ARMCPU *cpu; 1340d09e41aSPaolo Bonzini DeviceState *pic; 1350d09e41aSPaolo Bonzini qemu_irq reset; 1360d09e41aSPaolo Bonzini MemoryRegion sdram; 1370d09e41aSPaolo Bonzini MemoryRegion internal; 1380d09e41aSPaolo Bonzini MemoryRegion cm_iomem; 1390d09e41aSPaolo Bonzini MemoryRegion mm_iomem; 1400d09e41aSPaolo Bonzini MemoryRegion pm_iomem; 1410d09e41aSPaolo Bonzini DeviceState *dma; 1420d09e41aSPaolo Bonzini DeviceState *gpio; 1430d09e41aSPaolo Bonzini PXA2xxLCDState *lcd; 1440d09e41aSPaolo Bonzini SSIBus **ssp; 1450d09e41aSPaolo Bonzini PXA2xxI2CState *i2c[2]; 1460d09e41aSPaolo Bonzini PXA2xxMMCIState *mmc; 1470d09e41aSPaolo Bonzini PXA2xxPCMCIAState *pcmcia[2]; 1480d09e41aSPaolo Bonzini PXA2xxI2SState *i2s; 1490d09e41aSPaolo Bonzini PXA2xxFIrState *fir; 1500d09e41aSPaolo Bonzini PXA2xxKeyPadState *kp; 1510d09e41aSPaolo Bonzini 1520d09e41aSPaolo Bonzini /* Power management */ 1530d09e41aSPaolo Bonzini hwaddr pm_base; 1540d09e41aSPaolo Bonzini uint32_t pm_regs[0x40]; 1550d09e41aSPaolo Bonzini 1560d09e41aSPaolo Bonzini /* Clock management */ 1570d09e41aSPaolo Bonzini hwaddr cm_base; 1580d09e41aSPaolo Bonzini uint32_t cm_regs[4]; 1590d09e41aSPaolo Bonzini uint32_t clkcfg; 1600d09e41aSPaolo Bonzini 1610d09e41aSPaolo Bonzini /* Memory management */ 1620d09e41aSPaolo Bonzini hwaddr mm_base; 1630d09e41aSPaolo Bonzini uint32_t mm_regs[0x1a]; 1640d09e41aSPaolo Bonzini 1650d09e41aSPaolo Bonzini /* Performance monitoring */ 1660d09e41aSPaolo Bonzini uint32_t pmnc; 1670d09e41aSPaolo Bonzini } PXA2xxState; 1680d09e41aSPaolo Bonzini 1690d09e41aSPaolo Bonzini struct PXA2xxI2SState { 1700d09e41aSPaolo Bonzini MemoryRegion iomem; 1710d09e41aSPaolo Bonzini qemu_irq irq; 1720d09e41aSPaolo Bonzini qemu_irq rx_dma; 1730d09e41aSPaolo Bonzini qemu_irq tx_dma; 1740d09e41aSPaolo Bonzini void (*data_req)(void *, int, int); 1750d09e41aSPaolo Bonzini 1760d09e41aSPaolo Bonzini uint32_t control[2]; 1770d09e41aSPaolo Bonzini uint32_t status; 1780d09e41aSPaolo Bonzini uint32_t mask; 1790d09e41aSPaolo Bonzini uint32_t clk; 1800d09e41aSPaolo Bonzini 1810d09e41aSPaolo Bonzini int enable; 1820d09e41aSPaolo Bonzini int rx_len; 1830d09e41aSPaolo Bonzini int tx_len; 1840d09e41aSPaolo Bonzini void (*codec_out)(void *, uint32_t); 1850d09e41aSPaolo Bonzini uint32_t (*codec_in)(void *); 1860d09e41aSPaolo Bonzini void *opaque; 1870d09e41aSPaolo Bonzini 1880d09e41aSPaolo Bonzini int fifo_len; 1890d09e41aSPaolo Bonzini uint32_t fifo[16]; 1900d09e41aSPaolo Bonzini }; 1910d09e41aSPaolo Bonzini 1920d09e41aSPaolo Bonzini # define PA_FMT "0x%08lx" 1930d09e41aSPaolo Bonzini 1942990bf5dSPhilippe Mathieu-Daudé PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision); 195abf8361cSPhilippe Mathieu-Daudé PXA2xxState *pxa255_init(unsigned int sdram_size); 1960d09e41aSPaolo Bonzini 1970d09e41aSPaolo Bonzini #endif /* PXA_H */ 198