10d09e41aSPaolo Bonzini /* 20d09e41aSPaolo Bonzini * Intel XScale PXA255/270 processor support. 30d09e41aSPaolo Bonzini * 40d09e41aSPaolo Bonzini * Copyright (c) 2006 Openedhand Ltd. 50d09e41aSPaolo Bonzini * Written by Andrzej Zaborowski <balrog@zabor.org> 60d09e41aSPaolo Bonzini * 70d09e41aSPaolo Bonzini * This code is licensed under the GNU GPL v2. 80d09e41aSPaolo Bonzini */ 9175de524SMarkus Armbruster 100d09e41aSPaolo Bonzini #ifndef PXA_H 11175de524SMarkus Armbruster #define PXA_H 120d09e41aSPaolo Bonzini 130d09e41aSPaolo Bonzini #include "exec/memory.h" 14*fcf5ef2aSThomas Huth #include "target/arm/cpu-qom.h" 150d09e41aSPaolo Bonzini 160d09e41aSPaolo Bonzini /* Interrupt numbers */ 170d09e41aSPaolo Bonzini # define PXA2XX_PIC_SSP3 0 180d09e41aSPaolo Bonzini # define PXA2XX_PIC_USBH2 2 190d09e41aSPaolo Bonzini # define PXA2XX_PIC_USBH1 3 200d09e41aSPaolo Bonzini # define PXA2XX_PIC_KEYPAD 4 210d09e41aSPaolo Bonzini # define PXA2XX_PIC_PWRI2C 6 220d09e41aSPaolo Bonzini # define PXA25X_PIC_HWUART 7 230d09e41aSPaolo Bonzini # define PXA27X_PIC_OST_4_11 7 240d09e41aSPaolo Bonzini # define PXA2XX_PIC_GPIO_0 8 250d09e41aSPaolo Bonzini # define PXA2XX_PIC_GPIO_1 9 260d09e41aSPaolo Bonzini # define PXA2XX_PIC_GPIO_X 10 270d09e41aSPaolo Bonzini # define PXA2XX_PIC_I2S 13 280d09e41aSPaolo Bonzini # define PXA26X_PIC_ASSP 15 290d09e41aSPaolo Bonzini # define PXA25X_PIC_NSSP 16 300d09e41aSPaolo Bonzini # define PXA27X_PIC_SSP2 16 310d09e41aSPaolo Bonzini # define PXA2XX_PIC_LCD 17 320d09e41aSPaolo Bonzini # define PXA2XX_PIC_I2C 18 330d09e41aSPaolo Bonzini # define PXA2XX_PIC_ICP 19 340d09e41aSPaolo Bonzini # define PXA2XX_PIC_STUART 20 350d09e41aSPaolo Bonzini # define PXA2XX_PIC_BTUART 21 360d09e41aSPaolo Bonzini # define PXA2XX_PIC_FFUART 22 370d09e41aSPaolo Bonzini # define PXA2XX_PIC_MMC 23 380d09e41aSPaolo Bonzini # define PXA2XX_PIC_SSP 24 390d09e41aSPaolo Bonzini # define PXA2XX_PIC_DMA 25 400d09e41aSPaolo Bonzini # define PXA2XX_PIC_OST_0 26 410d09e41aSPaolo Bonzini # define PXA2XX_PIC_RTC1HZ 30 420d09e41aSPaolo Bonzini # define PXA2XX_PIC_RTCALARM 31 430d09e41aSPaolo Bonzini 440d09e41aSPaolo Bonzini /* DMA requests */ 450d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_I2S 2 460d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_I2S 3 470d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_BTUART 4 480d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_BTUART 5 490d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_FFUART 6 500d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_FFUART 7 510d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_SSP1 13 520d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_SSP1 14 530d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_SSP2 15 540d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_SSP2 16 550d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_ICP 17 560d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_ICP 18 570d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_STUART 19 580d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_STUART 20 590d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_MMCI 21 600d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_MMCI 22 610d09e41aSPaolo Bonzini # define PXA2XX_USB_RQ(x) ((x) + 24) 620d09e41aSPaolo Bonzini # define PXA2XX_RX_RQ_SSP3 66 630d09e41aSPaolo Bonzini # define PXA2XX_TX_RQ_SSP3 67 640d09e41aSPaolo Bonzini 650d09e41aSPaolo Bonzini # define PXA2XX_SDRAM_BASE 0xa0000000 660d09e41aSPaolo Bonzini # define PXA2XX_INTERNAL_BASE 0x5c000000 670d09e41aSPaolo Bonzini # define PXA2XX_INTERNAL_SIZE 0x40000 680d09e41aSPaolo Bonzini 690d09e41aSPaolo Bonzini /* pxa2xx_pic.c */ 700d09e41aSPaolo Bonzini DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu); 710d09e41aSPaolo Bonzini 720d09e41aSPaolo Bonzini /* pxa2xx_gpio.c */ 730d09e41aSPaolo Bonzini DeviceState *pxa2xx_gpio_init(hwaddr base, 740d09e41aSPaolo Bonzini ARMCPU *cpu, DeviceState *pic, int lines); 750d09e41aSPaolo Bonzini void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); 760d09e41aSPaolo Bonzini 770d09e41aSPaolo Bonzini /* pxa2xx_dma.c */ 780d09e41aSPaolo Bonzini DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq); 790d09e41aSPaolo Bonzini DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq); 800d09e41aSPaolo Bonzini 810d09e41aSPaolo Bonzini /* pxa2xx_lcd.c */ 820d09e41aSPaolo Bonzini typedef struct PXA2xxLCDState PXA2xxLCDState; 830d09e41aSPaolo Bonzini PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, 840d09e41aSPaolo Bonzini hwaddr base, qemu_irq irq); 850d09e41aSPaolo Bonzini void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); 860d09e41aSPaolo Bonzini 870d09e41aSPaolo Bonzini /* pxa2xx_mmci.c */ 880d09e41aSPaolo Bonzini typedef struct PXA2xxMMCIState PXA2xxMMCIState; 890d09e41aSPaolo Bonzini PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, 900d09e41aSPaolo Bonzini hwaddr base, 914be74634SMarkus Armbruster BlockBackend *blk, qemu_irq irq, 920d09e41aSPaolo Bonzini qemu_irq rx_dma, qemu_irq tx_dma); 930d09e41aSPaolo Bonzini void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, 940d09e41aSPaolo Bonzini qemu_irq coverswitch); 950d09e41aSPaolo Bonzini 960d09e41aSPaolo Bonzini /* pxa2xx_pcmcia.c */ 970d09e41aSPaolo Bonzini typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; 980d09e41aSPaolo Bonzini PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, 990d09e41aSPaolo Bonzini hwaddr base); 1000d09e41aSPaolo Bonzini int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); 101853ca11dSAndreas Färber int pxa2xx_pcmcia_detach(void *opaque); 1020d09e41aSPaolo Bonzini void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); 1030d09e41aSPaolo Bonzini 1040d09e41aSPaolo Bonzini /* pxa2xx_keypad.c */ 1050d09e41aSPaolo Bonzini struct keymap { 106f57d6693SStefan Weil int8_t column; 107f57d6693SStefan Weil int8_t row; 1080d09e41aSPaolo Bonzini }; 1090d09e41aSPaolo Bonzini typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; 1100d09e41aSPaolo Bonzini PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem, 1110d09e41aSPaolo Bonzini hwaddr base, 1120d09e41aSPaolo Bonzini qemu_irq irq); 11352975c31SStefan Weil void pxa27x_register_keypad(PXA2xxKeyPadState *kp, 11452975c31SStefan Weil const struct keymap *map, int size); 1150d09e41aSPaolo Bonzini 1160d09e41aSPaolo Bonzini /* pxa2xx.c */ 1170d09e41aSPaolo Bonzini typedef struct PXA2xxI2CState PXA2xxI2CState; 1180d09e41aSPaolo Bonzini PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 1190d09e41aSPaolo Bonzini qemu_irq irq, uint32_t page_size); 120a5c82852SAndreas Färber I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s); 1210d09e41aSPaolo Bonzini 1220d09e41aSPaolo Bonzini typedef struct PXA2xxI2SState PXA2xxI2SState; 1230d09e41aSPaolo Bonzini typedef struct PXA2xxFIrState PXA2xxFIrState; 1240d09e41aSPaolo Bonzini 1250d09e41aSPaolo Bonzini typedef struct { 1260d09e41aSPaolo Bonzini ARMCPU *cpu; 1270d09e41aSPaolo Bonzini DeviceState *pic; 1280d09e41aSPaolo Bonzini qemu_irq reset; 1290d09e41aSPaolo Bonzini MemoryRegion sdram; 1300d09e41aSPaolo Bonzini MemoryRegion internal; 1310d09e41aSPaolo Bonzini MemoryRegion cm_iomem; 1320d09e41aSPaolo Bonzini MemoryRegion mm_iomem; 1330d09e41aSPaolo Bonzini MemoryRegion pm_iomem; 1340d09e41aSPaolo Bonzini DeviceState *dma; 1350d09e41aSPaolo Bonzini DeviceState *gpio; 1360d09e41aSPaolo Bonzini PXA2xxLCDState *lcd; 1370d09e41aSPaolo Bonzini SSIBus **ssp; 1380d09e41aSPaolo Bonzini PXA2xxI2CState *i2c[2]; 1390d09e41aSPaolo Bonzini PXA2xxMMCIState *mmc; 1400d09e41aSPaolo Bonzini PXA2xxPCMCIAState *pcmcia[2]; 1410d09e41aSPaolo Bonzini PXA2xxI2SState *i2s; 1420d09e41aSPaolo Bonzini PXA2xxFIrState *fir; 1430d09e41aSPaolo Bonzini PXA2xxKeyPadState *kp; 1440d09e41aSPaolo Bonzini 1450d09e41aSPaolo Bonzini /* Power management */ 1460d09e41aSPaolo Bonzini hwaddr pm_base; 1470d09e41aSPaolo Bonzini uint32_t pm_regs[0x40]; 1480d09e41aSPaolo Bonzini 1490d09e41aSPaolo Bonzini /* Clock management */ 1500d09e41aSPaolo Bonzini hwaddr cm_base; 1510d09e41aSPaolo Bonzini uint32_t cm_regs[4]; 1520d09e41aSPaolo Bonzini uint32_t clkcfg; 1530d09e41aSPaolo Bonzini 1540d09e41aSPaolo Bonzini /* Memory management */ 1550d09e41aSPaolo Bonzini hwaddr mm_base; 1560d09e41aSPaolo Bonzini uint32_t mm_regs[0x1a]; 1570d09e41aSPaolo Bonzini 1580d09e41aSPaolo Bonzini /* Performance monitoring */ 1590d09e41aSPaolo Bonzini uint32_t pmnc; 1600d09e41aSPaolo Bonzini } PXA2xxState; 1610d09e41aSPaolo Bonzini 1620d09e41aSPaolo Bonzini struct PXA2xxI2SState { 1630d09e41aSPaolo Bonzini MemoryRegion iomem; 1640d09e41aSPaolo Bonzini qemu_irq irq; 1650d09e41aSPaolo Bonzini qemu_irq rx_dma; 1660d09e41aSPaolo Bonzini qemu_irq tx_dma; 1670d09e41aSPaolo Bonzini void (*data_req)(void *, int, int); 1680d09e41aSPaolo Bonzini 1690d09e41aSPaolo Bonzini uint32_t control[2]; 1700d09e41aSPaolo Bonzini uint32_t status; 1710d09e41aSPaolo Bonzini uint32_t mask; 1720d09e41aSPaolo Bonzini uint32_t clk; 1730d09e41aSPaolo Bonzini 1740d09e41aSPaolo Bonzini int enable; 1750d09e41aSPaolo Bonzini int rx_len; 1760d09e41aSPaolo Bonzini int tx_len; 1770d09e41aSPaolo Bonzini void (*codec_out)(void *, uint32_t); 1780d09e41aSPaolo Bonzini uint32_t (*codec_in)(void *); 1790d09e41aSPaolo Bonzini void *opaque; 1800d09e41aSPaolo Bonzini 1810d09e41aSPaolo Bonzini int fifo_len; 1820d09e41aSPaolo Bonzini uint32_t fifo[16]; 1830d09e41aSPaolo Bonzini }; 1840d09e41aSPaolo Bonzini 1850d09e41aSPaolo Bonzini # define PA_FMT "0x%08lx" 1860d09e41aSPaolo Bonzini # define REG_FMT "0x" TARGET_FMT_plx 1870d09e41aSPaolo Bonzini 1880d09e41aSPaolo Bonzini PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, 1890d09e41aSPaolo Bonzini const char *revision); 1900d09e41aSPaolo Bonzini PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size); 1910d09e41aSPaolo Bonzini 1920d09e41aSPaolo Bonzini #endif /* PXA_H */ 193