1 /* 2 * Intel XScale PXA255/270 processor support. 3 * 4 * Copyright (c) 2006 Openedhand Ltd. 5 * Written by Andrzej Zaborowski <balrog@zabor.org> 6 * 7 * This code is licensed under the GNU GPL v2. 8 */ 9 10 #ifndef PXA_H 11 #define PXA_H 12 13 #include "exec/memory.h" 14 #include "target/arm/cpu-qom.h" 15 #include "hw/pcmcia.h" 16 #include "qom/object.h" 17 18 /* Interrupt numbers */ 19 # define PXA2XX_PIC_SSP3 0 20 # define PXA2XX_PIC_USBH2 2 21 # define PXA2XX_PIC_USBH1 3 22 # define PXA2XX_PIC_KEYPAD 4 23 # define PXA2XX_PIC_PWRI2C 6 24 # define PXA25X_PIC_HWUART 7 25 # define PXA27X_PIC_OST_4_11 7 26 # define PXA2XX_PIC_GPIO_0 8 27 # define PXA2XX_PIC_GPIO_1 9 28 # define PXA2XX_PIC_GPIO_X 10 29 # define PXA2XX_PIC_I2S 13 30 # define PXA26X_PIC_ASSP 15 31 # define PXA25X_PIC_NSSP 16 32 # define PXA27X_PIC_SSP2 16 33 # define PXA2XX_PIC_LCD 17 34 # define PXA2XX_PIC_I2C 18 35 # define PXA2XX_PIC_ICP 19 36 # define PXA2XX_PIC_STUART 20 37 # define PXA2XX_PIC_BTUART 21 38 # define PXA2XX_PIC_FFUART 22 39 # define PXA2XX_PIC_MMC 23 40 # define PXA2XX_PIC_SSP 24 41 # define PXA2XX_PIC_DMA 25 42 # define PXA2XX_PIC_OST_0 26 43 # define PXA2XX_PIC_RTC1HZ 30 44 # define PXA2XX_PIC_RTCALARM 31 45 46 /* DMA requests */ 47 # define PXA2XX_RX_RQ_I2S 2 48 # define PXA2XX_TX_RQ_I2S 3 49 # define PXA2XX_RX_RQ_BTUART 4 50 # define PXA2XX_TX_RQ_BTUART 5 51 # define PXA2XX_RX_RQ_FFUART 6 52 # define PXA2XX_TX_RQ_FFUART 7 53 # define PXA2XX_RX_RQ_SSP1 13 54 # define PXA2XX_TX_RQ_SSP1 14 55 # define PXA2XX_RX_RQ_SSP2 15 56 # define PXA2XX_TX_RQ_SSP2 16 57 # define PXA2XX_RX_RQ_ICP 17 58 # define PXA2XX_TX_RQ_ICP 18 59 # define PXA2XX_RX_RQ_STUART 19 60 # define PXA2XX_TX_RQ_STUART 20 61 # define PXA2XX_RX_RQ_MMCI 21 62 # define PXA2XX_TX_RQ_MMCI 22 63 # define PXA2XX_USB_RQ(x) ((x) + 24) 64 # define PXA2XX_RX_RQ_SSP3 66 65 # define PXA2XX_TX_RQ_SSP3 67 66 67 # define PXA2XX_SDRAM_BASE 0xa0000000 68 # define PXA2XX_INTERNAL_BASE 0x5c000000 69 # define PXA2XX_INTERNAL_SIZE 0x40000 70 71 /* pxa2xx_pic.c */ 72 DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu); 73 74 /* pxa2xx_gpio.c */ 75 DeviceState *pxa2xx_gpio_init(hwaddr base, 76 ARMCPU *cpu, DeviceState *pic, int lines); 77 void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler); 78 79 /* pxa2xx_dma.c */ 80 DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq); 81 DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq); 82 83 /* pxa2xx_lcd.c */ 84 typedef struct PXA2xxLCDState PXA2xxLCDState; 85 PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem, 86 hwaddr base, qemu_irq irq); 87 void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler); 88 89 /* pxa2xx_mmci.c */ 90 #define TYPE_PXA2XX_MMCI "pxa2xx-mmci" 91 typedef struct PXA2xxMMCIState PXA2xxMMCIState; 92 DECLARE_INSTANCE_CHECKER(PXA2xxMMCIState, PXA2XX_MMCI, 93 TYPE_PXA2XX_MMCI) 94 95 PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem, 96 hwaddr base, 97 qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma); 98 void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly, 99 qemu_irq coverswitch); 100 101 /* pxa2xx_pcmcia.c */ 102 #define TYPE_PXA2XX_PCMCIA "pxa2xx-pcmcia" 103 typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState; 104 DECLARE_INSTANCE_CHECKER(PXA2xxPCMCIAState, PXA2XX_PCMCIA, 105 TYPE_PXA2XX_PCMCIA) 106 107 PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem, 108 hwaddr base); 109 int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card); 110 int pxa2xx_pcmcia_detach(void *opaque); 111 void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq); 112 113 /* pxa2xx_keypad.c */ 114 struct keymap { 115 int8_t column; 116 int8_t row; 117 }; 118 typedef struct PXA2xxKeyPadState PXA2xxKeyPadState; 119 PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem, 120 hwaddr base, 121 qemu_irq irq); 122 void pxa27x_register_keypad(PXA2xxKeyPadState *kp, 123 const struct keymap *map, int size); 124 125 /* pxa2xx.c */ 126 typedef struct PXA2xxI2CState PXA2xxI2CState; 127 PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base, 128 qemu_irq irq, uint32_t page_size); 129 I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s); 130 131 #define TYPE_PXA2XX_I2C "pxa2xx_i2c" 132 typedef struct PXA2xxI2SState PXA2xxI2SState; 133 DECLARE_INSTANCE_CHECKER(PXA2xxI2CState, PXA2XX_I2C, 134 TYPE_PXA2XX_I2C) 135 136 #define TYPE_PXA2XX_FIR "pxa2xx-fir" 137 typedef struct PXA2xxFIrState PXA2xxFIrState; 138 DECLARE_INSTANCE_CHECKER(PXA2xxFIrState, PXA2XX_FIR, 139 TYPE_PXA2XX_FIR) 140 141 typedef struct { 142 ARMCPU *cpu; 143 DeviceState *pic; 144 qemu_irq reset; 145 MemoryRegion sdram; 146 MemoryRegion internal; 147 MemoryRegion cm_iomem; 148 MemoryRegion mm_iomem; 149 MemoryRegion pm_iomem; 150 DeviceState *dma; 151 DeviceState *gpio; 152 PXA2xxLCDState *lcd; 153 SSIBus **ssp; 154 PXA2xxI2CState *i2c[2]; 155 PXA2xxMMCIState *mmc; 156 PXA2xxPCMCIAState *pcmcia[2]; 157 PXA2xxI2SState *i2s; 158 PXA2xxFIrState *fir; 159 PXA2xxKeyPadState *kp; 160 161 /* Power management */ 162 hwaddr pm_base; 163 uint32_t pm_regs[0x40]; 164 165 /* Clock management */ 166 hwaddr cm_base; 167 uint32_t cm_regs[4]; 168 uint32_t clkcfg; 169 170 /* Memory management */ 171 hwaddr mm_base; 172 uint32_t mm_regs[0x1a]; 173 174 /* Performance monitoring */ 175 uint32_t pmnc; 176 } PXA2xxState; 177 178 struct PXA2xxI2SState { 179 MemoryRegion iomem; 180 qemu_irq irq; 181 qemu_irq rx_dma; 182 qemu_irq tx_dma; 183 void (*data_req)(void *, int, int); 184 185 uint32_t control[2]; 186 uint32_t status; 187 uint32_t mask; 188 uint32_t clk; 189 190 int enable; 191 int rx_len; 192 int tx_len; 193 void (*codec_out)(void *, uint32_t); 194 uint32_t (*codec_in)(void *); 195 void *opaque; 196 197 int fifo_len; 198 uint32_t fifo[16]; 199 }; 200 201 # define PA_FMT "0x%08lx" 202 203 PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size, 204 const char *revision); 205 PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size); 206 207 #endif /* PXA_H */ 208