1 /* 2 * ARM SMMU Support 3 * 4 * Copyright (C) 2015-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef HW_ARM_SMMU_COMMON_H 20 #define HW_ARM_SMMU_COMMON_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci.h" 24 #include "qom/object.h" 25 26 #define SMMU_PCI_BUS_MAX 256 27 #define SMMU_PCI_DEVFN_MAX 256 28 #define SMMU_PCI_DEVFN(sid) (sid & 0xFF) 29 30 /* 31 * Page table walk error types 32 */ 33 typedef enum { 34 SMMU_PTW_ERR_NONE, 35 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */ 36 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */ 37 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */ 38 SMMU_PTW_ERR_ACCESS, /* Access fault */ 39 SMMU_PTW_ERR_PERMISSION, /* Permission fault */ 40 } SMMUPTWEventType; 41 42 typedef struct SMMUPTWEventInfo { 43 SMMUPTWEventType type; 44 dma_addr_t addr; /* fetched address that induced an abort, if any */ 45 } SMMUPTWEventInfo; 46 47 typedef struct SMMUTransTableInfo { 48 bool disabled; /* is the translation table disabled? */ 49 uint64_t ttb; /* TT base address */ 50 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ 51 uint8_t granule_sz; /* granule page shift */ 52 bool had; /* hierarchical attribute disable */ 53 } SMMUTransTableInfo; 54 55 typedef struct SMMUTLBEntry { 56 IOMMUTLBEntry entry; 57 uint8_t level; 58 uint8_t granule; 59 } SMMUTLBEntry; 60 61 /* 62 * Generic structure populated by derived SMMU devices 63 * after decoding the configuration information and used as 64 * input to the page table walk 65 */ 66 typedef struct SMMUTransCfg { 67 int stage; /* translation stage */ 68 bool aa64; /* arch64 or aarch32 translation table */ 69 bool disabled; /* smmu is disabled */ 70 bool bypassed; /* translation is bypassed */ 71 bool aborted; /* translation is aborted */ 72 bool record_faults; /* record fault events */ 73 uint64_t ttb; /* TT base address */ 74 uint8_t oas; /* output address width */ 75 uint8_t tbi; /* Top Byte Ignore */ 76 uint16_t asid; 77 SMMUTransTableInfo tt[2]; 78 uint32_t iotlb_hits; /* counts IOTLB hits for this asid */ 79 uint32_t iotlb_misses; /* counts IOTLB misses for this asid */ 80 } SMMUTransCfg; 81 82 typedef struct SMMUDevice { 83 void *smmu; 84 PCIBus *bus; 85 int devfn; 86 IOMMUMemoryRegion iommu; 87 AddressSpace as; 88 uint32_t cfg_cache_hits; 89 uint32_t cfg_cache_misses; 90 QLIST_ENTRY(SMMUDevice) next; 91 } SMMUDevice; 92 93 typedef struct SMMUPciBus { 94 PCIBus *bus; 95 SMMUDevice *pbdev[]; /* Parent array is sparse, so dynamically alloc */ 96 } SMMUPciBus; 97 98 typedef struct SMMUIOTLBKey { 99 uint64_t iova; 100 uint16_t asid; 101 uint8_t tg; 102 uint8_t level; 103 } SMMUIOTLBKey; 104 105 struct SMMUState { 106 /* <private> */ 107 SysBusDevice dev; 108 const char *mrtypename; 109 MemoryRegion iomem; 110 111 GHashTable *smmu_pcibus_by_busptr; 112 GHashTable *configs; /* cache for configuration data */ 113 GHashTable *iotlb; 114 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; 115 PCIBus *pci_bus; 116 QLIST_HEAD(, SMMUDevice) devices_with_notifiers; 117 uint8_t bus_num; 118 PCIBus *primary_bus; 119 }; 120 121 struct SMMUBaseClass { 122 /* <private> */ 123 SysBusDeviceClass parent_class; 124 125 /*< public >*/ 126 127 DeviceRealize parent_realize; 128 129 }; 130 131 #define TYPE_ARM_SMMU "arm-smmu" 132 OBJECT_DECLARE_TYPE(SMMUState, SMMUBaseClass, ARM_SMMU) 133 134 /* Return the SMMUPciBus handle associated to a PCI bus number */ 135 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 136 137 /* Return the stream ID of an SMMU device */ 138 static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 139 { 140 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 141 } 142 143 /** 144 * smmu_ptw - Perform the page table walk for a given iova / access flags 145 * pair, according to @cfg translation config 146 */ 147 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, 148 SMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); 149 150 /** 151 * select_tt - compute which translation table shall be used according to 152 * the input iova and translation config and return the TT specific info 153 */ 154 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); 155 156 /* Return the iommu mr associated to @sid, or NULL if none */ 157 IOMMUMemoryRegion *smmu_iommu_mr(SMMUState *s, uint32_t sid); 158 159 #define SMMU_IOTLB_MAX_SIZE 256 160 161 SMMUTLBEntry *smmu_iotlb_lookup(SMMUState *bs, SMMUTransCfg *cfg, 162 SMMUTransTableInfo *tt, hwaddr iova); 163 void smmu_iotlb_insert(SMMUState *bs, SMMUTransCfg *cfg, SMMUTLBEntry *entry); 164 SMMUIOTLBKey smmu_get_iotlb_key(uint16_t asid, uint64_t iova, 165 uint8_t tg, uint8_t level); 166 void smmu_iotlb_inv_all(SMMUState *s); 167 void smmu_iotlb_inv_asid(SMMUState *s, uint16_t asid); 168 void smmu_iotlb_inv_iova(SMMUState *s, int asid, dma_addr_t iova, 169 uint8_t tg, uint64_t num_pages, uint8_t ttl); 170 171 /* Unmap the range of all the notifiers registered to any IOMMU mr */ 172 void smmu_inv_notifiers_all(SMMUState *s); 173 174 #endif /* HW_ARM_SMMU_COMMON_H */ 175