1 /* 2 * ARM SMMU Support 3 * 4 * Copyright (C) 2015-2016 Broadcom Corporation 5 * Copyright (c) 2017 Red Hat, Inc. 6 * Written by Prem Mallappa, Eric Auger 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #ifndef HW_ARM_SMMU_COMMON_H 20 #define HW_ARM_SMMU_COMMON_H 21 22 #include "hw/sysbus.h" 23 #include "hw/pci/pci.h" 24 25 #define SMMU_PCI_BUS_MAX 256 26 #define SMMU_PCI_DEVFN_MAX 256 27 28 #define SMMU_MAX_VA_BITS 48 29 30 /* 31 * Page table walk error types 32 */ 33 typedef enum { 34 SMMU_PTW_ERR_NONE, 35 SMMU_PTW_ERR_WALK_EABT, /* Translation walk external abort */ 36 SMMU_PTW_ERR_TRANSLATION, /* Translation fault */ 37 SMMU_PTW_ERR_ADDR_SIZE, /* Address Size fault */ 38 SMMU_PTW_ERR_ACCESS, /* Access fault */ 39 SMMU_PTW_ERR_PERMISSION, /* Permission fault */ 40 } SMMUPTWEventType; 41 42 typedef struct SMMUPTWEventInfo { 43 SMMUPTWEventType type; 44 dma_addr_t addr; /* fetched address that induced an abort, if any */ 45 } SMMUPTWEventInfo; 46 47 typedef struct SMMUTransTableInfo { 48 bool disabled; /* is the translation table disabled? */ 49 uint64_t ttb; /* TT base address */ 50 uint8_t tsz; /* input range, ie. 2^(64 -tsz)*/ 51 uint8_t granule_sz; /* granule page shift */ 52 } SMMUTransTableInfo; 53 54 /* 55 * Generic structure populated by derived SMMU devices 56 * after decoding the configuration information and used as 57 * input to the page table walk 58 */ 59 typedef struct SMMUTransCfg { 60 int stage; /* translation stage */ 61 bool aa64; /* arch64 or aarch32 translation table */ 62 bool disabled; /* smmu is disabled */ 63 bool bypassed; /* translation is bypassed */ 64 bool aborted; /* translation is aborted */ 65 uint64_t ttb; /* TT base address */ 66 uint8_t oas; /* output address width */ 67 uint8_t tbi; /* Top Byte Ignore */ 68 uint16_t asid; 69 SMMUTransTableInfo tt[2]; 70 } SMMUTransCfg; 71 72 typedef struct SMMUDevice { 73 void *smmu; 74 PCIBus *bus; 75 int devfn; 76 IOMMUMemoryRegion iommu; 77 AddressSpace as; 78 } SMMUDevice; 79 80 typedef struct SMMUNotifierNode { 81 SMMUDevice *sdev; 82 QLIST_ENTRY(SMMUNotifierNode) next; 83 } SMMUNotifierNode; 84 85 typedef struct SMMUPciBus { 86 PCIBus *bus; 87 SMMUDevice *pbdev[0]; /* Parent array is sparse, so dynamically alloc */ 88 } SMMUPciBus; 89 90 typedef struct SMMUState { 91 /* <private> */ 92 SysBusDevice dev; 93 const char *mrtypename; 94 MemoryRegion iomem; 95 96 GHashTable *smmu_pcibus_by_busptr; 97 GHashTable *configs; /* cache for configuration data */ 98 GHashTable *iotlb; 99 SMMUPciBus *smmu_pcibus_by_bus_num[SMMU_PCI_BUS_MAX]; 100 PCIBus *pci_bus; 101 QLIST_HEAD(, SMMUNotifierNode) notifiers_list; 102 uint8_t bus_num; 103 PCIBus *primary_bus; 104 } SMMUState; 105 106 typedef struct { 107 /* <private> */ 108 SysBusDeviceClass parent_class; 109 110 /*< public >*/ 111 112 DeviceRealize parent_realize; 113 114 } SMMUBaseClass; 115 116 #define TYPE_ARM_SMMU "arm-smmu" 117 #define ARM_SMMU(obj) OBJECT_CHECK(SMMUState, (obj), TYPE_ARM_SMMU) 118 #define ARM_SMMU_CLASS(klass) \ 119 OBJECT_CLASS_CHECK(SMMUBaseClass, (klass), TYPE_ARM_SMMU) 120 #define ARM_SMMU_GET_CLASS(obj) \ 121 OBJECT_GET_CLASS(SMMUBaseClass, (obj), TYPE_ARM_SMMU) 122 123 /* Return the SMMUPciBus handle associated to a PCI bus number */ 124 SMMUPciBus *smmu_find_smmu_pcibus(SMMUState *s, uint8_t bus_num); 125 126 /* Return the stream ID of an SMMU device */ 127 static inline uint16_t smmu_get_sid(SMMUDevice *sdev) 128 { 129 return PCI_BUILD_BDF(pci_bus_num(sdev->bus), sdev->devfn); 130 } 131 132 /** 133 * smmu_ptw - Perform the page table walk for a given iova / access flags 134 * pair, according to @cfg translation config 135 */ 136 int smmu_ptw(SMMUTransCfg *cfg, dma_addr_t iova, IOMMUAccessFlags perm, 137 IOMMUTLBEntry *tlbe, SMMUPTWEventInfo *info); 138 139 /** 140 * select_tt - compute which translation table shall be used according to 141 * the input iova and translation config and return the TT specific info 142 */ 143 SMMUTransTableInfo *select_tt(SMMUTransCfg *cfg, dma_addr_t iova); 144 145 #endif /* HW_ARM_SMMU_COMMON */ 146