1 /* 2 * STM32L4x5 SoC family 3 * 4 * Copyright (c) 2023 Arnaud Minier <arnaud.minier@telecom-paris.fr> 5 * Copyright (c) 2023 Inès Varhol <ines.varhol@telecom-paris.fr> 6 * 7 * SPDX-License-Identifier: GPL-2.0-or-later 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 * 12 * This work is heavily inspired by the stm32f405_soc by Alistair Francis. 13 * Original code is licensed under the MIT License: 14 * 15 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me> 16 */ 17 18 /* 19 * The reference used is the STMicroElectronics RM0351 Reference manual 20 * for STM32L4x5 and STM32L4x6 advanced Arm ® -based 32-bit MCUs. 21 * https://www.st.com/en/microcontrollers-microprocessors/stm32l4x5/documentation.html 22 */ 23 24 #ifndef HW_ARM_STM32L4x5_SOC_H 25 #define HW_ARM_STM32L4x5_SOC_H 26 27 #include "exec/memory.h" 28 #include "hw/arm/armv7m.h" 29 #include "qom/object.h" 30 31 #define TYPE_STM32L4X5_SOC "stm32l4x5-soc" 32 #define TYPE_STM32L4X5XC_SOC "stm32l4x5xc-soc" 33 #define TYPE_STM32L4X5XE_SOC "stm32l4x5xe-soc" 34 #define TYPE_STM32L4X5XG_SOC "stm32l4x5xg-soc" 35 OBJECT_DECLARE_TYPE(Stm32l4x5SocState, Stm32l4x5SocClass, STM32L4X5_SOC) 36 37 struct Stm32l4x5SocState { 38 SysBusDevice parent_obj; 39 40 ARMv7MState armv7m; 41 42 MemoryRegion sram1; 43 MemoryRegion sram2; 44 MemoryRegion flash; 45 MemoryRegion flash_alias; 46 47 Clock *sysclk; 48 Clock *refclk; 49 }; 50 51 struct Stm32l4x5SocClass { 52 SysBusDeviceClass parent_class; 53 54 size_t flash_size; 55 }; 56 57 #endif 58