1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 1888052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 19*4bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 20b89de436SEdgar E. Iglesias 21b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 22b89de436SEdgar E. Iglesias #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) 23b89de436SEdgar E. Iglesias 24b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 25b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 26b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 278a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 28f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 29b89de436SEdgar E. Iglesias 30b89de436SEdgar E. Iglesias typedef struct Versal { 31b89de436SEdgar E. Iglesias /*< private >*/ 32b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 33b89de436SEdgar E. Iglesias 34b89de436SEdgar E. Iglesias /*< public >*/ 35b89de436SEdgar E. Iglesias struct { 36b89de436SEdgar E. Iglesias struct { 37b89de436SEdgar E. Iglesias MemoryRegion mr; 38b89de436SEdgar E. Iglesias ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; 39b89de436SEdgar E. Iglesias GICv3State gic; 40b89de436SEdgar E. Iglesias } apu; 41b89de436SEdgar E. Iglesias } fpd; 42b89de436SEdgar E. Iglesias 43b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 44b89de436SEdgar E. Iglesias 45b89de436SEdgar E. Iglesias struct { 46b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 47b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 48b89de436SEdgar E. Iglesias } noc; 49b89de436SEdgar E. Iglesias 50b89de436SEdgar E. Iglesias struct { 51b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 52b89de436SEdgar E. Iglesias 53b89de436SEdgar E. Iglesias struct { 5488052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 55*4bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 568a218651SEdgar E. Iglesias SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; 57b89de436SEdgar E. Iglesias } iou; 58b89de436SEdgar E. Iglesias } lpd; 59b89de436SEdgar E. Iglesias 60b89de436SEdgar E. Iglesias struct { 61b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 62b89de436SEdgar E. Iglesias uint32_t psci_conduit; 63b89de436SEdgar E. Iglesias } cfg; 64b89de436SEdgar E. Iglesias } Versal; 65b89de436SEdgar E. Iglesias 66b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 67b89de436SEdgar E. Iglesias * auto-generated files. */ 68b89de436SEdgar E. Iglesias 69b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 70b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 71b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 72b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 73b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 74b89de436SEdgar E. Iglesias 75b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 76b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 77b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 78b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 79b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 80b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 818a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 82b89de436SEdgar E. Iglesias 83fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 84fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 85fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 86b89de436SEdgar E. Iglesias 87b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 88b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 89b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 90b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 91b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 92b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 93b89de436SEdgar E. Iglesias 94b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 95b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 96b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 97b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 98b89de436SEdgar E. Iglesias 99b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 100b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 101b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 102b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 103b89de436SEdgar E. Iglesias 1048a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1058a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1068a218651SEdgar E. Iglesias 107b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 108b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 109b89de436SEdgar E. Iglesias 110b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 111b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 112b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 113b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 114b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 115b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 116b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 117b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 118b89de436SEdgar E. Iglesias 119b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 120b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 121b89de436SEdgar E. Iglesias 122b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 123b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 124b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 125b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 126b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 127b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 128b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 129b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 130f0138990SEdgar E. Iglesias 131f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 132f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 133b89de436SEdgar E. Iglesias #endif 134