1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17a55b441bSEdgar E. Iglesias #include "hw/or-irq.h" 18724c6e12SEdgar E. Iglesias #include "hw/sd/sdhci.h" 19b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 2088052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 21f4e3fa37SEdgar E. Iglesias #include "hw/dma/xlnx-zdma.h" 224bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 23eb1221c5SEdgar E. Iglesias #include "hw/rtc/xlnx-zynqmp-rtc.h" 24db1015e9SEduardo Habkost #include "qom/object.h" 25144677d4SVikram Garhwal #include "hw/usb/xlnx-usb-subsystem.h" 26a55b441bSEdgar E. Iglesias #include "hw/misc/xlnx-versal-xramc.h" 27393185bcSTong Ho #include "hw/nvram/xlnx-bbram.h" 28*5f4910ffSTong Ho #include "hw/nvram/xlnx-versal-efuse.h" 29b89de436SEdgar E. Iglesias 30b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 318063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 32b89de436SEdgar E. Iglesias 33b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 34b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 35b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 368a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 37724c6e12SEdgar E. Iglesias #define XLNX_VERSAL_NR_SDS 2 38a55b441bSEdgar E. Iglesias #define XLNX_VERSAL_NR_XRAM 4 39f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 40b89de436SEdgar E. Iglesias 41db1015e9SEduardo Habkost struct Versal { 42b89de436SEdgar E. Iglesias /*< private >*/ 43b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 44b89de436SEdgar E. Iglesias 45b89de436SEdgar E. Iglesias /*< public >*/ 46b89de436SEdgar E. Iglesias struct { 47b89de436SEdgar E. Iglesias struct { 48b89de436SEdgar E. Iglesias MemoryRegion mr; 49ced18d5eSEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 50b89de436SEdgar E. Iglesias GICv3State gic; 51b89de436SEdgar E. Iglesias } apu; 52b89de436SEdgar E. Iglesias } fpd; 53b89de436SEdgar E. Iglesias 54b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 55b89de436SEdgar E. Iglesias 56b89de436SEdgar E. Iglesias struct { 57b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 58b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 59b89de436SEdgar E. Iglesias } noc; 60b89de436SEdgar E. Iglesias 61b89de436SEdgar E. Iglesias struct { 62b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 63b89de436SEdgar E. Iglesias 64b89de436SEdgar E. Iglesias struct { 6588052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 664bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 67f4e3fa37SEdgar E. Iglesias XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 68144677d4SVikram Garhwal VersalUsb2 usb; 69b89de436SEdgar E. Iglesias } iou; 70a55b441bSEdgar E. Iglesias 71a55b441bSEdgar E. Iglesias struct { 72a55b441bSEdgar E. Iglesias qemu_or_irq irq_orgate; 73a55b441bSEdgar E. Iglesias XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 74a55b441bSEdgar E. Iglesias } xram; 75b89de436SEdgar E. Iglesias } lpd; 76b89de436SEdgar E. Iglesias 77724c6e12SEdgar E. Iglesias /* The Platform Management Controller subsystem. */ 78724c6e12SEdgar E. Iglesias struct { 79724c6e12SEdgar E. Iglesias struct { 80724c6e12SEdgar E. Iglesias SDHCIState sd[XLNX_VERSAL_NR_SDS]; 81724c6e12SEdgar E. Iglesias } iou; 82eb1221c5SEdgar E. Iglesias 83eb1221c5SEdgar E. Iglesias XlnxZynqMPRTC rtc; 84393185bcSTong Ho XlnxBBRam bbram; 85*5f4910ffSTong Ho XlnxEFuse efuse; 86*5f4910ffSTong Ho XlnxVersalEFuseCtrl efuse_ctrl; 87*5f4910ffSTong Ho XlnxVersalEFuseCache efuse_cache; 88724c6e12SEdgar E. Iglesias } pmc; 89724c6e12SEdgar E. Iglesias 90b89de436SEdgar E. Iglesias struct { 91b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 92b89de436SEdgar E. Iglesias uint32_t psci_conduit; 93b89de436SEdgar E. Iglesias } cfg; 94db1015e9SEduardo Habkost }; 95b89de436SEdgar E. Iglesias 96b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 97b89de436SEdgar E. Iglesias * auto-generated files. */ 98b89de436SEdgar E. Iglesias 99b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 100b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 101b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 102b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 103b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 104b89de436SEdgar E. Iglesias 105b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 106b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 107144677d4SVikram Garhwal #define VERSAL_USB0_IRQ_0 22 108b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 109b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 110b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 111b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 1128a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 113a55b441bSEdgar E. Iglesias #define VERSAL_XRAM_IRQ_0 79 114393185bcSTong Ho #define VERSAL_BBRAM_APB_IRQ_0 121 115eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_APB_ERR_IRQ 121 116724c6e12SEdgar E. Iglesias #define VERSAL_SD0_IRQ_0 126 117*5f4910ffSTong Ho #define VERSAL_EFUSE_IRQ 139 118eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_ALARM_IRQ 142 119eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_SECONDS_IRQ 143 120b89de436SEdgar E. Iglesias 121fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 122fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 123fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 124b89de436SEdgar E. Iglesias 125b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 126b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 127b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 128b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 129b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 130b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 131b89de436SEdgar E. Iglesias 132b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 133b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 134b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 135b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 136b89de436SEdgar E. Iglesias 137b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 138b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 139b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 140b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 141b89de436SEdgar E. Iglesias 1428a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1438a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1448a218651SEdgar E. Iglesias 145b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 146b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 147b89de436SEdgar E. Iglesias 148a55b441bSEdgar E. Iglesias #define MM_XRAM 0xfe800000 149a55b441bSEdgar E. Iglesias #define MM_XRAMC 0xff8e0000 150a55b441bSEdgar E. Iglesias #define MM_XRAMC_SIZE 0x10000 151a55b441bSEdgar E. Iglesias 152144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS 0xFF9D0000 153144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS_SIZE 0x10000 154144677d4SVikram Garhwal 155144677d4SVikram Garhwal #define MM_USB_0 0xFE200000 156144677d4SVikram Garhwal #define MM_USB_0_SIZE 0x10000 157144677d4SVikram Garhwal 158b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 159b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 160b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 161b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 162b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 163b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 164b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 165b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 166b89de436SEdgar E. Iglesias 167b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 168b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 169b89de436SEdgar E. Iglesias 170b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 171b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 172b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 173b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 174b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 175b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 176b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 177b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 1789a0fcb7fSTong Ho #define MM_FPD_FPD_APU 0xfd5c0000 1799a0fcb7fSTong Ho #define MM_FPD_FPD_APU_SIZE 0x100 180f0138990SEdgar E. Iglesias 181724c6e12SEdgar E. Iglesias #define MM_PMC_SD0 0xf1040000U 182724c6e12SEdgar E. Iglesias #define MM_PMC_SD0_SIZE 0x10000 183393185bcSTong Ho #define MM_PMC_BBRAM_CTRL 0xf11f0000 184393185bcSTong Ho #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 185*5f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL 0xf1240000 186*5f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 187*5f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE 0xf1250000 188*5f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 189*5f4910ffSTong Ho 190f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 191f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 192eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC 0xf12a0000 193eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC_SIZE 0x10000 194b89de436SEdgar E. Iglesias #endif 195