1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 178779d00cSEdgar E. Iglesias #include "hw/cpu/cluster.h" 18a55b441bSEdgar E. Iglesias #include "hw/or-irq.h" 19724c6e12SEdgar E. Iglesias #include "hw/sd/sdhci.h" 20b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 2188052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 22f4e3fa37SEdgar E. Iglesias #include "hw/dma/xlnx-zdma.h" 234bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 24eb1221c5SEdgar E. Iglesias #include "hw/rtc/xlnx-zynqmp-rtc.h" 25db1015e9SEduardo Habkost #include "qom/object.h" 26144677d4SVikram Garhwal #include "hw/usb/xlnx-usb-subsystem.h" 27a55b441bSEdgar E. Iglesias #include "hw/misc/xlnx-versal-xramc.h" 28393185bcSTong Ho #include "hw/nvram/xlnx-bbram.h" 295f4910ffSTong Ho #include "hw/nvram/xlnx-versal-efuse.h" 30868d9680SFrancisco Iglesias #include "hw/ssi/xlnx-versal-ospi.h" 31868d9680SFrancisco Iglesias #include "hw/dma/xlnx_csu_dma.h" 32f7c9aecbSFrancisco Iglesias #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 33b89de436SEdgar E. Iglesias 34b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 358063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 36b89de436SEdgar E. Iglesias 37b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 38*67a645a3SEdgar E. Iglesias #define XLNX_VERSAL_NR_RCPUS 2 39b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 40b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 418a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 42724c6e12SEdgar E. Iglesias #define XLNX_VERSAL_NR_SDS 2 43a55b441bSEdgar E. Iglesias #define XLNX_VERSAL_NR_XRAM 4 44f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 45b89de436SEdgar E. Iglesias 46db1015e9SEduardo Habkost struct Versal { 47b89de436SEdgar E. Iglesias /*< private >*/ 48b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 49b89de436SEdgar E. Iglesias 50b89de436SEdgar E. Iglesias /*< public >*/ 51b89de436SEdgar E. Iglesias struct { 52b89de436SEdgar E. Iglesias struct { 53b89de436SEdgar E. Iglesias MemoryRegion mr; 548779d00cSEdgar E. Iglesias CPUClusterState cluster; 55ced18d5eSEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 56b89de436SEdgar E. Iglesias GICv3State gic; 57b89de436SEdgar E. Iglesias } apu; 58b89de436SEdgar E. Iglesias } fpd; 59b89de436SEdgar E. Iglesias 60b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 61b89de436SEdgar E. Iglesias 62b89de436SEdgar E. Iglesias struct { 63b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 64b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 65b89de436SEdgar E. Iglesias } noc; 66b89de436SEdgar E. Iglesias 67b89de436SEdgar E. Iglesias struct { 68b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 69b89de436SEdgar E. Iglesias 70b89de436SEdgar E. Iglesias struct { 7188052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 724bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 73f4e3fa37SEdgar E. Iglesias XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 74144677d4SVikram Garhwal VersalUsb2 usb; 75b89de436SEdgar E. Iglesias } iou; 76a55b441bSEdgar E. Iglesias 77*67a645a3SEdgar E. Iglesias /* Real-time Processing Unit. */ 78*67a645a3SEdgar E. Iglesias struct { 79*67a645a3SEdgar E. Iglesias MemoryRegion mr; 80*67a645a3SEdgar E. Iglesias MemoryRegion mr_ps_alias; 81*67a645a3SEdgar E. Iglesias 82*67a645a3SEdgar E. Iglesias CPUClusterState cluster; 83*67a645a3SEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; 84*67a645a3SEdgar E. Iglesias } rpu; 85*67a645a3SEdgar E. Iglesias 86a55b441bSEdgar E. Iglesias struct { 87a55b441bSEdgar E. Iglesias qemu_or_irq irq_orgate; 88a55b441bSEdgar E. Iglesias XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 89a55b441bSEdgar E. Iglesias } xram; 90b89de436SEdgar E. Iglesias } lpd; 91b89de436SEdgar E. Iglesias 92724c6e12SEdgar E. Iglesias /* The Platform Management Controller subsystem. */ 93724c6e12SEdgar E. Iglesias struct { 94724c6e12SEdgar E. Iglesias struct { 95724c6e12SEdgar E. Iglesias SDHCIState sd[XLNX_VERSAL_NR_SDS]; 96f7c9aecbSFrancisco Iglesias XlnxVersalPmcIouSlcr slcr; 97868d9680SFrancisco Iglesias 98868d9680SFrancisco Iglesias struct { 99868d9680SFrancisco Iglesias XlnxVersalOspi ospi; 100868d9680SFrancisco Iglesias XlnxCSUDMA dma_src; 101868d9680SFrancisco Iglesias XlnxCSUDMA dma_dst; 102868d9680SFrancisco Iglesias MemoryRegion linear_mr; 103868d9680SFrancisco Iglesias qemu_or_irq irq_orgate; 104868d9680SFrancisco Iglesias } ospi; 105724c6e12SEdgar E. Iglesias } iou; 106eb1221c5SEdgar E. Iglesias 107eb1221c5SEdgar E. Iglesias XlnxZynqMPRTC rtc; 108393185bcSTong Ho XlnxBBRam bbram; 1095f4910ffSTong Ho XlnxEFuse efuse; 1105f4910ffSTong Ho XlnxVersalEFuseCtrl efuse_ctrl; 1115f4910ffSTong Ho XlnxVersalEFuseCache efuse_cache; 1129a6d4918SFrancisco Iglesias 1139a6d4918SFrancisco Iglesias qemu_or_irq apb_irq_orgate; 114724c6e12SEdgar E. Iglesias } pmc; 115724c6e12SEdgar E. Iglesias 116b89de436SEdgar E. Iglesias struct { 117b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 118b89de436SEdgar E. Iglesias } cfg; 119db1015e9SEduardo Habkost }; 120b89de436SEdgar E. Iglesias 121b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 122b89de436SEdgar E. Iglesias * auto-generated files. */ 123b89de436SEdgar E. Iglesias 124b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 125b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 126b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 127b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 128b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 129b89de436SEdgar E. Iglesias 130b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 131b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 132144677d4SVikram Garhwal #define VERSAL_USB0_IRQ_0 22 133b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 134b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 135b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 136b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 1378a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 138a55b441bSEdgar E. Iglesias #define VERSAL_XRAM_IRQ_0 79 1399a6d4918SFrancisco Iglesias #define VERSAL_PMC_APB_IRQ 121 140868d9680SFrancisco Iglesias #define VERSAL_OSPI_IRQ 124 141724c6e12SEdgar E. Iglesias #define VERSAL_SD0_IRQ_0 126 1425f4910ffSTong Ho #define VERSAL_EFUSE_IRQ 139 143eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_ALARM_IRQ 142 144eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_SECONDS_IRQ 143 145b89de436SEdgar E. Iglesias 146fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 147fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 148fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 149b89de436SEdgar E. Iglesias 150b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 151b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 152b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 153b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 154b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 155b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 156b89de436SEdgar E. Iglesias 157b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 158b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 159b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 160b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 161b89de436SEdgar E. Iglesias 162b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 163b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 164b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 165b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 166b89de436SEdgar E. Iglesias 1678a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1688a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1698a218651SEdgar E. Iglesias 170b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 171b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 172b89de436SEdgar E. Iglesias 173a55b441bSEdgar E. Iglesias #define MM_XRAM 0xfe800000 174a55b441bSEdgar E. Iglesias #define MM_XRAMC 0xff8e0000 175a55b441bSEdgar E. Iglesias #define MM_XRAMC_SIZE 0x10000 176a55b441bSEdgar E. Iglesias 177144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS 0xFF9D0000 178144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS_SIZE 0x10000 179144677d4SVikram Garhwal 180144677d4SVikram Garhwal #define MM_USB_0 0xFE200000 181144677d4SVikram Garhwal #define MM_USB_0_SIZE 0x10000 182144677d4SVikram Garhwal 183b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 184b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 185b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 186b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 187b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 188b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 189b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 190b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 191b89de436SEdgar E. Iglesias 192b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 193b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 194b89de436SEdgar E. Iglesias 195b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 196b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 197b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 198b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 199b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 200b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 201b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 202b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 2039a0fcb7fSTong Ho #define MM_FPD_FPD_APU 0xfd5c0000 2049a0fcb7fSTong Ho #define MM_FPD_FPD_APU_SIZE 0x100 205f0138990SEdgar E. Iglesias 206f7c9aecbSFrancisco Iglesias #define MM_PMC_PMC_IOU_SLCR 0xf1060000 207f7c9aecbSFrancisco Iglesias #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 208f7c9aecbSFrancisco Iglesias 209868d9680SFrancisco Iglesias #define MM_PMC_OSPI 0xf1010000 210868d9680SFrancisco Iglesias #define MM_PMC_OSPI_SIZE 0x10000 211868d9680SFrancisco Iglesias 212868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DAC 0xc0000000 213868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DAC_SIZE 0x20000000 214868d9680SFrancisco Iglesias 215868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DMA_DST 0xf1011800 216868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DMA_SRC 0xf1011000 217868d9680SFrancisco Iglesias 218724c6e12SEdgar E. Iglesias #define MM_PMC_SD0 0xf1040000U 219724c6e12SEdgar E. Iglesias #define MM_PMC_SD0_SIZE 0x10000 220393185bcSTong Ho #define MM_PMC_BBRAM_CTRL 0xf11f0000 221393185bcSTong Ho #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 2225f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL 0xf1240000 2235f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 2245f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE 0xf1250000 2255f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 2265f4910ffSTong Ho 227f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 228f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 229eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC 0xf12a0000 230eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC_SIZE 0x10000 231b89de436SEdgar E. Iglesias #endif 232