1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17*8779d00cSEdgar E. Iglesias #include "hw/cpu/cluster.h" 18a55b441bSEdgar E. Iglesias #include "hw/or-irq.h" 19724c6e12SEdgar E. Iglesias #include "hw/sd/sdhci.h" 20b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 2188052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 22f4e3fa37SEdgar E. Iglesias #include "hw/dma/xlnx-zdma.h" 234bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 24eb1221c5SEdgar E. Iglesias #include "hw/rtc/xlnx-zynqmp-rtc.h" 25db1015e9SEduardo Habkost #include "qom/object.h" 26144677d4SVikram Garhwal #include "hw/usb/xlnx-usb-subsystem.h" 27a55b441bSEdgar E. Iglesias #include "hw/misc/xlnx-versal-xramc.h" 28393185bcSTong Ho #include "hw/nvram/xlnx-bbram.h" 295f4910ffSTong Ho #include "hw/nvram/xlnx-versal-efuse.h" 30868d9680SFrancisco Iglesias #include "hw/ssi/xlnx-versal-ospi.h" 31868d9680SFrancisco Iglesias #include "hw/dma/xlnx_csu_dma.h" 32f7c9aecbSFrancisco Iglesias #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 33b89de436SEdgar E. Iglesias 34b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 358063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 36b89de436SEdgar E. Iglesias 37b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 38b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 39b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 408a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 41724c6e12SEdgar E. Iglesias #define XLNX_VERSAL_NR_SDS 2 42a55b441bSEdgar E. Iglesias #define XLNX_VERSAL_NR_XRAM 4 43f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 44b89de436SEdgar E. Iglesias 45db1015e9SEduardo Habkost struct Versal { 46b89de436SEdgar E. Iglesias /*< private >*/ 47b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 48b89de436SEdgar E. Iglesias 49b89de436SEdgar E. Iglesias /*< public >*/ 50b89de436SEdgar E. Iglesias struct { 51b89de436SEdgar E. Iglesias struct { 52b89de436SEdgar E. Iglesias MemoryRegion mr; 53*8779d00cSEdgar E. Iglesias CPUClusterState cluster; 54ced18d5eSEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 55b89de436SEdgar E. Iglesias GICv3State gic; 56b89de436SEdgar E. Iglesias } apu; 57b89de436SEdgar E. Iglesias } fpd; 58b89de436SEdgar E. Iglesias 59b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 60b89de436SEdgar E. Iglesias 61b89de436SEdgar E. Iglesias struct { 62b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 63b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 64b89de436SEdgar E. Iglesias } noc; 65b89de436SEdgar E. Iglesias 66b89de436SEdgar E. Iglesias struct { 67b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 68b89de436SEdgar E. Iglesias 69b89de436SEdgar E. Iglesias struct { 7088052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 714bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 72f4e3fa37SEdgar E. Iglesias XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 73144677d4SVikram Garhwal VersalUsb2 usb; 74b89de436SEdgar E. Iglesias } iou; 75a55b441bSEdgar E. Iglesias 76a55b441bSEdgar E. Iglesias struct { 77a55b441bSEdgar E. Iglesias qemu_or_irq irq_orgate; 78a55b441bSEdgar E. Iglesias XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 79a55b441bSEdgar E. Iglesias } xram; 80b89de436SEdgar E. Iglesias } lpd; 81b89de436SEdgar E. Iglesias 82724c6e12SEdgar E. Iglesias /* The Platform Management Controller subsystem. */ 83724c6e12SEdgar E. Iglesias struct { 84724c6e12SEdgar E. Iglesias struct { 85724c6e12SEdgar E. Iglesias SDHCIState sd[XLNX_VERSAL_NR_SDS]; 86f7c9aecbSFrancisco Iglesias XlnxVersalPmcIouSlcr slcr; 87868d9680SFrancisco Iglesias 88868d9680SFrancisco Iglesias struct { 89868d9680SFrancisco Iglesias XlnxVersalOspi ospi; 90868d9680SFrancisco Iglesias XlnxCSUDMA dma_src; 91868d9680SFrancisco Iglesias XlnxCSUDMA dma_dst; 92868d9680SFrancisco Iglesias MemoryRegion linear_mr; 93868d9680SFrancisco Iglesias qemu_or_irq irq_orgate; 94868d9680SFrancisco Iglesias } ospi; 95724c6e12SEdgar E. Iglesias } iou; 96eb1221c5SEdgar E. Iglesias 97eb1221c5SEdgar E. Iglesias XlnxZynqMPRTC rtc; 98393185bcSTong Ho XlnxBBRam bbram; 995f4910ffSTong Ho XlnxEFuse efuse; 1005f4910ffSTong Ho XlnxVersalEFuseCtrl efuse_ctrl; 1015f4910ffSTong Ho XlnxVersalEFuseCache efuse_cache; 1029a6d4918SFrancisco Iglesias 1039a6d4918SFrancisco Iglesias qemu_or_irq apb_irq_orgate; 104724c6e12SEdgar E. Iglesias } pmc; 105724c6e12SEdgar E. Iglesias 106b89de436SEdgar E. Iglesias struct { 107b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 108b89de436SEdgar E. Iglesias } cfg; 109db1015e9SEduardo Habkost }; 110b89de436SEdgar E. Iglesias 111b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 112b89de436SEdgar E. Iglesias * auto-generated files. */ 113b89de436SEdgar E. Iglesias 114b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 115b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 116b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 117b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 118b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 119b89de436SEdgar E. Iglesias 120b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 121b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 122144677d4SVikram Garhwal #define VERSAL_USB0_IRQ_0 22 123b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 124b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 125b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 126b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 1278a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 128a55b441bSEdgar E. Iglesias #define VERSAL_XRAM_IRQ_0 79 1299a6d4918SFrancisco Iglesias #define VERSAL_PMC_APB_IRQ 121 130868d9680SFrancisco Iglesias #define VERSAL_OSPI_IRQ 124 131724c6e12SEdgar E. Iglesias #define VERSAL_SD0_IRQ_0 126 1325f4910ffSTong Ho #define VERSAL_EFUSE_IRQ 139 133eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_ALARM_IRQ 142 134eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_SECONDS_IRQ 143 135b89de436SEdgar E. Iglesias 136fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 137fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 138fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 139b89de436SEdgar E. Iglesias 140b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 141b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 142b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 143b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 144b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 145b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 146b89de436SEdgar E. Iglesias 147b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 148b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 149b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 150b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 151b89de436SEdgar E. Iglesias 152b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 153b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 154b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 155b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 156b89de436SEdgar E. Iglesias 1578a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1588a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1598a218651SEdgar E. Iglesias 160b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 161b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 162b89de436SEdgar E. Iglesias 163a55b441bSEdgar E. Iglesias #define MM_XRAM 0xfe800000 164a55b441bSEdgar E. Iglesias #define MM_XRAMC 0xff8e0000 165a55b441bSEdgar E. Iglesias #define MM_XRAMC_SIZE 0x10000 166a55b441bSEdgar E. Iglesias 167144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS 0xFF9D0000 168144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS_SIZE 0x10000 169144677d4SVikram Garhwal 170144677d4SVikram Garhwal #define MM_USB_0 0xFE200000 171144677d4SVikram Garhwal #define MM_USB_0_SIZE 0x10000 172144677d4SVikram Garhwal 173b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 174b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 175b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 176b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 177b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 178b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 179b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 180b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 181b89de436SEdgar E. Iglesias 182b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 183b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 184b89de436SEdgar E. Iglesias 185b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 186b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 187b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 188b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 189b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 190b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 191b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 192b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 1939a0fcb7fSTong Ho #define MM_FPD_FPD_APU 0xfd5c0000 1949a0fcb7fSTong Ho #define MM_FPD_FPD_APU_SIZE 0x100 195f0138990SEdgar E. Iglesias 196f7c9aecbSFrancisco Iglesias #define MM_PMC_PMC_IOU_SLCR 0xf1060000 197f7c9aecbSFrancisco Iglesias #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 198f7c9aecbSFrancisco Iglesias 199868d9680SFrancisco Iglesias #define MM_PMC_OSPI 0xf1010000 200868d9680SFrancisco Iglesias #define MM_PMC_OSPI_SIZE 0x10000 201868d9680SFrancisco Iglesias 202868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DAC 0xc0000000 203868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DAC_SIZE 0x20000000 204868d9680SFrancisco Iglesias 205868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DMA_DST 0xf1011800 206868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DMA_SRC 0xf1011000 207868d9680SFrancisco Iglesias 208724c6e12SEdgar E. Iglesias #define MM_PMC_SD0 0xf1040000U 209724c6e12SEdgar E. Iglesias #define MM_PMC_SD0_SIZE 0x10000 210393185bcSTong Ho #define MM_PMC_BBRAM_CTRL 0xf11f0000 211393185bcSTong Ho #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 2125f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL 0xf1240000 2135f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 2145f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE 0xf1250000 2155f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 2165f4910ffSTong Ho 217f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 218f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 219eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC 0xf12a0000 220eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC_SIZE 0x10000 221b89de436SEdgar E. Iglesias #endif 222