1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 18*88052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 19b89de436SEdgar E. Iglesias 20b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 21b89de436SEdgar E. Iglesias #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) 22b89de436SEdgar E. Iglesias 23b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 24b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 25b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 268a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 27f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 28b89de436SEdgar E. Iglesias 29b89de436SEdgar E. Iglesias typedef struct Versal { 30b89de436SEdgar E. Iglesias /*< private >*/ 31b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 32b89de436SEdgar E. Iglesias 33b89de436SEdgar E. Iglesias /*< public >*/ 34b89de436SEdgar E. Iglesias struct { 35b89de436SEdgar E. Iglesias struct { 36b89de436SEdgar E. Iglesias MemoryRegion mr; 37b89de436SEdgar E. Iglesias ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; 38b89de436SEdgar E. Iglesias GICv3State gic; 39b89de436SEdgar E. Iglesias } apu; 40b89de436SEdgar E. Iglesias } fpd; 41b89de436SEdgar E. Iglesias 42b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 43b89de436SEdgar E. Iglesias 44b89de436SEdgar E. Iglesias struct { 45b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 46b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 47b89de436SEdgar E. Iglesias } noc; 48b89de436SEdgar E. Iglesias 49b89de436SEdgar E. Iglesias struct { 50b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 51b89de436SEdgar E. Iglesias 52b89de436SEdgar E. Iglesias struct { 53*88052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 54b89de436SEdgar E. Iglesias SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; 558a218651SEdgar E. Iglesias SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; 56b89de436SEdgar E. Iglesias } iou; 57b89de436SEdgar E. Iglesias } lpd; 58b89de436SEdgar E. Iglesias 59b89de436SEdgar E. Iglesias struct { 60b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 61b89de436SEdgar E. Iglesias uint32_t psci_conduit; 62b89de436SEdgar E. Iglesias } cfg; 63b89de436SEdgar E. Iglesias } Versal; 64b89de436SEdgar E. Iglesias 65b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 66b89de436SEdgar E. Iglesias * auto-generated files. */ 67b89de436SEdgar E. Iglesias 68b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 69b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 70b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 71b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 72b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 73b89de436SEdgar E. Iglesias 74b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 75b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 76b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 77b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 78b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 79b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 808a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 81b89de436SEdgar E. Iglesias 82fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 83fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 84fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 85b89de436SEdgar E. Iglesias 86b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 87b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 88b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 89b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 90b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 91b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 92b89de436SEdgar E. Iglesias 93b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 94b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 95b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 96b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 97b89de436SEdgar E. Iglesias 98b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 99b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 100b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 101b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 102b89de436SEdgar E. Iglesias 1038a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1048a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1058a218651SEdgar E. Iglesias 106b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 107b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 108b89de436SEdgar E. Iglesias 109b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 110b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 111b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 112b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 113b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 114b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 115b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 116b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 117b89de436SEdgar E. Iglesias 118b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 119b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 120b89de436SEdgar E. Iglesias 121b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 122b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 123b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 124b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 125b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 126b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 127b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 128b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 129f0138990SEdgar E. Iglesias 130f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 131f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 132b89de436SEdgar E. Iglesias #endif 133