1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 18b89de436SEdgar E. Iglesias 19b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 20b89de436SEdgar E. Iglesias #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) 21b89de436SEdgar E. Iglesias 22b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 23b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 24b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 25*8a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 26f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 27b89de436SEdgar E. Iglesias 28b89de436SEdgar E. Iglesias typedef struct Versal { 29b89de436SEdgar E. Iglesias /*< private >*/ 30b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 31b89de436SEdgar E. Iglesias 32b89de436SEdgar E. Iglesias /*< public >*/ 33b89de436SEdgar E. Iglesias struct { 34b89de436SEdgar E. Iglesias struct { 35b89de436SEdgar E. Iglesias MemoryRegion mr; 36b89de436SEdgar E. Iglesias ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; 37b89de436SEdgar E. Iglesias GICv3State gic; 38b89de436SEdgar E. Iglesias } apu; 39b89de436SEdgar E. Iglesias } fpd; 40b89de436SEdgar E. Iglesias 41b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 42b89de436SEdgar E. Iglesias 43b89de436SEdgar E. Iglesias struct { 44b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 45b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 46b89de436SEdgar E. Iglesias } noc; 47b89de436SEdgar E. Iglesias 48b89de436SEdgar E. Iglesias struct { 49b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 50b89de436SEdgar E. Iglesias 51b89de436SEdgar E. Iglesias struct { 52b89de436SEdgar E. Iglesias SysBusDevice *uart[XLNX_VERSAL_NR_UARTS]; 53b89de436SEdgar E. Iglesias SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; 54*8a218651SEdgar E. Iglesias SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; 55b89de436SEdgar E. Iglesias } iou; 56b89de436SEdgar E. Iglesias } lpd; 57b89de436SEdgar E. Iglesias 58b89de436SEdgar E. Iglesias struct { 59b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 60b89de436SEdgar E. Iglesias uint32_t psci_conduit; 61b89de436SEdgar E. Iglesias } cfg; 62b89de436SEdgar E. Iglesias } Versal; 63b89de436SEdgar E. Iglesias 64b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 65b89de436SEdgar E. Iglesias * auto-generated files. */ 66b89de436SEdgar E. Iglesias 67b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 68b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 69b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 70b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 71b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 72b89de436SEdgar E. Iglesias 73b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 74b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 75b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 76b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 77b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 78b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 79*8a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 80b89de436SEdgar E. Iglesias 81fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 82fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 83fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 84b89de436SEdgar E. Iglesias 85b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 86b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 87b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 88b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 89b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 90b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 91b89de436SEdgar E. Iglesias 92b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 93b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 94b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 95b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 96b89de436SEdgar E. Iglesias 97b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 98b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 99b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 100b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 101b89de436SEdgar E. Iglesias 102*8a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 103*8a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 104*8a218651SEdgar E. Iglesias 105b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 106b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 107b89de436SEdgar E. Iglesias 108b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 109b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 110b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 111b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 112b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 113b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 114b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 115b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 116b89de436SEdgar E. Iglesias 117b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 118b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 119b89de436SEdgar E. Iglesias 120b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 121b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 122b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 123b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 124b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 125b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 126b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 127b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 128f0138990SEdgar E. Iglesias 129f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 130f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 131b89de436SEdgar E. Iglesias #endif 132