1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17*a55b441bSEdgar E. Iglesias #include "hw/or-irq.h" 18724c6e12SEdgar E. Iglesias #include "hw/sd/sdhci.h" 19b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 2088052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 21f4e3fa37SEdgar E. Iglesias #include "hw/dma/xlnx-zdma.h" 224bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 23eb1221c5SEdgar E. Iglesias #include "hw/rtc/xlnx-zynqmp-rtc.h" 24db1015e9SEduardo Habkost #include "qom/object.h" 25144677d4SVikram Garhwal #include "hw/usb/xlnx-usb-subsystem.h" 26*a55b441bSEdgar E. Iglesias #include "hw/misc/xlnx-versal-xramc.h" 27b89de436SEdgar E. Iglesias 28b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 298063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 30b89de436SEdgar E. Iglesias 31b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 32b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 33b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 348a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 35724c6e12SEdgar E. Iglesias #define XLNX_VERSAL_NR_SDS 2 36*a55b441bSEdgar E. Iglesias #define XLNX_VERSAL_NR_XRAM 4 37f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 38b89de436SEdgar E. Iglesias 39db1015e9SEduardo Habkost struct Versal { 40b89de436SEdgar E. Iglesias /*< private >*/ 41b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 42b89de436SEdgar E. Iglesias 43b89de436SEdgar E. Iglesias /*< public >*/ 44b89de436SEdgar E. Iglesias struct { 45b89de436SEdgar E. Iglesias struct { 46b89de436SEdgar E. Iglesias MemoryRegion mr; 47ced18d5eSEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 48b89de436SEdgar E. Iglesias GICv3State gic; 49b89de436SEdgar E. Iglesias } apu; 50b89de436SEdgar E. Iglesias } fpd; 51b89de436SEdgar E. Iglesias 52b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 53b89de436SEdgar E. Iglesias 54b89de436SEdgar E. Iglesias struct { 55b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 56b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 57b89de436SEdgar E. Iglesias } noc; 58b89de436SEdgar E. Iglesias 59b89de436SEdgar E. Iglesias struct { 60b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 61b89de436SEdgar E. Iglesias 62b89de436SEdgar E. Iglesias struct { 6388052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 644bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 65f4e3fa37SEdgar E. Iglesias XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 66144677d4SVikram Garhwal VersalUsb2 usb; 67b89de436SEdgar E. Iglesias } iou; 68*a55b441bSEdgar E. Iglesias 69*a55b441bSEdgar E. Iglesias struct { 70*a55b441bSEdgar E. Iglesias qemu_or_irq irq_orgate; 71*a55b441bSEdgar E. Iglesias XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 72*a55b441bSEdgar E. Iglesias } xram; 73b89de436SEdgar E. Iglesias } lpd; 74b89de436SEdgar E. Iglesias 75724c6e12SEdgar E. Iglesias /* The Platform Management Controller subsystem. */ 76724c6e12SEdgar E. Iglesias struct { 77724c6e12SEdgar E. Iglesias struct { 78724c6e12SEdgar E. Iglesias SDHCIState sd[XLNX_VERSAL_NR_SDS]; 79724c6e12SEdgar E. Iglesias } iou; 80eb1221c5SEdgar E. Iglesias 81eb1221c5SEdgar E. Iglesias XlnxZynqMPRTC rtc; 82724c6e12SEdgar E. Iglesias } pmc; 83724c6e12SEdgar E. Iglesias 84b89de436SEdgar E. Iglesias struct { 85b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 86b89de436SEdgar E. Iglesias uint32_t psci_conduit; 87b89de436SEdgar E. Iglesias } cfg; 88db1015e9SEduardo Habkost }; 89b89de436SEdgar E. Iglesias 90b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 91b89de436SEdgar E. Iglesias * auto-generated files. */ 92b89de436SEdgar E. Iglesias 93b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 94b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 95b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 96b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 97b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 98b89de436SEdgar E. Iglesias 99b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 100b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 101144677d4SVikram Garhwal #define VERSAL_USB0_IRQ_0 22 102b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 103b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 104b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 105b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 1068a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 107*a55b441bSEdgar E. Iglesias #define VERSAL_XRAM_IRQ_0 79 108eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_APB_ERR_IRQ 121 109724c6e12SEdgar E. Iglesias #define VERSAL_SD0_IRQ_0 126 110eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_ALARM_IRQ 142 111eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_SECONDS_IRQ 143 112b89de436SEdgar E. Iglesias 113fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 114fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 115fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 116b89de436SEdgar E. Iglesias 117b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 118b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 119b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 120b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 121b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 122b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 123b89de436SEdgar E. Iglesias 124b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 125b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 126b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 127b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 128b89de436SEdgar E. Iglesias 129b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 130b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 131b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 132b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 133b89de436SEdgar E. Iglesias 1348a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1358a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1368a218651SEdgar E. Iglesias 137b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 138b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 139b89de436SEdgar E. Iglesias 140*a55b441bSEdgar E. Iglesias #define MM_XRAM 0xfe800000 141*a55b441bSEdgar E. Iglesias #define MM_XRAMC 0xff8e0000 142*a55b441bSEdgar E. Iglesias #define MM_XRAMC_SIZE 0x10000 143*a55b441bSEdgar E. Iglesias 144144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS 0xFF9D0000 145144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS_SIZE 0x10000 146144677d4SVikram Garhwal 147144677d4SVikram Garhwal #define MM_USB_0 0xFE200000 148144677d4SVikram Garhwal #define MM_USB_0_SIZE 0x10000 149144677d4SVikram Garhwal 150b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 151b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 152b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 153b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 154b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 155b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 156b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 157b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 158b89de436SEdgar E. Iglesias 159b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 160b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 161b89de436SEdgar E. Iglesias 162b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 163b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 164b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 165b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 166b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 167b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 168b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 169b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 170f0138990SEdgar E. Iglesias 171724c6e12SEdgar E. Iglesias #define MM_PMC_SD0 0xf1040000U 172724c6e12SEdgar E. Iglesias #define MM_PMC_SD0_SIZE 0x10000 173f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 174f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 175eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC 0xf12a0000 176eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC_SIZE 0x10000 177b89de436SEdgar E. Iglesias #endif 178