1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 178779d00cSEdgar E. Iglesias #include "hw/cpu/cluster.h" 18a55b441bSEdgar E. Iglesias #include "hw/or-irq.h" 19724c6e12SEdgar E. Iglesias #include "hw/sd/sdhci.h" 20b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 2188052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 22f4e3fa37SEdgar E. Iglesias #include "hw/dma/xlnx-zdma.h" 234bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 24eb1221c5SEdgar E. Iglesias #include "hw/rtc/xlnx-zynqmp-rtc.h" 25db1015e9SEduardo Habkost #include "qom/object.h" 26144677d4SVikram Garhwal #include "hw/usb/xlnx-usb-subsystem.h" 27a55b441bSEdgar E. Iglesias #include "hw/misc/xlnx-versal-xramc.h" 28393185bcSTong Ho #include "hw/nvram/xlnx-bbram.h" 295f4910ffSTong Ho #include "hw/nvram/xlnx-versal-efuse.h" 30868d9680SFrancisco Iglesias #include "hw/ssi/xlnx-versal-ospi.h" 31868d9680SFrancisco Iglesias #include "hw/dma/xlnx_csu_dma.h" 32d6ccfc7eSEdgar E. Iglesias #include "hw/misc/xlnx-versal-crl.h" 33f7c9aecbSFrancisco Iglesias #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 34042d6b02SVikram Garhwal #include "hw/net/xlnx-versal-canfd.h" 35b286d08aSFrancisco Iglesias #include "hw/misc/xlnx-versal-cfu.h" 36b89de436SEdgar E. Iglesias 37b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 388063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 39b89de436SEdgar E. Iglesias 40b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 4167a645a3SEdgar E. Iglesias #define XLNX_VERSAL_NR_RCPUS 2 42b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 43b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 448a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 45724c6e12SEdgar E. Iglesias #define XLNX_VERSAL_NR_SDS 2 46a55b441bSEdgar E. Iglesias #define XLNX_VERSAL_NR_XRAM 4 47f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 48042d6b02SVikram Garhwal #define XLNX_VERSAL_NR_CANFD 2 49042d6b02SVikram Garhwal #define XLNX_VERSAL_CANFD_REF_CLK (24 * 1000 * 1000) 50b89de436SEdgar E. Iglesias 51db1015e9SEduardo Habkost struct Versal { 52b89de436SEdgar E. Iglesias /*< private >*/ 53b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 54b89de436SEdgar E. Iglesias 55b89de436SEdgar E. Iglesias /*< public >*/ 56b89de436SEdgar E. Iglesias struct { 57b89de436SEdgar E. Iglesias struct { 58b89de436SEdgar E. Iglesias MemoryRegion mr; 598779d00cSEdgar E. Iglesias CPUClusterState cluster; 60ced18d5eSEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 61b89de436SEdgar E. Iglesias GICv3State gic; 62b89de436SEdgar E. Iglesias } apu; 63b89de436SEdgar E. Iglesias } fpd; 64b89de436SEdgar E. Iglesias 65b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 66b89de436SEdgar E. Iglesias 67b89de436SEdgar E. Iglesias struct { 68b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 69b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 70b89de436SEdgar E. Iglesias } noc; 71b89de436SEdgar E. Iglesias 72b89de436SEdgar E. Iglesias struct { 73b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 74b89de436SEdgar E. Iglesias 75b89de436SEdgar E. Iglesias struct { 7688052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 774bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 78f4e3fa37SEdgar E. Iglesias XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 79144677d4SVikram Garhwal VersalUsb2 usb; 80042d6b02SVikram Garhwal CanBusState *canbus[XLNX_VERSAL_NR_CANFD]; 81042d6b02SVikram Garhwal XlnxVersalCANFDState canfd[XLNX_VERSAL_NR_CANFD]; 82b89de436SEdgar E. Iglesias } iou; 83a55b441bSEdgar E. Iglesias 8467a645a3SEdgar E. Iglesias /* Real-time Processing Unit. */ 8567a645a3SEdgar E. Iglesias struct { 8667a645a3SEdgar E. Iglesias MemoryRegion mr; 8767a645a3SEdgar E. Iglesias MemoryRegion mr_ps_alias; 8867a645a3SEdgar E. Iglesias 8967a645a3SEdgar E. Iglesias CPUClusterState cluster; 9067a645a3SEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; 9167a645a3SEdgar E. Iglesias } rpu; 9267a645a3SEdgar E. Iglesias 93a55b441bSEdgar E. Iglesias struct { 94e844f0c5SPhilippe Mathieu-Daudé OrIRQState irq_orgate; 95a55b441bSEdgar E. Iglesias XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 96a55b441bSEdgar E. Iglesias } xram; 97d6ccfc7eSEdgar E. Iglesias 98d6ccfc7eSEdgar E. Iglesias XlnxVersalCRL crl; 99b89de436SEdgar E. Iglesias } lpd; 100b89de436SEdgar E. Iglesias 101724c6e12SEdgar E. Iglesias /* The Platform Management Controller subsystem. */ 102724c6e12SEdgar E. Iglesias struct { 103724c6e12SEdgar E. Iglesias struct { 104724c6e12SEdgar E. Iglesias SDHCIState sd[XLNX_VERSAL_NR_SDS]; 105f7c9aecbSFrancisco Iglesias XlnxVersalPmcIouSlcr slcr; 106868d9680SFrancisco Iglesias 107868d9680SFrancisco Iglesias struct { 108868d9680SFrancisco Iglesias XlnxVersalOspi ospi; 109868d9680SFrancisco Iglesias XlnxCSUDMA dma_src; 110868d9680SFrancisco Iglesias XlnxCSUDMA dma_dst; 111868d9680SFrancisco Iglesias MemoryRegion linear_mr; 112e844f0c5SPhilippe Mathieu-Daudé OrIRQState irq_orgate; 113868d9680SFrancisco Iglesias } ospi; 114724c6e12SEdgar E. Iglesias } iou; 115eb1221c5SEdgar E. Iglesias 116eb1221c5SEdgar E. Iglesias XlnxZynqMPRTC rtc; 117393185bcSTong Ho XlnxBBRam bbram; 1185f4910ffSTong Ho XlnxEFuse efuse; 1195f4910ffSTong Ho XlnxVersalEFuseCtrl efuse_ctrl; 1205f4910ffSTong Ho XlnxVersalEFuseCache efuse_cache; 121b286d08aSFrancisco Iglesias XlnxVersalCFUAPB cfu_apb; 122b286d08aSFrancisco Iglesias XlnxVersalCFUFDRO cfu_fdro; 123b286d08aSFrancisco Iglesias XlnxVersalCFUSFR cfu_sfr; 1249a6d4918SFrancisco Iglesias 125e844f0c5SPhilippe Mathieu-Daudé OrIRQState apb_irq_orgate; 126724c6e12SEdgar E. Iglesias } pmc; 127724c6e12SEdgar E. Iglesias 128b89de436SEdgar E. Iglesias struct { 129b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 130b89de436SEdgar E. Iglesias } cfg; 131db1015e9SEduardo Habkost }; 132b89de436SEdgar E. Iglesias 133b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 134b89de436SEdgar E. Iglesias * auto-generated files. */ 135b89de436SEdgar E. Iglesias 136b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 137b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 138b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 139b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 140b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 141b89de436SEdgar E. Iglesias 142d6ccfc7eSEdgar E. Iglesias #define VERSAL_CRL_IRQ 10 143b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 144b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 145042d6b02SVikram Garhwal #define VERSAL_CANFD0_IRQ_0 20 146042d6b02SVikram Garhwal #define VERSAL_CANFD1_IRQ_0 21 147144677d4SVikram Garhwal #define VERSAL_USB0_IRQ_0 22 148b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 149b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 150b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 151b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 1528a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 153a55b441bSEdgar E. Iglesias #define VERSAL_XRAM_IRQ_0 79 154b286d08aSFrancisco Iglesias #define VERSAL_CFU_IRQ_0 120 1559a6d4918SFrancisco Iglesias #define VERSAL_PMC_APB_IRQ 121 156868d9680SFrancisco Iglesias #define VERSAL_OSPI_IRQ 124 157724c6e12SEdgar E. Iglesias #define VERSAL_SD0_IRQ_0 126 1585f4910ffSTong Ho #define VERSAL_EFUSE_IRQ 139 159eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_ALARM_IRQ 142 160eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_SECONDS_IRQ 143 161b89de436SEdgar E. Iglesias 162fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 163fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 164fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 165b89de436SEdgar E. Iglesias 166b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 167b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 168b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 169b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 170b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 171b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 172b89de436SEdgar E. Iglesias 173b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 174b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 175b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 176b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 177b89de436SEdgar E. Iglesias 178042d6b02SVikram Garhwal #define MM_CANFD0 0xff060000U 179042d6b02SVikram Garhwal #define MM_CANFD0_SIZE 0x10000 180042d6b02SVikram Garhwal #define MM_CANFD1 0xff070000U 181042d6b02SVikram Garhwal #define MM_CANFD1_SIZE 0x10000 182042d6b02SVikram Garhwal 183b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 184b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 185b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 186b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 187b89de436SEdgar E. Iglesias 1888a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1898a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1908a218651SEdgar E. Iglesias 191b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 192b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 193b89de436SEdgar E. Iglesias 194a55b441bSEdgar E. Iglesias #define MM_XRAM 0xfe800000 195a55b441bSEdgar E. Iglesias #define MM_XRAMC 0xff8e0000 196a55b441bSEdgar E. Iglesias #define MM_XRAMC_SIZE 0x10000 197a55b441bSEdgar E. Iglesias 198144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS 0xFF9D0000 199144677d4SVikram Garhwal #define MM_USB2_CTRL_REGS_SIZE 0x10000 200144677d4SVikram Garhwal 201144677d4SVikram Garhwal #define MM_USB_0 0xFE200000 202144677d4SVikram Garhwal #define MM_USB_0_SIZE 0x10000 203144677d4SVikram Garhwal 204b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 205b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 206b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 207b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 208b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 209b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 210b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 211b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 212b89de436SEdgar E. Iglesias 213b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 214b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 215b89de436SEdgar E. Iglesias 216b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 217b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 218b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 219b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 220b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 221b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 222b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 223b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 2249a0fcb7fSTong Ho #define MM_FPD_FPD_APU 0xfd5c0000 2259a0fcb7fSTong Ho #define MM_FPD_FPD_APU_SIZE 0x100 226f0138990SEdgar E. Iglesias 227f7c9aecbSFrancisco Iglesias #define MM_PMC_PMC_IOU_SLCR 0xf1060000 228f7c9aecbSFrancisco Iglesias #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 229f7c9aecbSFrancisco Iglesias 230868d9680SFrancisco Iglesias #define MM_PMC_OSPI 0xf1010000 231868d9680SFrancisco Iglesias #define MM_PMC_OSPI_SIZE 0x10000 232868d9680SFrancisco Iglesias 233868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DAC 0xc0000000 234868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DAC_SIZE 0x20000000 235868d9680SFrancisco Iglesias 236868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DMA_DST 0xf1011800 237868d9680SFrancisco Iglesias #define MM_PMC_OSPI_DMA_SRC 0xf1011000 238868d9680SFrancisco Iglesias 239724c6e12SEdgar E. Iglesias #define MM_PMC_SD0 0xf1040000U 240724c6e12SEdgar E. Iglesias #define MM_PMC_SD0_SIZE 0x10000 241393185bcSTong Ho #define MM_PMC_BBRAM_CTRL 0xf11f0000 242393185bcSTong Ho #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 2435f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL 0xf1240000 2445f4910ffSTong Ho #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 2455f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE 0xf1250000 2465f4910ffSTong Ho #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 2475f4910ffSTong Ho 248b286d08aSFrancisco Iglesias #define MM_PMC_CFU_APB 0xf12b0000 249b286d08aSFrancisco Iglesias #define MM_PMC_CFU_APB_SIZE 0x10000 250b286d08aSFrancisco Iglesias #define MM_PMC_CFU_STREAM 0xf12c0000 251b286d08aSFrancisco Iglesias #define MM_PMC_CFU_STREAM_SIZE 0x1000 252b286d08aSFrancisco Iglesias #define MM_PMC_CFU_SFR 0xf12c1000 253b286d08aSFrancisco Iglesias #define MM_PMC_CFU_SFR_SIZE 0x1000 254b286d08aSFrancisco Iglesias #define MM_PMC_CFU_FDRO 0xf12c2000 255b286d08aSFrancisco Iglesias #define MM_PMC_CFU_FDRO_SIZE 0x1000 256b286d08aSFrancisco Iglesias #define MM_PMC_CFU_STREAM_2 0xf1f80000 257b286d08aSFrancisco Iglesias #define MM_PMC_CFU_STREAM_2_SIZE 0x40000 258b286d08aSFrancisco Iglesias 259f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 260f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 261eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC 0xf12a0000 262eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC_SIZE 0x10000 263b89de436SEdgar E. Iglesias #endif 264