1*b89de436SEdgar E. Iglesias /* 2*b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3*b89de436SEdgar E. Iglesias * 4*b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5*b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6*b89de436SEdgar E. Iglesias * 7*b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8*b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9*b89de436SEdgar E. Iglesias * (at your option) any later version. 10*b89de436SEdgar E. Iglesias */ 11*b89de436SEdgar E. Iglesias 12*b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13*b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14*b89de436SEdgar E. Iglesias 15*b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 16*b89de436SEdgar E. Iglesias #include "hw/arm/arm.h" 17*b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 18*b89de436SEdgar E. Iglesias 19*b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 20*b89de436SEdgar E. Iglesias #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) 21*b89de436SEdgar E. Iglesias 22*b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 23*b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 24*b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 25*b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 256 26*b89de436SEdgar E. Iglesias 27*b89de436SEdgar E. Iglesias typedef struct Versal { 28*b89de436SEdgar E. Iglesias /*< private >*/ 29*b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 30*b89de436SEdgar E. Iglesias 31*b89de436SEdgar E. Iglesias /*< public >*/ 32*b89de436SEdgar E. Iglesias struct { 33*b89de436SEdgar E. Iglesias struct { 34*b89de436SEdgar E. Iglesias MemoryRegion mr; 35*b89de436SEdgar E. Iglesias ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; 36*b89de436SEdgar E. Iglesias GICv3State gic; 37*b89de436SEdgar E. Iglesias } apu; 38*b89de436SEdgar E. Iglesias } fpd; 39*b89de436SEdgar E. Iglesias 40*b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 41*b89de436SEdgar E. Iglesias 42*b89de436SEdgar E. Iglesias struct { 43*b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 44*b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 45*b89de436SEdgar E. Iglesias } noc; 46*b89de436SEdgar E. Iglesias 47*b89de436SEdgar E. Iglesias struct { 48*b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 49*b89de436SEdgar E. Iglesias 50*b89de436SEdgar E. Iglesias struct { 51*b89de436SEdgar E. Iglesias SysBusDevice *uart[XLNX_VERSAL_NR_UARTS]; 52*b89de436SEdgar E. Iglesias SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; 53*b89de436SEdgar E. Iglesias } iou; 54*b89de436SEdgar E. Iglesias } lpd; 55*b89de436SEdgar E. Iglesias 56*b89de436SEdgar E. Iglesias struct { 57*b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 58*b89de436SEdgar E. Iglesias uint32_t psci_conduit; 59*b89de436SEdgar E. Iglesias } cfg; 60*b89de436SEdgar E. Iglesias } Versal; 61*b89de436SEdgar E. Iglesias 62*b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 63*b89de436SEdgar E. Iglesias * auto-generated files. */ 64*b89de436SEdgar E. Iglesias 65*b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 66*b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 67*b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 68*b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 69*b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 70*b89de436SEdgar E. Iglesias 71*b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 72*b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 73*b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 74*b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 75*b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 76*b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 77*b89de436SEdgar E. Iglesias 78*b89de436SEdgar E. Iglesias /* Architecturally eserved IRQs suitable for virtualization. */ 79*b89de436SEdgar E. Iglesias #define VERSAL_RSVD_HIGH_IRQ_FIRST 160 80*b89de436SEdgar E. Iglesias #define VERSAL_RSVD_HIGH_IRQ_LAST 255 81*b89de436SEdgar E. Iglesias 82*b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 83*b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 84*b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 85*b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 86*b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 87*b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 88*b89de436SEdgar E. Iglesias 89*b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 90*b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 91*b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 92*b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 93*b89de436SEdgar E. Iglesias 94*b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 95*b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 96*b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 97*b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 98*b89de436SEdgar E. Iglesias 99*b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 100*b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 101*b89de436SEdgar E. Iglesias 102*b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 103*b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 104*b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 105*b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 106*b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 107*b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 108*b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 109*b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 110*b89de436SEdgar E. Iglesias 111*b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 112*b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 113*b89de436SEdgar E. Iglesias 114*b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 115*b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 116*b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 117*b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 118*b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 119*b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 120*b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 121*b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 122*b89de436SEdgar E. Iglesias #endif 123