1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17724c6e12SEdgar E. Iglesias #include "hw/sd/sdhci.h" 18b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 1988052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 20f4e3fa37SEdgar E. Iglesias #include "hw/dma/xlnx-zdma.h" 214bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 22eb1221c5SEdgar E. Iglesias #include "hw/rtc/xlnx-zynqmp-rtc.h" 23*db1015e9SEduardo Habkost #include "qom/object.h" 24b89de436SEdgar E. Iglesias 25b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 26*db1015e9SEduardo Habkost typedef struct Versal Versal; 27b89de436SEdgar E. Iglesias #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) 28b89de436SEdgar E. Iglesias 29b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 30b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 31b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 328a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 33724c6e12SEdgar E. Iglesias #define XLNX_VERSAL_NR_SDS 2 34f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 35b89de436SEdgar E. Iglesias 36*db1015e9SEduardo Habkost struct Versal { 37b89de436SEdgar E. Iglesias /*< private >*/ 38b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 39b89de436SEdgar E. Iglesias 40b89de436SEdgar E. Iglesias /*< public >*/ 41b89de436SEdgar E. Iglesias struct { 42b89de436SEdgar E. Iglesias struct { 43b89de436SEdgar E. Iglesias MemoryRegion mr; 44ced18d5eSEdgar E. Iglesias ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 45b89de436SEdgar E. Iglesias GICv3State gic; 46b89de436SEdgar E. Iglesias } apu; 47b89de436SEdgar E. Iglesias } fpd; 48b89de436SEdgar E. Iglesias 49b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 50b89de436SEdgar E. Iglesias 51b89de436SEdgar E. Iglesias struct { 52b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 53b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 54b89de436SEdgar E. Iglesias } noc; 55b89de436SEdgar E. Iglesias 56b89de436SEdgar E. Iglesias struct { 57b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 58b89de436SEdgar E. Iglesias 59b89de436SEdgar E. Iglesias struct { 6088052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 614bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 62f4e3fa37SEdgar E. Iglesias XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 63b89de436SEdgar E. Iglesias } iou; 64b89de436SEdgar E. Iglesias } lpd; 65b89de436SEdgar E. Iglesias 66724c6e12SEdgar E. Iglesias /* The Platform Management Controller subsystem. */ 67724c6e12SEdgar E. Iglesias struct { 68724c6e12SEdgar E. Iglesias struct { 69724c6e12SEdgar E. Iglesias SDHCIState sd[XLNX_VERSAL_NR_SDS]; 70724c6e12SEdgar E. Iglesias } iou; 71eb1221c5SEdgar E. Iglesias 72eb1221c5SEdgar E. Iglesias XlnxZynqMPRTC rtc; 73724c6e12SEdgar E. Iglesias } pmc; 74724c6e12SEdgar E. Iglesias 75b89de436SEdgar E. Iglesias struct { 76b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 77b89de436SEdgar E. Iglesias uint32_t psci_conduit; 78b89de436SEdgar E. Iglesias } cfg; 79*db1015e9SEduardo Habkost }; 80b89de436SEdgar E. Iglesias 81b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 82b89de436SEdgar E. Iglesias * auto-generated files. */ 83b89de436SEdgar E. Iglesias 84b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 85b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 86b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 87b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 88b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 89b89de436SEdgar E. Iglesias 90b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 91b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 92b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 93b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 94b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 95b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 968a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 97eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_APB_ERR_IRQ 121 98724c6e12SEdgar E. Iglesias #define VERSAL_SD0_IRQ_0 126 99eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_ALARM_IRQ 142 100eb1221c5SEdgar E. Iglesias #define VERSAL_RTC_SECONDS_IRQ 143 101b89de436SEdgar E. Iglesias 102fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 103fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 104fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 105b89de436SEdgar E. Iglesias 106b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 107b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 108b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 109b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 110b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 111b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 112b89de436SEdgar E. Iglesias 113b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 114b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 115b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 116b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 117b89de436SEdgar E. Iglesias 118b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 119b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 120b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 121b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 122b89de436SEdgar E. Iglesias 1238a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1248a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1258a218651SEdgar E. Iglesias 126b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 127b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 128b89de436SEdgar E. Iglesias 129b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 130b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 131b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 132b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 133b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 134b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 135b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 136b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 137b89de436SEdgar E. Iglesias 138b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 139b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 140b89de436SEdgar E. Iglesias 141b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 142b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 143b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 144b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 145b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 146b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 147b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 148b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 149f0138990SEdgar E. Iglesias 150724c6e12SEdgar E. Iglesias #define MM_PMC_SD0 0xf1040000U 151724c6e12SEdgar E. Iglesias #define MM_PMC_SD0_SIZE 0x10000 152f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 153f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 154eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC 0xf12a0000 155eb1221c5SEdgar E. Iglesias #define MM_PMC_RTC_SIZE 0x10000 156b89de436SEdgar E. Iglesias #endif 157