1b89de436SEdgar E. Iglesias /* 2b89de436SEdgar E. Iglesias * Model of the Xilinx Versal 3b89de436SEdgar E. Iglesias * 4b89de436SEdgar E. Iglesias * Copyright (c) 2018 Xilinx Inc. 5b89de436SEdgar E. Iglesias * Written by Edgar E. Iglesias 6b89de436SEdgar E. Iglesias * 7b89de436SEdgar E. Iglesias * This program is free software; you can redistribute it and/or modify 8b89de436SEdgar E. Iglesias * it under the terms of the GNU General Public License version 2 or 9b89de436SEdgar E. Iglesias * (at your option) any later version. 10b89de436SEdgar E. Iglesias */ 11b89de436SEdgar E. Iglesias 12b89de436SEdgar E. Iglesias #ifndef XLNX_VERSAL_H 13b89de436SEdgar E. Iglesias #define XLNX_VERSAL_H 14b89de436SEdgar E. Iglesias 15b89de436SEdgar E. Iglesias #include "hw/sysbus.h" 1612ec8bd5SPeter Maydell #include "hw/arm/boot.h" 17b89de436SEdgar E. Iglesias #include "hw/intc/arm_gicv3.h" 1888052ffdSEdgar E. Iglesias #include "hw/char/pl011.h" 19*f4e3fa37SEdgar E. Iglesias #include "hw/dma/xlnx-zdma.h" 204bd9b59cSEdgar E. Iglesias #include "hw/net/cadence_gem.h" 21b89de436SEdgar E. Iglesias 22b89de436SEdgar E. Iglesias #define TYPE_XLNX_VERSAL "xlnx-versal" 23b89de436SEdgar E. Iglesias #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) 24b89de436SEdgar E. Iglesias 25b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_ACPUS 2 26b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_UARTS 2 27b89de436SEdgar E. Iglesias #define XLNX_VERSAL_NR_GEMS 2 288a218651SEdgar E. Iglesias #define XLNX_VERSAL_NR_ADMAS 8 29f6ef171dSEdgar E. Iglesias #define XLNX_VERSAL_NR_IRQS 192 30b89de436SEdgar E. Iglesias 31b89de436SEdgar E. Iglesias typedef struct Versal { 32b89de436SEdgar E. Iglesias /*< private >*/ 33b89de436SEdgar E. Iglesias SysBusDevice parent_obj; 34b89de436SEdgar E. Iglesias 35b89de436SEdgar E. Iglesias /*< public >*/ 36b89de436SEdgar E. Iglesias struct { 37b89de436SEdgar E. Iglesias struct { 38b89de436SEdgar E. Iglesias MemoryRegion mr; 39b89de436SEdgar E. Iglesias ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; 40b89de436SEdgar E. Iglesias GICv3State gic; 41b89de436SEdgar E. Iglesias } apu; 42b89de436SEdgar E. Iglesias } fpd; 43b89de436SEdgar E. Iglesias 44b89de436SEdgar E. Iglesias MemoryRegion mr_ps; 45b89de436SEdgar E. Iglesias 46b89de436SEdgar E. Iglesias struct { 47b89de436SEdgar E. Iglesias /* 4 ranges to access DDR. */ 48b89de436SEdgar E. Iglesias MemoryRegion mr_ddr_ranges[4]; 49b89de436SEdgar E. Iglesias } noc; 50b89de436SEdgar E. Iglesias 51b89de436SEdgar E. Iglesias struct { 52b89de436SEdgar E. Iglesias MemoryRegion mr_ocm; 53b89de436SEdgar E. Iglesias 54b89de436SEdgar E. Iglesias struct { 5588052ffdSEdgar E. Iglesias PL011State uart[XLNX_VERSAL_NR_UARTS]; 564bd9b59cSEdgar E. Iglesias CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 57*f4e3fa37SEdgar E. Iglesias XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 58b89de436SEdgar E. Iglesias } iou; 59b89de436SEdgar E. Iglesias } lpd; 60b89de436SEdgar E. Iglesias 61b89de436SEdgar E. Iglesias struct { 62b89de436SEdgar E. Iglesias MemoryRegion *mr_ddr; 63b89de436SEdgar E. Iglesias uint32_t psci_conduit; 64b89de436SEdgar E. Iglesias } cfg; 65b89de436SEdgar E. Iglesias } Versal; 66b89de436SEdgar E. Iglesias 67b89de436SEdgar E. Iglesias /* Memory-map and IRQ definitions. Copied a subset from 68b89de436SEdgar E. Iglesias * auto-generated files. */ 69b89de436SEdgar E. Iglesias 70b89de436SEdgar E. Iglesias #define VERSAL_GIC_MAINT_IRQ 9 71b89de436SEdgar E. Iglesias #define VERSAL_TIMER_VIRT_IRQ 11 72b89de436SEdgar E. Iglesias #define VERSAL_TIMER_S_EL1_IRQ 13 73b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL1_IRQ 14 74b89de436SEdgar E. Iglesias #define VERSAL_TIMER_NS_EL2_IRQ 10 75b89de436SEdgar E. Iglesias 76b89de436SEdgar E. Iglesias #define VERSAL_UART0_IRQ_0 18 77b89de436SEdgar E. Iglesias #define VERSAL_UART1_IRQ_0 19 78b89de436SEdgar E. Iglesias #define VERSAL_GEM0_IRQ_0 56 79b89de436SEdgar E. Iglesias #define VERSAL_GEM0_WAKE_IRQ_0 57 80b89de436SEdgar E. Iglesias #define VERSAL_GEM1_IRQ_0 58 81b89de436SEdgar E. Iglesias #define VERSAL_GEM1_WAKE_IRQ_0 59 828a218651SEdgar E. Iglesias #define VERSAL_ADMA_IRQ_0 60 83b89de436SEdgar E. Iglesias 84fb179055SEdgar E. Iglesias /* Architecturally reserved IRQs suitable for virtualization. */ 85fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_FIRST 111 86fb179055SEdgar E. Iglesias #define VERSAL_RSVD_IRQ_LAST 118 87b89de436SEdgar E. Iglesias 88b89de436SEdgar E. Iglesias #define MM_TOP_RSVD 0xa0000000U 89b89de436SEdgar E. Iglesias #define MM_TOP_RSVD_SIZE 0x4000000 90b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN 0xf9000000U 91b89de436SEdgar E. Iglesias #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 92b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0 0xf9080000U 93b89de436SEdgar E. Iglesias #define MM_GIC_APU_REDIST_0_SIZE 0x80000 94b89de436SEdgar E. Iglesias 95b89de436SEdgar E. Iglesias #define MM_UART0 0xff000000U 96b89de436SEdgar E. Iglesias #define MM_UART0_SIZE 0x10000 97b89de436SEdgar E. Iglesias #define MM_UART1 0xff010000U 98b89de436SEdgar E. Iglesias #define MM_UART1_SIZE 0x10000 99b89de436SEdgar E. Iglesias 100b89de436SEdgar E. Iglesias #define MM_GEM0 0xff0c0000U 101b89de436SEdgar E. Iglesias #define MM_GEM0_SIZE 0x10000 102b89de436SEdgar E. Iglesias #define MM_GEM1 0xff0d0000U 103b89de436SEdgar E. Iglesias #define MM_GEM1_SIZE 0x10000 104b89de436SEdgar E. Iglesias 1058a218651SEdgar E. Iglesias #define MM_ADMA_CH0 0xffa80000U 1068a218651SEdgar E. Iglesias #define MM_ADMA_CH0_SIZE 0x10000 1078a218651SEdgar E. Iglesias 108b89de436SEdgar E. Iglesias #define MM_OCM 0xfffc0000U 109b89de436SEdgar E. Iglesias #define MM_OCM_SIZE 0x40000 110b89de436SEdgar E. Iglesias 111b89de436SEdgar E. Iglesias #define MM_TOP_DDR 0x0 112b89de436SEdgar E. Iglesias #define MM_TOP_DDR_SIZE 0x80000000U 113b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2 0x800000000ULL 114b89de436SEdgar E. Iglesias #define MM_TOP_DDR_2_SIZE 0x800000000ULL 115b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3 0xc000000000ULL 116b89de436SEdgar E. Iglesias #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 117b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4 0x10000000000ULL 118b89de436SEdgar E. Iglesias #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 119b89de436SEdgar E. Iglesias 120b89de436SEdgar E. Iglesias #define MM_PSM_START 0xffc80000U 121b89de436SEdgar E. Iglesias #define MM_PSM_END 0xffcf0000U 122b89de436SEdgar E. Iglesias 123b89de436SEdgar E. Iglesias #define MM_CRL 0xff5e0000U 124b89de436SEdgar E. Iglesias #define MM_CRL_SIZE 0x300000 125b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR 0xff130000U 126b89de436SEdgar E. Iglesias #define MM_IOU_SCNTR_SIZE 0x10000 127b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS 0xff140000U 128b89de436SEdgar E. Iglesias #define MM_IOU_SCNTRS_SIZE 0x10000 129b89de436SEdgar E. Iglesias #define MM_FPD_CRF 0xfd1a0000U 130b89de436SEdgar E. Iglesias #define MM_FPD_CRF_SIZE 0x140000 131f0138990SEdgar E. Iglesias 132f0138990SEdgar E. Iglesias #define MM_PMC_CRP 0xf1260000U 133f0138990SEdgar E. Iglesias #define MM_PMC_CRP_SIZE 0x10000 134b89de436SEdgar E. Iglesias #endif 135