1 /* 2 * Model of the Xilinx Versal 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #ifndef XLNX_VERSAL_H 13 #define XLNX_VERSAL_H 14 15 #include "hw/sysbus.h" 16 #include "hw/arm/boot.h" 17 #include "hw/intc/arm_gicv3.h" 18 19 #define TYPE_XLNX_VERSAL "xlnx-versal" 20 #define XLNX_VERSAL(obj) OBJECT_CHECK(Versal, (obj), TYPE_XLNX_VERSAL) 21 22 #define XLNX_VERSAL_NR_ACPUS 2 23 #define XLNX_VERSAL_NR_UARTS 2 24 #define XLNX_VERSAL_NR_GEMS 2 25 #define XLNX_VERSAL_NR_ADMAS 8 26 #define XLNX_VERSAL_NR_IRQS 192 27 28 typedef struct Versal { 29 /*< private >*/ 30 SysBusDevice parent_obj; 31 32 /*< public >*/ 33 struct { 34 struct { 35 MemoryRegion mr; 36 ARMCPU *cpu[XLNX_VERSAL_NR_ACPUS]; 37 GICv3State gic; 38 } apu; 39 } fpd; 40 41 MemoryRegion mr_ps; 42 43 struct { 44 /* 4 ranges to access DDR. */ 45 MemoryRegion mr_ddr_ranges[4]; 46 } noc; 47 48 struct { 49 MemoryRegion mr_ocm; 50 51 struct { 52 SysBusDevice *uart[XLNX_VERSAL_NR_UARTS]; 53 SysBusDevice *gem[XLNX_VERSAL_NR_GEMS]; 54 SysBusDevice *adma[XLNX_VERSAL_NR_ADMAS]; 55 } iou; 56 } lpd; 57 58 struct { 59 MemoryRegion *mr_ddr; 60 uint32_t psci_conduit; 61 } cfg; 62 } Versal; 63 64 /* Memory-map and IRQ definitions. Copied a subset from 65 * auto-generated files. */ 66 67 #define VERSAL_GIC_MAINT_IRQ 9 68 #define VERSAL_TIMER_VIRT_IRQ 11 69 #define VERSAL_TIMER_S_EL1_IRQ 13 70 #define VERSAL_TIMER_NS_EL1_IRQ 14 71 #define VERSAL_TIMER_NS_EL2_IRQ 10 72 73 #define VERSAL_UART0_IRQ_0 18 74 #define VERSAL_UART1_IRQ_0 19 75 #define VERSAL_GEM0_IRQ_0 56 76 #define VERSAL_GEM0_WAKE_IRQ_0 57 77 #define VERSAL_GEM1_IRQ_0 58 78 #define VERSAL_GEM1_WAKE_IRQ_0 59 79 #define VERSAL_ADMA_IRQ_0 60 80 81 /* Architecturally reserved IRQs suitable for virtualization. */ 82 #define VERSAL_RSVD_IRQ_FIRST 111 83 #define VERSAL_RSVD_IRQ_LAST 118 84 85 #define MM_TOP_RSVD 0xa0000000U 86 #define MM_TOP_RSVD_SIZE 0x4000000 87 #define MM_GIC_APU_DIST_MAIN 0xf9000000U 88 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 89 #define MM_GIC_APU_REDIST_0 0xf9080000U 90 #define MM_GIC_APU_REDIST_0_SIZE 0x80000 91 92 #define MM_UART0 0xff000000U 93 #define MM_UART0_SIZE 0x10000 94 #define MM_UART1 0xff010000U 95 #define MM_UART1_SIZE 0x10000 96 97 #define MM_GEM0 0xff0c0000U 98 #define MM_GEM0_SIZE 0x10000 99 #define MM_GEM1 0xff0d0000U 100 #define MM_GEM1_SIZE 0x10000 101 102 #define MM_ADMA_CH0 0xffa80000U 103 #define MM_ADMA_CH0_SIZE 0x10000 104 105 #define MM_OCM 0xfffc0000U 106 #define MM_OCM_SIZE 0x40000 107 108 #define MM_TOP_DDR 0x0 109 #define MM_TOP_DDR_SIZE 0x80000000U 110 #define MM_TOP_DDR_2 0x800000000ULL 111 #define MM_TOP_DDR_2_SIZE 0x800000000ULL 112 #define MM_TOP_DDR_3 0xc000000000ULL 113 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 114 #define MM_TOP_DDR_4 0x10000000000ULL 115 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 116 117 #define MM_PSM_START 0xffc80000U 118 #define MM_PSM_END 0xffcf0000U 119 120 #define MM_CRL 0xff5e0000U 121 #define MM_CRL_SIZE 0x300000 122 #define MM_IOU_SCNTR 0xff130000U 123 #define MM_IOU_SCNTR_SIZE 0x10000 124 #define MM_IOU_SCNTRS 0xff140000U 125 #define MM_IOU_SCNTRS_SIZE 0x10000 126 #define MM_FPD_CRF 0xfd1a0000U 127 #define MM_FPD_CRF_SIZE 0x140000 128 129 #define MM_PMC_CRP 0xf1260000U 130 #define MM_PMC_CRP_SIZE 0x10000 131 #endif 132