1 /* 2 * Model of the Xilinx Versal 3 * 4 * Copyright (c) 2018 Xilinx Inc. 5 * Written by Edgar E. Iglesias 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 or 9 * (at your option) any later version. 10 */ 11 12 #ifndef XLNX_VERSAL_H 13 #define XLNX_VERSAL_H 14 15 #include "hw/sysbus.h" 16 #include "hw/arm/boot.h" 17 #include "hw/or-irq.h" 18 #include "hw/sd/sdhci.h" 19 #include "hw/intc/arm_gicv3.h" 20 #include "hw/char/pl011.h" 21 #include "hw/dma/xlnx-zdma.h" 22 #include "hw/net/cadence_gem.h" 23 #include "hw/rtc/xlnx-zynqmp-rtc.h" 24 #include "qom/object.h" 25 #include "hw/usb/xlnx-usb-subsystem.h" 26 #include "hw/misc/xlnx-versal-xramc.h" 27 #include "hw/nvram/xlnx-bbram.h" 28 #include "hw/nvram/xlnx-versal-efuse.h" 29 #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" 30 31 #define TYPE_XLNX_VERSAL "xlnx-versal" 32 OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) 33 34 #define XLNX_VERSAL_NR_ACPUS 2 35 #define XLNX_VERSAL_NR_UARTS 2 36 #define XLNX_VERSAL_NR_GEMS 2 37 #define XLNX_VERSAL_NR_ADMAS 8 38 #define XLNX_VERSAL_NR_SDS 2 39 #define XLNX_VERSAL_NR_XRAM 4 40 #define XLNX_VERSAL_NR_IRQS 192 41 42 struct Versal { 43 /*< private >*/ 44 SysBusDevice parent_obj; 45 46 /*< public >*/ 47 struct { 48 struct { 49 MemoryRegion mr; 50 ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; 51 GICv3State gic; 52 } apu; 53 } fpd; 54 55 MemoryRegion mr_ps; 56 57 struct { 58 /* 4 ranges to access DDR. */ 59 MemoryRegion mr_ddr_ranges[4]; 60 } noc; 61 62 struct { 63 MemoryRegion mr_ocm; 64 65 struct { 66 PL011State uart[XLNX_VERSAL_NR_UARTS]; 67 CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; 68 XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; 69 VersalUsb2 usb; 70 } iou; 71 72 struct { 73 qemu_or_irq irq_orgate; 74 XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; 75 } xram; 76 } lpd; 77 78 /* The Platform Management Controller subsystem. */ 79 struct { 80 struct { 81 SDHCIState sd[XLNX_VERSAL_NR_SDS]; 82 XlnxVersalPmcIouSlcr slcr; 83 } iou; 84 85 XlnxZynqMPRTC rtc; 86 XlnxBBRam bbram; 87 XlnxEFuse efuse; 88 XlnxVersalEFuseCtrl efuse_ctrl; 89 XlnxVersalEFuseCache efuse_cache; 90 91 qemu_or_irq apb_irq_orgate; 92 } pmc; 93 94 struct { 95 MemoryRegion *mr_ddr; 96 uint32_t psci_conduit; 97 } cfg; 98 }; 99 100 /* Memory-map and IRQ definitions. Copied a subset from 101 * auto-generated files. */ 102 103 #define VERSAL_GIC_MAINT_IRQ 9 104 #define VERSAL_TIMER_VIRT_IRQ 11 105 #define VERSAL_TIMER_S_EL1_IRQ 13 106 #define VERSAL_TIMER_NS_EL1_IRQ 14 107 #define VERSAL_TIMER_NS_EL2_IRQ 10 108 109 #define VERSAL_UART0_IRQ_0 18 110 #define VERSAL_UART1_IRQ_0 19 111 #define VERSAL_USB0_IRQ_0 22 112 #define VERSAL_GEM0_IRQ_0 56 113 #define VERSAL_GEM0_WAKE_IRQ_0 57 114 #define VERSAL_GEM1_IRQ_0 58 115 #define VERSAL_GEM1_WAKE_IRQ_0 59 116 #define VERSAL_ADMA_IRQ_0 60 117 #define VERSAL_XRAM_IRQ_0 79 118 #define VERSAL_PMC_APB_IRQ 121 119 #define VERSAL_SD0_IRQ_0 126 120 #define VERSAL_EFUSE_IRQ 139 121 #define VERSAL_RTC_ALARM_IRQ 142 122 #define VERSAL_RTC_SECONDS_IRQ 143 123 124 /* Architecturally reserved IRQs suitable for virtualization. */ 125 #define VERSAL_RSVD_IRQ_FIRST 111 126 #define VERSAL_RSVD_IRQ_LAST 118 127 128 #define MM_TOP_RSVD 0xa0000000U 129 #define MM_TOP_RSVD_SIZE 0x4000000 130 #define MM_GIC_APU_DIST_MAIN 0xf9000000U 131 #define MM_GIC_APU_DIST_MAIN_SIZE 0x10000 132 #define MM_GIC_APU_REDIST_0 0xf9080000U 133 #define MM_GIC_APU_REDIST_0_SIZE 0x80000 134 135 #define MM_UART0 0xff000000U 136 #define MM_UART0_SIZE 0x10000 137 #define MM_UART1 0xff010000U 138 #define MM_UART1_SIZE 0x10000 139 140 #define MM_GEM0 0xff0c0000U 141 #define MM_GEM0_SIZE 0x10000 142 #define MM_GEM1 0xff0d0000U 143 #define MM_GEM1_SIZE 0x10000 144 145 #define MM_ADMA_CH0 0xffa80000U 146 #define MM_ADMA_CH0_SIZE 0x10000 147 148 #define MM_OCM 0xfffc0000U 149 #define MM_OCM_SIZE 0x40000 150 151 #define MM_XRAM 0xfe800000 152 #define MM_XRAMC 0xff8e0000 153 #define MM_XRAMC_SIZE 0x10000 154 155 #define MM_USB2_CTRL_REGS 0xFF9D0000 156 #define MM_USB2_CTRL_REGS_SIZE 0x10000 157 158 #define MM_USB_0 0xFE200000 159 #define MM_USB_0_SIZE 0x10000 160 161 #define MM_TOP_DDR 0x0 162 #define MM_TOP_DDR_SIZE 0x80000000U 163 #define MM_TOP_DDR_2 0x800000000ULL 164 #define MM_TOP_DDR_2_SIZE 0x800000000ULL 165 #define MM_TOP_DDR_3 0xc000000000ULL 166 #define MM_TOP_DDR_3_SIZE 0x4000000000ULL 167 #define MM_TOP_DDR_4 0x10000000000ULL 168 #define MM_TOP_DDR_4_SIZE 0xb780000000ULL 169 170 #define MM_PSM_START 0xffc80000U 171 #define MM_PSM_END 0xffcf0000U 172 173 #define MM_CRL 0xff5e0000U 174 #define MM_CRL_SIZE 0x300000 175 #define MM_IOU_SCNTR 0xff130000U 176 #define MM_IOU_SCNTR_SIZE 0x10000 177 #define MM_IOU_SCNTRS 0xff140000U 178 #define MM_IOU_SCNTRS_SIZE 0x10000 179 #define MM_FPD_CRF 0xfd1a0000U 180 #define MM_FPD_CRF_SIZE 0x140000 181 #define MM_FPD_FPD_APU 0xfd5c0000 182 #define MM_FPD_FPD_APU_SIZE 0x100 183 184 #define MM_PMC_PMC_IOU_SLCR 0xf1060000 185 #define MM_PMC_PMC_IOU_SLCR_SIZE 0x10000 186 187 #define MM_PMC_SD0 0xf1040000U 188 #define MM_PMC_SD0_SIZE 0x10000 189 #define MM_PMC_BBRAM_CTRL 0xf11f0000 190 #define MM_PMC_BBRAM_CTRL_SIZE 0x00050 191 #define MM_PMC_EFUSE_CTRL 0xf1240000 192 #define MM_PMC_EFUSE_CTRL_SIZE 0x00104 193 #define MM_PMC_EFUSE_CACHE 0xf1250000 194 #define MM_PMC_EFUSE_CACHE_SIZE 0x00C00 195 196 #define MM_PMC_CRP 0xf1260000U 197 #define MM_PMC_CRP_SIZE 0x10000 198 #define MM_PMC_RTC 0xf12a0000 199 #define MM_PMC_RTC_SIZE 0x10000 200 #endif 201