1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 20 #include "qemu-common.h" 21 #include "hw/arm/arm.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 #include "hw/ide/pci.h" 26 #include "hw/ide/ahci.h" 27 #include "hw/sd/sdhci.h" 28 #include "hw/ssi/xilinx_spips.h" 29 #include "hw/dma/xlnx_dpdma.h" 30 #include "hw/display/xlnx_dp.h" 31 #include "hw/intc/xlnx-zynqmp-ipi.h" 32 #include "hw/timer/xlnx-zynqmp-rtc.h" 33 34 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 35 #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ 36 TYPE_XLNX_ZYNQMP) 37 38 #define XLNX_ZYNQMP_NUM_APU_CPUS 4 39 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 40 #define XLNX_ZYNQMP_NUM_GEMS 4 41 #define XLNX_ZYNQMP_NUM_UARTS 2 42 #define XLNX_ZYNQMP_NUM_SDHCI 2 43 #define XLNX_ZYNQMP_NUM_SPIS 2 44 45 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 46 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 47 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 48 49 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 50 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 51 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 52 53 #define XLNX_ZYNQMP_GIC_REGIONS 2 54 55 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 56 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 57 * aligned address in the 64k region. To implement each GIC region needs a 58 * number of memory region aliases. 59 */ 60 61 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 62 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1) 63 64 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull 65 66 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull 67 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull 68 69 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ 70 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) 71 72 typedef struct XlnxZynqMPState { 73 /*< private >*/ 74 DeviceState parent_obj; 75 76 /*< public >*/ 77 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 78 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 79 GICState gic; 80 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 81 82 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 83 84 MemoryRegion *ddr_ram; 85 MemoryRegion ddr_ram_low, ddr_ram_high; 86 87 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 88 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 89 SysbusAHCIState sata; 90 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; 91 XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; 92 XlnxZynqMPQSPIPS qspi; 93 XlnxDPState dp; 94 XlnxDPDMAState dpdma; 95 XlnxZynqMPIPI ipi; 96 XlnxZynqMPRTC rtc; 97 98 char *boot_cpu; 99 ARMCPU *boot_cpu_ptr; 100 101 /* Has the ARM Security extensions? */ 102 bool secure; 103 /* Has the ARM Virtualization extensions? */ 104 bool virt; 105 /* Has the RPU subsystem? */ 106 bool has_rpu; 107 } XlnxZynqMPState; 108 109 #define XLNX_ZYNQMP_H 110 #endif 111