1 /* 2 * Xilinx Zynq MPSoC emulation 3 * 4 * Copyright (C) 2015 Xilinx Inc 5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or 10 * (at your option) any later version. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 * for more details. 16 */ 17 18 #ifndef XLNX_ZYNQMP_H 19 #define XLNX_ZYNQMP_H 20 21 #include "hw/arm/boot.h" 22 #include "hw/intc/arm_gic.h" 23 #include "hw/net/cadence_gem.h" 24 #include "hw/char/cadence_uart.h" 25 #include "hw/ide/ahci.h" 26 #include "hw/sd/sdhci.h" 27 #include "hw/ssi/xilinx_spips.h" 28 #include "hw/dma/xlnx_dpdma.h" 29 #include "hw/dma/xlnx-zdma.h" 30 #include "hw/display/xlnx_dp.h" 31 #include "hw/intc/xlnx-zynqmp-ipi.h" 32 #include "hw/rtc/xlnx-zynqmp-rtc.h" 33 #include "hw/cpu/cluster.h" 34 #include "target/arm/cpu.h" 35 #include "qom/object.h" 36 37 #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" 38 typedef struct XlnxZynqMPState XlnxZynqMPState; 39 DECLARE_INSTANCE_CHECKER(XlnxZynqMPState, XLNX_ZYNQMP, 40 TYPE_XLNX_ZYNQMP) 41 42 #define XLNX_ZYNQMP_NUM_APU_CPUS 4 43 #define XLNX_ZYNQMP_NUM_RPU_CPUS 2 44 #define XLNX_ZYNQMP_NUM_GEMS 4 45 #define XLNX_ZYNQMP_NUM_UARTS 2 46 #define XLNX_ZYNQMP_NUM_SDHCI 2 47 #define XLNX_ZYNQMP_NUM_SPIS 2 48 #define XLNX_ZYNQMP_NUM_GDMA_CH 8 49 #define XLNX_ZYNQMP_NUM_ADMA_CH 8 50 51 #define XLNX_ZYNQMP_NUM_QSPI_BUS 2 52 #define XLNX_ZYNQMP_NUM_QSPI_BUS_CS 2 53 #define XLNX_ZYNQMP_NUM_QSPI_FLASH 4 54 55 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4 56 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 57 #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000 58 59 #define XLNX_ZYNQMP_GIC_REGIONS 6 60 61 /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets 62 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k 63 * aligned address in the 64k region. To implement each GIC region needs a 64 * number of memory region aliases. 65 */ 66 67 #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000 68 #define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE) 69 70 #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull 71 72 #define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE 0x800000000ull 73 #define XLNX_ZYNQMP_HIGH_RAM_START 0x800000000ull 74 75 #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ 76 XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) 77 78 struct XlnxZynqMPState { 79 /*< private >*/ 80 DeviceState parent_obj; 81 82 /*< public >*/ 83 CPUClusterState apu_cluster; 84 CPUClusterState rpu_cluster; 85 ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS]; 86 ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS]; 87 GICState gic; 88 MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES]; 89 90 MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS]; 91 92 MemoryRegion *ddr_ram; 93 MemoryRegion ddr_ram_low, ddr_ram_high; 94 95 CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS]; 96 CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; 97 SysbusAHCIState sata; 98 SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; 99 XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS]; 100 XlnxZynqMPQSPIPS qspi; 101 XlnxDPState dp; 102 XlnxDPDMAState dpdma; 103 XlnxZynqMPIPI ipi; 104 XlnxZynqMPRTC rtc; 105 XlnxZDMA gdma[XLNX_ZYNQMP_NUM_GDMA_CH]; 106 XlnxZDMA adma[XLNX_ZYNQMP_NUM_ADMA_CH]; 107 108 char *boot_cpu; 109 ARMCPU *boot_cpu_ptr; 110 111 /* Has the ARM Security extensions? */ 112 bool secure; 113 /* Has the ARM Virtualization extensions? */ 114 bool virt; 115 /* Has the RPU subsystem? */ 116 bool has_rpu; 117 }; 118 119 #endif 120