1 /* 2 * QEMU 16550A UART emulation 3 * 4 * Copyright (c) 2003-2004 Fabrice Bellard 5 * Copyright (c) 2008 Citrix Systems, Inc. 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 #ifndef HW_SERIAL_H 26 #define HW_SERIAL_H 1 27 28 #include "hw/hw.h" 29 #include "sysemu/sysemu.h" 30 #include "exec/memory.h" 31 #include "qemu/fifo8.h" 32 33 #define UART_FIFO_LENGTH 16 /* 16550A Fifo Length */ 34 35 struct SerialState { 36 uint16_t divider; 37 uint8_t rbr; /* receive register */ 38 uint8_t thr; /* transmit holding register */ 39 uint8_t tsr; /* transmit shift register */ 40 uint8_t ier; 41 uint8_t iir; /* read only */ 42 uint8_t lcr; 43 uint8_t mcr; 44 uint8_t lsr; /* read only */ 45 uint8_t msr; /* read only */ 46 uint8_t scr; 47 uint8_t fcr; 48 uint8_t fcr_vmstate; /* we can't write directly this value 49 it has side effects */ 50 /* NOTE: this hidden state is necessary for tx irq generation as 51 it can be reset while reading iir */ 52 int thr_ipending; 53 qemu_irq irq; 54 CharDriverState *chr; 55 int last_break_enable; 56 int it_shift; 57 int baudbase; 58 uint32_t tsr_retry; 59 guint watch_tag; 60 uint32_t wakeup; 61 62 /* Time when the last byte was successfully sent out of the tsr */ 63 uint64_t last_xmit_ts; 64 Fifo8 recv_fifo; 65 Fifo8 xmit_fifo; 66 /* Interrupt trigger level for recv_fifo */ 67 uint8_t recv_fifo_itl; 68 69 QEMUTimer *fifo_timeout_timer; 70 int timeout_ipending; /* timeout interrupt pending state */ 71 72 uint64_t char_transmit_time; /* time to transmit a char in ticks */ 73 int poll_msl; 74 75 QEMUTimer *modem_status_poll; 76 MemoryRegion io; 77 }; 78 79 extern const VMStateDescription vmstate_serial; 80 extern const MemoryRegionOps serial_io_ops; 81 82 void serial_realize_core(SerialState *s, Error **errp); 83 void serial_exit_core(SerialState *s); 84 void serial_set_frequency(SerialState *s, uint32_t frequency); 85 86 /* legacy pre qom */ 87 SerialState *serial_init(int base, qemu_irq irq, int baudbase, 88 CharDriverState *chr, MemoryRegion *system_io); 89 SerialState *serial_mm_init(MemoryRegion *address_space, 90 hwaddr base, int it_shift, 91 qemu_irq irq, int baudbase, 92 CharDriverState *chr, enum device_endian end); 93 94 /* serial-isa.c */ 95 #define TYPE_ISA_SERIAL "isa-serial" 96 void serial_hds_isa_init(ISABus *bus, int n); 97 98 #endif 99