1 /* 2 * QEMU CPU model 3 * 4 * Copyright (c) 2012 SUSE LINUX Products GmbH 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * as published by the Free Software Foundation; either version 2 9 * of the License, or (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, see 18 * <http://www.gnu.org/licenses/gpl-2.0.html> 19 */ 20 #ifndef QEMU_CPU_H 21 #define QEMU_CPU_H 22 23 #include "hw/qdev-core.h" 24 #include "disas/dis-asm.h" 25 #include "exec/breakpoint.h" 26 #include "exec/hwaddr.h" 27 #include "exec/vaddr.h" 28 #include "exec/memattrs.h" 29 #include "exec/mmu-access-type.h" 30 #include "exec/tlb-common.h" 31 #include "qapi/qapi-types-machine.h" 32 #include "qapi/qapi-types-run-state.h" 33 #include "qemu/bitmap.h" 34 #include "qemu/rcu_queue.h" 35 #include "qemu/queue.h" 36 #include "qemu/thread.h" 37 #include "qom/object.h" 38 39 typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, 40 void *opaque); 41 42 /** 43 * SECTION:cpu 44 * @section_id: QEMU-cpu 45 * @title: CPU Class 46 * @short_description: Base class for all CPUs 47 */ 48 49 #define TYPE_CPU "cpu" 50 51 /* Since this macro is used a lot in hot code paths and in conjunction with 52 * FooCPU *foo_env_get_cpu(), we deviate from usual QOM practice by using 53 * an unchecked cast. 54 */ 55 #define CPU(obj) ((CPUState *)(obj)) 56 57 /* 58 * The class checkers bring in CPU_GET_CLASS() which is potentially 59 * expensive given the eventual call to 60 * object_class_dynamic_cast_assert(). Because of this the CPUState 61 * has a cached value for the class in cs->cc which is set up in 62 * cpu_exec_realizefn() for use in hot code paths. 63 */ 64 typedef struct CPUClass CPUClass; 65 DECLARE_CLASS_CHECKERS(CPUClass, CPU, 66 TYPE_CPU) 67 68 /** 69 * OBJECT_DECLARE_CPU_TYPE: 70 * @CpuInstanceType: instance struct name 71 * @CpuClassType: class struct name 72 * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separators 73 * 74 * This macro is typically used in "cpu-qom.h" header file, and will: 75 * 76 * - create the typedefs for the CPU object and class structs 77 * - register the type for use with g_autoptr 78 * - provide three standard type cast functions 79 * 80 * The object struct and class struct need to be declared manually. 81 */ 82 #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME) \ 83 typedef struct ArchCPU CpuInstanceType; \ 84 OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); 85 86 typedef struct CPUWatchpoint CPUWatchpoint; 87 88 /* see physmem.c */ 89 struct CPUAddressSpace; 90 91 /* see accel/tcg/tb-jmp-cache.h */ 92 struct CPUJumpCache; 93 94 /* see accel-cpu.h */ 95 struct AccelCPUClass; 96 97 /* see sysemu-cpu-ops.h */ 98 struct SysemuCPUOps; 99 100 /** 101 * CPUClass: 102 * @class_by_name: Callback to map -cpu command line model name to an 103 * instantiatable CPU type. 104 * @parse_features: Callback to parse command line arguments. 105 * @reset_dump_flags: #CPUDumpFlags to use for reset logging. 106 * @has_work: Callback for checking if there is work to do. 107 * @mmu_index: Callback for choosing softmmu mmu index; 108 * may be used internally by memory_rw_debug without TCG. 109 * @memory_rw_debug: Callback for GDB memory access. 110 * @dump_state: Callback for dumping state. 111 * @query_cpu_fast: 112 * Fill in target specific information for the "query-cpus-fast" 113 * QAPI call. 114 * @get_arch_id: Callback for getting architecture-dependent CPU ID. 115 * @set_pc: Callback for setting the Program Counter register. This 116 * should have the semantics used by the target architecture when 117 * setting the PC from a source such as an ELF file entry point; 118 * for example on Arm it will also set the Thumb mode bit based 119 * on the least significant bit of the new PC value. 120 * If the target behaviour here is anything other than "set 121 * the PC register to the value passed in" then the target must 122 * also implement the synchronize_from_tb hook. 123 * @get_pc: Callback for getting the Program Counter register. 124 * As above, with the semantics of the target architecture. 125 * @gdb_read_register: Callback for letting GDB read a register. 126 * @gdb_write_register: Callback for letting GDB write a register. 127 * @gdb_adjust_breakpoint: Callback for adjusting the address of a 128 * breakpoint. Used by AVR to handle a gdb mis-feature with 129 * its Harvard architecture split code and data. 130 * @gdb_num_core_regs: Number of core registers accessible to GDB or 0 to infer 131 * from @gdb_core_xml_file. 132 * @gdb_core_xml_file: File name for core registers GDB XML description. 133 * @gdb_stop_before_watchpoint: Indicates whether GDB expects the CPU to stop 134 * before the insn which triggers a watchpoint rather than after it. 135 * @gdb_arch_name: Optional callback that returns the architecture name known 136 * to GDB. The caller must free the returned string with g_free. 137 * @disas_set_info: Setup architecture specific components of disassembly info 138 * @adjust_watchpoint_address: Perform a target-specific adjustment to an 139 * address before attempting to match it against watchpoints. 140 * @deprecation_note: If this CPUClass is deprecated, this field provides 141 * related information. 142 * 143 * Represents a CPU family or model. 144 */ 145 struct CPUClass { 146 /*< private >*/ 147 DeviceClass parent_class; 148 /*< public >*/ 149 150 ObjectClass *(*class_by_name)(const char *cpu_model); 151 void (*parse_features)(const char *typename, char *str, Error **errp); 152 153 bool (*has_work)(CPUState *cpu); 154 int (*mmu_index)(CPUState *cpu, bool ifetch); 155 int (*memory_rw_debug)(CPUState *cpu, vaddr addr, 156 uint8_t *buf, int len, bool is_write); 157 void (*dump_state)(CPUState *cpu, FILE *, int flags); 158 void (*query_cpu_fast)(CPUState *cpu, CpuInfoFast *value); 159 int64_t (*get_arch_id)(CPUState *cpu); 160 void (*set_pc)(CPUState *cpu, vaddr value); 161 vaddr (*get_pc)(CPUState *cpu); 162 int (*gdb_read_register)(CPUState *cpu, GByteArray *buf, int reg); 163 int (*gdb_write_register)(CPUState *cpu, uint8_t *buf, int reg); 164 vaddr (*gdb_adjust_breakpoint)(CPUState *cpu, vaddr addr); 165 166 const char *gdb_core_xml_file; 167 const gchar * (*gdb_arch_name)(CPUState *cpu); 168 169 void (*disas_set_info)(CPUState *cpu, disassemble_info *info); 170 171 const char *deprecation_note; 172 struct AccelCPUClass *accel_cpu; 173 174 /* when system emulation is not available, this pointer is NULL */ 175 const struct SysemuCPUOps *sysemu_ops; 176 177 /* when TCG is not available, this pointer is NULL */ 178 const TCGCPUOps *tcg_ops; 179 180 /* 181 * if not NULL, this is called in order for the CPUClass to initialize 182 * class data that depends on the accelerator, see accel/accel-common.c. 183 */ 184 void (*init_accel_cpu)(struct AccelCPUClass *accel_cpu, CPUClass *cc); 185 186 /* 187 * Keep non-pointer data at the end to minimize holes. 188 */ 189 int reset_dump_flags; 190 int gdb_num_core_regs; 191 bool gdb_stop_before_watchpoint; 192 }; 193 194 /* 195 * Fix the number of mmu modes to 16, which is also the maximum 196 * supported by the softmmu tlb api. 197 */ 198 #define NB_MMU_MODES 16 199 200 /* Use a fully associative victim tlb of 8 entries. */ 201 #define CPU_VTLB_SIZE 8 202 203 /* 204 * The full TLB entry, which is not accessed by generated TCG code, 205 * so the layout is not as critical as that of CPUTLBEntry. This is 206 * also why we don't want to combine the two structs. 207 */ 208 typedef struct CPUTLBEntryFull { 209 /* 210 * @xlat_section contains: 211 * - in the lower TARGET_PAGE_BITS, a physical section number 212 * - with the lower TARGET_PAGE_BITS masked off, an offset which 213 * must be added to the virtual address to obtain: 214 * + the ram_addr_t of the target RAM (if the physical section 215 * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) 216 * + the offset within the target MemoryRegion (otherwise) 217 */ 218 hwaddr xlat_section; 219 220 /* 221 * @phys_addr contains the physical address in the address space 222 * given by cpu_asidx_from_attrs(cpu, @attrs). 223 */ 224 hwaddr phys_addr; 225 226 /* @attrs contains the memory transaction attributes for the page. */ 227 MemTxAttrs attrs; 228 229 /* @prot contains the complete protections for the page. */ 230 uint8_t prot; 231 232 /* @lg_page_size contains the log2 of the page size. */ 233 uint8_t lg_page_size; 234 235 /* Additional tlb flags requested by tlb_fill. */ 236 uint8_t tlb_fill_flags; 237 238 /* 239 * Additional tlb flags for use by the slow path. If non-zero, 240 * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. 241 */ 242 uint8_t slow_flags[MMU_ACCESS_COUNT]; 243 244 /* 245 * Allow target-specific additions to this structure. 246 * This may be used to cache items from the guest cpu 247 * page tables for later use by the implementation. 248 */ 249 union { 250 /* 251 * Cache the attrs and shareability fields from the page table entry. 252 * 253 * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. 254 * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. 255 * For shareability and guarded, as in the SH and GP fields respectively 256 * of the VMSAv8-64 PTEs. 257 */ 258 struct { 259 uint8_t pte_attrs; 260 uint8_t shareability; 261 bool guarded; 262 } arm; 263 } extra; 264 } CPUTLBEntryFull; 265 266 /* 267 * Data elements that are per MMU mode, minus the bits accessed by 268 * the TCG fast path. 269 */ 270 typedef struct CPUTLBDesc { 271 /* 272 * Describe a region covering all of the large pages allocated 273 * into the tlb. When any page within this region is flushed, 274 * we must flush the entire tlb. The region is matched if 275 * (addr & large_page_mask) == large_page_addr. 276 */ 277 vaddr large_page_addr; 278 vaddr large_page_mask; 279 /* host time (in ns) at the beginning of the time window */ 280 int64_t window_begin_ns; 281 /* maximum number of entries observed in the window */ 282 size_t window_max_entries; 283 size_t n_used_entries; 284 /* The next index to use in the tlb victim table. */ 285 size_t vindex; 286 /* The tlb victim table, in two parts. */ 287 CPUTLBEntry vtable[CPU_VTLB_SIZE]; 288 CPUTLBEntryFull vfulltlb[CPU_VTLB_SIZE]; 289 CPUTLBEntryFull *fulltlb; 290 } CPUTLBDesc; 291 292 /* 293 * Data elements that are shared between all MMU modes. 294 */ 295 typedef struct CPUTLBCommon { 296 /* Serialize updates to f.table and d.vtable, and others as noted. */ 297 QemuSpin lock; 298 /* 299 * Within dirty, for each bit N, modifications have been made to 300 * mmu_idx N since the last time that mmu_idx was flushed. 301 * Protected by tlb_c.lock. 302 */ 303 uint16_t dirty; 304 /* 305 * Statistics. These are not lock protected, but are read and 306 * written atomically. This allows the monitor to print a snapshot 307 * of the stats without interfering with the cpu. 308 */ 309 size_t full_flush_count; 310 size_t part_flush_count; 311 size_t elide_flush_count; 312 } CPUTLBCommon; 313 314 /* 315 * The entire softmmu tlb, for all MMU modes. 316 * The meaning of each of the MMU modes is defined in the target code. 317 * Since this is placed within CPUNegativeOffsetState, the smallest 318 * negative offsets are at the end of the struct. 319 */ 320 typedef struct CPUTLB { 321 #ifdef CONFIG_TCG 322 CPUTLBCommon c; 323 CPUTLBDesc d[NB_MMU_MODES]; 324 CPUTLBDescFast f[NB_MMU_MODES]; 325 #endif 326 } CPUTLB; 327 328 /* 329 * Low 16 bits: number of cycles left, used only in icount mode. 330 * High 16 bits: Set to -1 to force TCG to stop executing linked TBs 331 * for this CPU and return to its top level loop (even in non-icount mode). 332 * This allows a single read-compare-cbranch-write sequence to test 333 * for both decrementer underflow and exceptions. 334 */ 335 typedef union IcountDecr { 336 uint32_t u32; 337 struct { 338 #if HOST_BIG_ENDIAN 339 uint16_t high; 340 uint16_t low; 341 #else 342 uint16_t low; 343 uint16_t high; 344 #endif 345 } u16; 346 } IcountDecr; 347 348 /* 349 * Elements of CPUState most efficiently accessed from CPUArchState, 350 * via small negative offsets. 351 */ 352 typedef struct CPUNegativeOffsetState { 353 CPUTLB tlb; 354 IcountDecr icount_decr; 355 bool can_do_io; 356 } CPUNegativeOffsetState; 357 358 struct KVMState; 359 struct kvm_run; 360 361 /* work queue */ 362 363 /* The union type allows passing of 64 bit target pointers on 32 bit 364 * hosts in a single parameter 365 */ 366 typedef union { 367 int host_int; 368 unsigned long host_ulong; 369 void *host_ptr; 370 vaddr target_ptr; 371 } run_on_cpu_data; 372 373 #define RUN_ON_CPU_HOST_PTR(p) ((run_on_cpu_data){.host_ptr = (p)}) 374 #define RUN_ON_CPU_HOST_INT(i) ((run_on_cpu_data){.host_int = (i)}) 375 #define RUN_ON_CPU_HOST_ULONG(ul) ((run_on_cpu_data){.host_ulong = (ul)}) 376 #define RUN_ON_CPU_TARGET_PTR(v) ((run_on_cpu_data){.target_ptr = (v)}) 377 #define RUN_ON_CPU_NULL RUN_ON_CPU_HOST_PTR(NULL) 378 379 typedef void (*run_on_cpu_func)(CPUState *cpu, run_on_cpu_data data); 380 381 struct qemu_work_item; 382 383 #define CPU_UNSET_NUMA_NODE_ID -1 384 385 /** 386 * CPUState: 387 * @cpu_index: CPU index (informative). 388 * @cluster_index: Identifies which cluster this CPU is in. 389 * For boards which don't define clusters or for "loose" CPUs not assigned 390 * to a cluster this will be UNASSIGNED_CLUSTER_INDEX; otherwise it will 391 * be the same as the cluster-id property of the CPU object's TYPE_CPU_CLUSTER 392 * QOM parent. 393 * Under TCG this value is propagated to @tcg_cflags. 394 * See TranslationBlock::TCG CF_CLUSTER_MASK. 395 * @tcg_cflags: Pre-computed cflags for this cpu. 396 * @nr_cores: Number of cores within this CPU package. 397 * @nr_threads: Number of threads within this CPU core. 398 * @running: #true if CPU is currently running (lockless). 399 * @has_waiter: #true if a CPU is currently waiting for the cpu_exec_end; 400 * valid under cpu_list_lock. 401 * @created: Indicates whether the CPU thread has been successfully created. 402 * @interrupt_request: Indicates a pending interrupt request. 403 * @halted: Nonzero if the CPU is in suspended state. 404 * @stop: Indicates a pending stop request. 405 * @stopped: Indicates the CPU has been artificially stopped. 406 * @unplug: Indicates a pending CPU unplug request. 407 * @crash_occurred: Indicates the OS reported a crash (panic) for this CPU 408 * @singlestep_enabled: Flags for single-stepping. 409 * @icount_extra: Instructions until next timer event. 410 * @neg.can_do_io: True if memory-mapped IO is allowed. 411 * @cpu_ases: Pointer to array of CPUAddressSpaces (which define the 412 * AddressSpaces this CPU has) 413 * @num_ases: number of CPUAddressSpaces in @cpu_ases 414 * @as: Pointer to the first AddressSpace, for the convenience of targets which 415 * only have a single AddressSpace 416 * @gdb_regs: Additional GDB registers. 417 * @gdb_num_regs: Number of total registers accessible to GDB. 418 * @gdb_num_g_regs: Number of registers in GDB 'g' packets. 419 * @node: QTAILQ of CPUs sharing TB cache. 420 * @opaque: User data. 421 * @mem_io_pc: Host Program Counter at which the memory was accessed. 422 * @accel: Pointer to accelerator specific state. 423 * @kvm_fd: vCPU file descriptor for KVM. 424 * @work_mutex: Lock to prevent multiple access to @work_list. 425 * @work_list: List of pending asynchronous work. 426 * @plugin_mem_cbs: active plugin memory callbacks 427 * @plugin_state: per-CPU plugin state 428 * @ignore_memory_transaction_failures: Cached copy of the MachineState 429 * flag of the same name: allows the board to suppress calling of the 430 * CPU do_transaction_failed hook function. 431 * @kvm_dirty_gfns: Points to the KVM dirty ring for this CPU when KVM dirty 432 * ring is enabled. 433 * @kvm_fetch_index: Keeps the index that we last fetched from the per-vCPU 434 * dirty ring structure. 435 * 436 * State of one CPU core or thread. 437 * 438 * Align, in order to match possible alignment required by CPUArchState, 439 * and eliminate a hole between CPUState and CPUArchState within ArchCPU. 440 */ 441 struct CPUState { 442 /*< private >*/ 443 DeviceState parent_obj; 444 /* cache to avoid expensive CPU_GET_CLASS */ 445 CPUClass *cc; 446 /*< public >*/ 447 448 int nr_cores; 449 int nr_threads; 450 451 struct QemuThread *thread; 452 #ifdef _WIN32 453 QemuSemaphore sem; 454 #endif 455 int thread_id; 456 bool running, has_waiter; 457 struct QemuCond *halt_cond; 458 bool thread_kicked; 459 bool created; 460 bool stop; 461 bool stopped; 462 463 /* Should CPU start in powered-off state? */ 464 bool start_powered_off; 465 466 bool unplug; 467 bool crash_occurred; 468 bool exit_request; 469 int exclusive_context_count; 470 uint32_t cflags_next_tb; 471 /* updates protected by BQL */ 472 uint32_t interrupt_request; 473 int singlestep_enabled; 474 int64_t icount_budget; 475 int64_t icount_extra; 476 uint64_t random_seed; 477 sigjmp_buf jmp_env; 478 479 QemuMutex work_mutex; 480 QSIMPLEQ_HEAD(, qemu_work_item) work_list; 481 482 struct CPUAddressSpace *cpu_ases; 483 int num_ases; 484 AddressSpace *as; 485 MemoryRegion *memory; 486 487 struct CPUJumpCache *tb_jmp_cache; 488 489 GArray *gdb_regs; 490 int gdb_num_regs; 491 int gdb_num_g_regs; 492 QTAILQ_ENTRY(CPUState) node; 493 494 /* ice debug support */ 495 QTAILQ_HEAD(, CPUBreakpoint) breakpoints; 496 497 QTAILQ_HEAD(, CPUWatchpoint) watchpoints; 498 CPUWatchpoint *watchpoint_hit; 499 500 void *opaque; 501 502 /* In order to avoid passing too many arguments to the MMIO helpers, 503 * we store some rarely used information in the CPU context. 504 */ 505 uintptr_t mem_io_pc; 506 507 /* Only used in KVM */ 508 int kvm_fd; 509 struct KVMState *kvm_state; 510 struct kvm_run *kvm_run; 511 struct kvm_dirty_gfn *kvm_dirty_gfns; 512 uint32_t kvm_fetch_index; 513 uint64_t dirty_pages; 514 int kvm_vcpu_stats_fd; 515 bool vcpu_dirty; 516 517 /* Use by accel-block: CPU is executing an ioctl() */ 518 QemuLockCnt in_ioctl_lock; 519 520 #ifdef CONFIG_PLUGIN 521 /* 522 * The callback pointer stays in the main CPUState as it is 523 * accessed via TCG (see gen_empty_mem_helper). 524 */ 525 GArray *plugin_mem_cbs; 526 CPUPluginState *plugin_state; 527 #endif 528 529 /* TODO Move common fields from CPUArchState here. */ 530 int cpu_index; 531 int cluster_index; 532 uint32_t tcg_cflags; 533 uint32_t halted; 534 int32_t exception_index; 535 536 AccelCPUState *accel; 537 538 /* Used to keep track of an outstanding cpu throttle thread for migration 539 * autoconverge 540 */ 541 bool throttle_thread_scheduled; 542 543 /* 544 * Sleep throttle_us_per_full microseconds once dirty ring is full 545 * if dirty page rate limit is enabled. 546 */ 547 int64_t throttle_us_per_full; 548 549 bool ignore_memory_transaction_failures; 550 551 /* Used for user-only emulation of prctl(PR_SET_UNALIGN). */ 552 bool prctl_unalign_sigbus; 553 554 /* track IOMMUs whose translations we've cached in the TCG TLB */ 555 GArray *iommu_notifiers; 556 557 /* 558 * MUST BE LAST in order to minimize the displacement to CPUArchState. 559 */ 560 char neg_align[-sizeof(CPUNegativeOffsetState) % 16] QEMU_ALIGNED(16); 561 CPUNegativeOffsetState neg; 562 }; 563 564 /* Validate placement of CPUNegativeOffsetState. */ 565 QEMU_BUILD_BUG_ON(offsetof(CPUState, neg) != 566 sizeof(CPUState) - sizeof(CPUNegativeOffsetState)); 567 568 static inline CPUArchState *cpu_env(CPUState *cpu) 569 { 570 /* We validate that CPUArchState follows CPUState in cpu-all.h. */ 571 return (CPUArchState *)(cpu + 1); 572 } 573 574 typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; 575 extern CPUTailQ cpus_queue; 576 577 #define first_cpu QTAILQ_FIRST_RCU(&cpus_queue) 578 #define CPU_NEXT(cpu) QTAILQ_NEXT_RCU(cpu, node) 579 #define CPU_FOREACH(cpu) QTAILQ_FOREACH_RCU(cpu, &cpus_queue, node) 580 #define CPU_FOREACH_SAFE(cpu, next_cpu) \ 581 QTAILQ_FOREACH_SAFE_RCU(cpu, &cpus_queue, node, next_cpu) 582 583 extern __thread CPUState *current_cpu; 584 585 /** 586 * qemu_tcg_mttcg_enabled: 587 * Check whether we are running MultiThread TCG or not. 588 * 589 * Returns: %true if we are in MTTCG mode %false otherwise. 590 */ 591 extern bool mttcg_enabled; 592 #define qemu_tcg_mttcg_enabled() (mttcg_enabled) 593 594 /** 595 * cpu_paging_enabled: 596 * @cpu: The CPU whose state is to be inspected. 597 * 598 * Returns: %true if paging is enabled, %false otherwise. 599 */ 600 bool cpu_paging_enabled(const CPUState *cpu); 601 602 /** 603 * cpu_get_memory_mapping: 604 * @cpu: The CPU whose memory mappings are to be obtained. 605 * @list: Where to write the memory mappings to. 606 * @errp: Pointer for reporting an #Error. 607 * 608 * Returns: %true on success, %false otherwise. 609 */ 610 bool cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list, 611 Error **errp); 612 613 #if !defined(CONFIG_USER_ONLY) 614 615 /** 616 * cpu_write_elf64_note: 617 * @f: pointer to a function that writes memory to a file 618 * @cpu: The CPU whose memory is to be dumped 619 * @cpuid: ID number of the CPU 620 * @opaque: pointer to the CPUState struct 621 */ 622 int cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, 623 int cpuid, void *opaque); 624 625 /** 626 * cpu_write_elf64_qemunote: 627 * @f: pointer to a function that writes memory to a file 628 * @cpu: The CPU whose memory is to be dumped 629 * @cpuid: ID number of the CPU 630 * @opaque: pointer to the CPUState struct 631 */ 632 int cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 633 void *opaque); 634 635 /** 636 * cpu_write_elf32_note: 637 * @f: pointer to a function that writes memory to a file 638 * @cpu: The CPU whose memory is to be dumped 639 * @cpuid: ID number of the CPU 640 * @opaque: pointer to the CPUState struct 641 */ 642 int cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu, 643 int cpuid, void *opaque); 644 645 /** 646 * cpu_write_elf32_qemunote: 647 * @f: pointer to a function that writes memory to a file 648 * @cpu: The CPU whose memory is to be dumped 649 * @cpuid: ID number of the CPU 650 * @opaque: pointer to the CPUState struct 651 */ 652 int cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu, 653 void *opaque); 654 655 /** 656 * cpu_get_crash_info: 657 * @cpu: The CPU to get crash information for 658 * 659 * Gets the previously saved crash information. 660 * Caller is responsible for freeing the data. 661 */ 662 GuestPanicInformation *cpu_get_crash_info(CPUState *cpu); 663 664 #endif /* !CONFIG_USER_ONLY */ 665 666 /** 667 * CPUDumpFlags: 668 * @CPU_DUMP_CODE: 669 * @CPU_DUMP_FPU: dump FPU register state, not just integer 670 * @CPU_DUMP_CCOP: dump info about TCG QEMU's condition code optimization state 671 * @CPU_DUMP_VPU: dump VPU registers 672 */ 673 enum CPUDumpFlags { 674 CPU_DUMP_CODE = 0x00010000, 675 CPU_DUMP_FPU = 0x00020000, 676 CPU_DUMP_CCOP = 0x00040000, 677 CPU_DUMP_VPU = 0x00080000, 678 }; 679 680 /** 681 * cpu_dump_state: 682 * @cpu: The CPU whose state is to be dumped. 683 * @f: If non-null, dump to this stream, else to current print sink. 684 * 685 * Dumps CPU state. 686 */ 687 void cpu_dump_state(CPUState *cpu, FILE *f, int flags); 688 689 #ifndef CONFIG_USER_ONLY 690 /** 691 * cpu_get_phys_page_attrs_debug: 692 * @cpu: The CPU to obtain the physical page address for. 693 * @addr: The virtual address. 694 * @attrs: Updated on return with the memory transaction attributes to use 695 * for this access. 696 * 697 * Obtains the physical page corresponding to a virtual one, together 698 * with the corresponding memory transaction attributes to use for the access. 699 * Use it only for debugging because no protection checks are done. 700 * 701 * Returns: Corresponding physical page address or -1 if no page found. 702 */ 703 hwaddr cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr, 704 MemTxAttrs *attrs); 705 706 /** 707 * cpu_get_phys_page_debug: 708 * @cpu: The CPU to obtain the physical page address for. 709 * @addr: The virtual address. 710 * 711 * Obtains the physical page corresponding to a virtual one. 712 * Use it only for debugging because no protection checks are done. 713 * 714 * Returns: Corresponding physical page address or -1 if no page found. 715 */ 716 hwaddr cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); 717 718 /** cpu_asidx_from_attrs: 719 * @cpu: CPU 720 * @attrs: memory transaction attributes 721 * 722 * Returns the address space index specifying the CPU AddressSpace 723 * to use for a memory access with the given transaction attributes. 724 */ 725 int cpu_asidx_from_attrs(CPUState *cpu, MemTxAttrs attrs); 726 727 /** 728 * cpu_virtio_is_big_endian: 729 * @cpu: CPU 730 731 * Returns %true if a CPU which supports runtime configurable endianness 732 * is currently big-endian. 733 */ 734 bool cpu_virtio_is_big_endian(CPUState *cpu); 735 736 #endif /* CONFIG_USER_ONLY */ 737 738 /** 739 * cpu_list_add: 740 * @cpu: The CPU to be added to the list of CPUs. 741 */ 742 void cpu_list_add(CPUState *cpu); 743 744 /** 745 * cpu_list_remove: 746 * @cpu: The CPU to be removed from the list of CPUs. 747 */ 748 void cpu_list_remove(CPUState *cpu); 749 750 /** 751 * cpu_reset: 752 * @cpu: The CPU whose state is to be reset. 753 */ 754 void cpu_reset(CPUState *cpu); 755 756 /** 757 * cpu_class_by_name: 758 * @typename: The CPU base type. 759 * @cpu_model: The model string without any parameters. 760 * 761 * Looks up a concrete CPU #ObjectClass matching name @cpu_model. 762 * 763 * Returns: A concrete #CPUClass or %NULL if no matching class is found 764 * or if the matching class is abstract. 765 */ 766 ObjectClass *cpu_class_by_name(const char *typename, const char *cpu_model); 767 768 /** 769 * cpu_model_from_type: 770 * @typename: The CPU type name 771 * 772 * Extract the CPU model name from the CPU type name. The 773 * CPU type name is either the combination of the CPU model 774 * name and suffix, or same to the CPU model name. 775 * 776 * Returns: CPU model name or NULL if the CPU class doesn't exist 777 * The user should g_free() the string once no longer needed. 778 */ 779 char *cpu_model_from_type(const char *typename); 780 781 /** 782 * cpu_create: 783 * @typename: The CPU type. 784 * 785 * Instantiates a CPU and realizes the CPU. 786 * 787 * Returns: A #CPUState or %NULL if an error occurred. 788 */ 789 CPUState *cpu_create(const char *typename); 790 791 /** 792 * parse_cpu_option: 793 * @cpu_option: The -cpu option including optional parameters. 794 * 795 * processes optional parameters and registers them as global properties 796 * 797 * Returns: type of CPU to create or prints error and terminates process 798 * if an error occurred. 799 */ 800 const char *parse_cpu_option(const char *cpu_option); 801 802 /** 803 * cpu_has_work: 804 * @cpu: The vCPU to check. 805 * 806 * Checks whether the CPU has work to do. 807 * 808 * Returns: %true if the CPU has work, %false otherwise. 809 */ 810 static inline bool cpu_has_work(CPUState *cpu) 811 { 812 CPUClass *cc = CPU_GET_CLASS(cpu); 813 814 g_assert(cc->has_work); 815 return cc->has_work(cpu); 816 } 817 818 /** 819 * qemu_cpu_is_self: 820 * @cpu: The vCPU to check against. 821 * 822 * Checks whether the caller is executing on the vCPU thread. 823 * 824 * Returns: %true if called from @cpu's thread, %false otherwise. 825 */ 826 bool qemu_cpu_is_self(CPUState *cpu); 827 828 /** 829 * qemu_cpu_kick: 830 * @cpu: The vCPU to kick. 831 * 832 * Kicks @cpu's thread. 833 */ 834 void qemu_cpu_kick(CPUState *cpu); 835 836 /** 837 * cpu_is_stopped: 838 * @cpu: The CPU to check. 839 * 840 * Checks whether the CPU is stopped. 841 * 842 * Returns: %true if run state is not running or if artificially stopped; 843 * %false otherwise. 844 */ 845 bool cpu_is_stopped(CPUState *cpu); 846 847 /** 848 * do_run_on_cpu: 849 * @cpu: The vCPU to run on. 850 * @func: The function to be executed. 851 * @data: Data to pass to the function. 852 * @mutex: Mutex to release while waiting for @func to run. 853 * 854 * Used internally in the implementation of run_on_cpu. 855 */ 856 void do_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data, 857 QemuMutex *mutex); 858 859 /** 860 * run_on_cpu: 861 * @cpu: The vCPU to run on. 862 * @func: The function to be executed. 863 * @data: Data to pass to the function. 864 * 865 * Schedules the function @func for execution on the vCPU @cpu. 866 */ 867 void run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 868 869 /** 870 * async_run_on_cpu: 871 * @cpu: The vCPU to run on. 872 * @func: The function to be executed. 873 * @data: Data to pass to the function. 874 * 875 * Schedules the function @func for execution on the vCPU @cpu asynchronously. 876 */ 877 void async_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 878 879 /** 880 * async_safe_run_on_cpu: 881 * @cpu: The vCPU to run on. 882 * @func: The function to be executed. 883 * @data: Data to pass to the function. 884 * 885 * Schedules the function @func for execution on the vCPU @cpu asynchronously, 886 * while all other vCPUs are sleeping. 887 * 888 * Unlike run_on_cpu and async_run_on_cpu, the function is run outside the 889 * BQL. 890 */ 891 void async_safe_run_on_cpu(CPUState *cpu, run_on_cpu_func func, run_on_cpu_data data); 892 893 /** 894 * cpu_in_exclusive_context() 895 * @cpu: The vCPU to check 896 * 897 * Returns true if @cpu is an exclusive context, for example running 898 * something which has previously been queued via async_safe_run_on_cpu(). 899 */ 900 static inline bool cpu_in_exclusive_context(const CPUState *cpu) 901 { 902 return cpu->exclusive_context_count; 903 } 904 905 /** 906 * qemu_get_cpu: 907 * @index: The CPUState@cpu_index value of the CPU to obtain. 908 * 909 * Gets a CPU matching @index. 910 * 911 * Returns: The CPU or %NULL if there is no matching CPU. 912 */ 913 CPUState *qemu_get_cpu(int index); 914 915 /** 916 * cpu_exists: 917 * @id: Guest-exposed CPU ID to lookup. 918 * 919 * Search for CPU with specified ID. 920 * 921 * Returns: %true - CPU is found, %false - CPU isn't found. 922 */ 923 bool cpu_exists(int64_t id); 924 925 /** 926 * cpu_by_arch_id: 927 * @id: Guest-exposed CPU ID of the CPU to obtain. 928 * 929 * Get a CPU with matching @id. 930 * 931 * Returns: The CPU or %NULL if there is no matching CPU. 932 */ 933 CPUState *cpu_by_arch_id(int64_t id); 934 935 /** 936 * cpu_interrupt: 937 * @cpu: The CPU to set an interrupt on. 938 * @mask: The interrupts to set. 939 * 940 * Invokes the interrupt handler. 941 */ 942 943 void cpu_interrupt(CPUState *cpu, int mask); 944 945 /** 946 * cpu_set_pc: 947 * @cpu: The CPU to set the program counter for. 948 * @addr: Program counter value. 949 * 950 * Sets the program counter for a CPU. 951 */ 952 static inline void cpu_set_pc(CPUState *cpu, vaddr addr) 953 { 954 CPUClass *cc = CPU_GET_CLASS(cpu); 955 956 cc->set_pc(cpu, addr); 957 } 958 959 /** 960 * cpu_reset_interrupt: 961 * @cpu: The CPU to clear the interrupt on. 962 * @mask: The interrupt mask to clear. 963 * 964 * Resets interrupts on the vCPU @cpu. 965 */ 966 void cpu_reset_interrupt(CPUState *cpu, int mask); 967 968 /** 969 * cpu_exit: 970 * @cpu: The CPU to exit. 971 * 972 * Requests the CPU @cpu to exit execution. 973 */ 974 void cpu_exit(CPUState *cpu); 975 976 /** 977 * cpu_resume: 978 * @cpu: The CPU to resume. 979 * 980 * Resumes CPU, i.e. puts CPU into runnable state. 981 */ 982 void cpu_resume(CPUState *cpu); 983 984 /** 985 * cpu_remove_sync: 986 * @cpu: The CPU to remove. 987 * 988 * Requests the CPU to be removed and waits till it is removed. 989 */ 990 void cpu_remove_sync(CPUState *cpu); 991 992 /** 993 * process_queued_cpu_work() - process all items on CPU work queue 994 * @cpu: The CPU which work queue to process. 995 */ 996 void process_queued_cpu_work(CPUState *cpu); 997 998 /** 999 * cpu_exec_start: 1000 * @cpu: The CPU for the current thread. 1001 * 1002 * Record that a CPU has started execution and can be interrupted with 1003 * cpu_exit. 1004 */ 1005 void cpu_exec_start(CPUState *cpu); 1006 1007 /** 1008 * cpu_exec_end: 1009 * @cpu: The CPU for the current thread. 1010 * 1011 * Record that a CPU has stopped execution and exclusive sections 1012 * can be executed without interrupting it. 1013 */ 1014 void cpu_exec_end(CPUState *cpu); 1015 1016 /** 1017 * start_exclusive: 1018 * 1019 * Wait for a concurrent exclusive section to end, and then start 1020 * a section of work that is run while other CPUs are not running 1021 * between cpu_exec_start and cpu_exec_end. CPUs that are running 1022 * cpu_exec are exited immediately. CPUs that call cpu_exec_start 1023 * during the exclusive section go to sleep until this CPU calls 1024 * end_exclusive. 1025 */ 1026 void start_exclusive(void); 1027 1028 /** 1029 * end_exclusive: 1030 * 1031 * Concludes an exclusive execution section started by start_exclusive. 1032 */ 1033 void end_exclusive(void); 1034 1035 /** 1036 * qemu_init_vcpu: 1037 * @cpu: The vCPU to initialize. 1038 * 1039 * Initializes a vCPU. 1040 */ 1041 void qemu_init_vcpu(CPUState *cpu); 1042 1043 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */ 1044 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */ 1045 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ 1046 1047 /** 1048 * cpu_single_step: 1049 * @cpu: CPU to the flags for. 1050 * @enabled: Flags to enable. 1051 * 1052 * Enables or disables single-stepping for @cpu. 1053 */ 1054 void cpu_single_step(CPUState *cpu, int enabled); 1055 1056 /* Breakpoint/watchpoint flags */ 1057 #define BP_MEM_READ 0x01 1058 #define BP_MEM_WRITE 0x02 1059 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE) 1060 #define BP_STOP_BEFORE_ACCESS 0x04 1061 /* 0x08 currently unused */ 1062 #define BP_GDB 0x10 1063 #define BP_CPU 0x20 1064 #define BP_ANY (BP_GDB | BP_CPU) 1065 #define BP_HIT_SHIFT 6 1066 #define BP_WATCHPOINT_HIT_READ (BP_MEM_READ << BP_HIT_SHIFT) 1067 #define BP_WATCHPOINT_HIT_WRITE (BP_MEM_WRITE << BP_HIT_SHIFT) 1068 #define BP_WATCHPOINT_HIT (BP_MEM_ACCESS << BP_HIT_SHIFT) 1069 1070 int cpu_breakpoint_insert(CPUState *cpu, vaddr pc, int flags, 1071 CPUBreakpoint **breakpoint); 1072 int cpu_breakpoint_remove(CPUState *cpu, vaddr pc, int flags); 1073 void cpu_breakpoint_remove_by_ref(CPUState *cpu, CPUBreakpoint *breakpoint); 1074 void cpu_breakpoint_remove_all(CPUState *cpu, int mask); 1075 1076 /* Return true if PC matches an installed breakpoint. */ 1077 static inline bool cpu_breakpoint_test(CPUState *cpu, vaddr pc, int mask) 1078 { 1079 CPUBreakpoint *bp; 1080 1081 if (unlikely(!QTAILQ_EMPTY(&cpu->breakpoints))) { 1082 QTAILQ_FOREACH(bp, &cpu->breakpoints, entry) { 1083 if (bp->pc == pc && (bp->flags & mask)) { 1084 return true; 1085 } 1086 } 1087 } 1088 return false; 1089 } 1090 1091 #if defined(CONFIG_USER_ONLY) 1092 static inline int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 1093 int flags, CPUWatchpoint **watchpoint) 1094 { 1095 return -ENOSYS; 1096 } 1097 1098 static inline int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, 1099 vaddr len, int flags) 1100 { 1101 return -ENOSYS; 1102 } 1103 1104 static inline void cpu_watchpoint_remove_by_ref(CPUState *cpu, 1105 CPUWatchpoint *wp) 1106 { 1107 } 1108 1109 static inline void cpu_watchpoint_remove_all(CPUState *cpu, int mask) 1110 { 1111 } 1112 #else 1113 int cpu_watchpoint_insert(CPUState *cpu, vaddr addr, vaddr len, 1114 int flags, CPUWatchpoint **watchpoint); 1115 int cpu_watchpoint_remove(CPUState *cpu, vaddr addr, 1116 vaddr len, int flags); 1117 void cpu_watchpoint_remove_by_ref(CPUState *cpu, CPUWatchpoint *watchpoint); 1118 void cpu_watchpoint_remove_all(CPUState *cpu, int mask); 1119 #endif 1120 1121 /** 1122 * cpu_plugin_mem_cbs_enabled() - are plugin memory callbacks enabled? 1123 * @cs: CPUState pointer 1124 * 1125 * The memory callbacks are installed if a plugin has instrumented an 1126 * instruction for memory. This can be useful to know if you want to 1127 * force a slow path for a series of memory accesses. 1128 */ 1129 static inline bool cpu_plugin_mem_cbs_enabled(const CPUState *cpu) 1130 { 1131 #ifdef CONFIG_PLUGIN 1132 return !!cpu->plugin_mem_cbs; 1133 #else 1134 return false; 1135 #endif 1136 } 1137 1138 /** 1139 * cpu_get_address_space: 1140 * @cpu: CPU to get address space from 1141 * @asidx: index identifying which address space to get 1142 * 1143 * Return the requested address space of this CPU. @asidx 1144 * specifies which address space to read. 1145 */ 1146 AddressSpace *cpu_get_address_space(CPUState *cpu, int asidx); 1147 1148 G_NORETURN void cpu_abort(CPUState *cpu, const char *fmt, ...) 1149 G_GNUC_PRINTF(2, 3); 1150 1151 /* $(top_srcdir)/cpu.c */ 1152 void cpu_class_init_props(DeviceClass *dc); 1153 void cpu_exec_initfn(CPUState *cpu); 1154 bool cpu_exec_realizefn(CPUState *cpu, Error **errp); 1155 void cpu_exec_unrealizefn(CPUState *cpu); 1156 void cpu_exec_reset_hold(CPUState *cpu); 1157 1158 const char *target_name(void); 1159 1160 #ifdef COMPILING_PER_TARGET 1161 1162 #ifndef CONFIG_USER_ONLY 1163 1164 extern const VMStateDescription vmstate_cpu_common; 1165 1166 #define VMSTATE_CPU() { \ 1167 .name = "parent_obj", \ 1168 .size = sizeof(CPUState), \ 1169 .vmsd = &vmstate_cpu_common, \ 1170 .flags = VMS_STRUCT, \ 1171 .offset = 0, \ 1172 } 1173 #endif /* !CONFIG_USER_ONLY */ 1174 1175 #endif /* COMPILING_PER_TARGET */ 1176 1177 #define UNASSIGNED_CPU_INDEX -1 1178 #define UNASSIGNED_CLUSTER_INDEX -1 1179 1180 #endif 1181