1 /* 2 * QEMU CXL Devices 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_DEVICE_H 11 #define CXL_DEVICE_H 12 13 #include "hw/cxl/cxl_component.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/register.h" 16 #include "hw/cxl/cxl_events.h" 17 18 /* 19 * The following is how a CXL device's Memory Device registers are laid out. 20 * The only requirement from the spec is that the capabilities array and the 21 * capability headers start at offset 0 and are contiguously packed. The headers 22 * themselves provide offsets to the register fields. For this emulation, the 23 * actual registers * will start at offset 0x80 (m == 0x80). No secondary 24 * mailbox is implemented which means that the offset of the start of the 25 * mailbox payload (n) is given by 26 * n = m + sizeof(mailbox registers) + sizeof(device registers). 27 * 28 * +---------------------------------+ 29 * | | 30 * | Memory Device Registers | 31 * | | 32 * n + PAYLOAD_SIZE_MAX ----------------------------------- 33 * ^ | | 34 * | | | 35 * | | | 36 * | | | 37 * | | | 38 * | | Mailbox Payload | 39 * | | | 40 * | | | 41 * | | | 42 * n ----------------------------------- 43 * ^ | Mailbox Registers | 44 * | | | 45 * | ----------------------------------- 46 * | | | 47 * | | Device Registers | 48 * | | | 49 * m ----------------------------------> 50 * ^ | Memory Device Capability Header| 51 * | ----------------------------------- 52 * | | Mailbox Capability Header | 53 * | ----------------------------------- 54 * | | Device Capability Header | 55 * | ----------------------------------- 56 * | | Device Cap Array Register | 57 * 0 +---------------------------------+ 58 * 59 */ 60 61 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ 62 #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ 63 #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ 64 #define CXL_CAPS_SIZE \ 65 (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */ 66 67 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */ 68 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ 69 70 #define CXL_MAILBOX_REGISTERS_OFFSET \ 71 (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH) 72 #define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */ 73 #define CXL_MAILBOX_PAYLOAD_SHIFT 11 74 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) 75 #define CXL_MAILBOX_REGISTERS_LENGTH \ 76 (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) 77 78 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \ 79 (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH) 80 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8 81 82 #define CXL_MMIO_SIZE \ 83 (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \ 84 CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH) 85 86 /* 8.2.8.4.5.1 Command Return Codes */ 87 typedef enum { 88 CXL_MBOX_SUCCESS = 0x0, 89 CXL_MBOX_BG_STARTED = 0x1, 90 CXL_MBOX_INVALID_INPUT = 0x2, 91 CXL_MBOX_UNSUPPORTED = 0x3, 92 CXL_MBOX_INTERNAL_ERROR = 0x4, 93 CXL_MBOX_RETRY_REQUIRED = 0x5, 94 CXL_MBOX_BUSY = 0x6, 95 CXL_MBOX_MEDIA_DISABLED = 0x7, 96 CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8, 97 CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9, 98 CXL_MBOX_FW_AUTH_FAILED = 0xa, 99 CXL_MBOX_FW_INVALID_SLOT = 0xb, 100 CXL_MBOX_FW_ROLLEDBACK = 0xc, 101 CXL_MBOX_FW_REST_REQD = 0xd, 102 CXL_MBOX_INVALID_HANDLE = 0xe, 103 CXL_MBOX_INVALID_PA = 0xf, 104 CXL_MBOX_INJECT_POISON_LIMIT = 0x10, 105 CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11, 106 CXL_MBOX_ABORTED = 0x12, 107 CXL_MBOX_INVALID_SECURITY_STATE = 0x13, 108 CXL_MBOX_INCORRECT_PASSPHRASE = 0x14, 109 CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15, 110 CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16, 111 CXL_MBOX_MAX = 0x17 112 } CXLRetCode; 113 114 typedef struct CXLCCI CXLCCI; 115 typedef struct cxl_device_state CXLDeviceState; 116 struct cxl_cmd; 117 typedef CXLRetCode (*opcode_handler)(const struct cxl_cmd *cmd, 118 uint8_t *payload_in, size_t len_in, 119 uint8_t *payload_out, size_t *len_out, 120 CXLCCI *cci); 121 struct cxl_cmd { 122 const char *name; 123 opcode_handler handler; 124 ssize_t in; 125 uint16_t effect; /* Reported in CEL */ 126 }; 127 128 typedef struct CXLEvent { 129 CXLEventRecordRaw data; 130 QSIMPLEQ_ENTRY(CXLEvent) node; 131 } CXLEvent; 132 133 typedef struct CXLEventLog { 134 uint16_t next_handle; 135 uint16_t overflow_err_count; 136 uint64_t first_overflow_timestamp; 137 uint64_t last_overflow_timestamp; 138 bool irq_enabled; 139 int irq_vec; 140 QemuMutex lock; 141 QSIMPLEQ_HEAD(, CXLEvent) events; 142 } CXLEventLog; 143 144 typedef struct CXLCCI { 145 const struct cxl_cmd (*cxl_cmd_set)[256]; 146 struct cel_log { 147 uint16_t opcode; 148 uint16_t effect; 149 } cel_log[1 << 16]; 150 size_t cel_size; 151 152 size_t payload_max; 153 /* Pointer to device hosting the CCI */ 154 DeviceState *d; 155 /* Pointer to the device hosting the protocol conversion */ 156 DeviceState *intf; 157 } CXLCCI; 158 159 typedef struct cxl_device_state { 160 MemoryRegion device_registers; 161 162 /* mmio for device capabilities array - 8.2.8.2 */ 163 struct { 164 MemoryRegion device; 165 union { 166 uint8_t dev_reg_state[CXL_DEVICE_STATUS_REGISTERS_LENGTH]; 167 uint16_t dev_reg_state16[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 2]; 168 uint32_t dev_reg_state32[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 4]; 169 uint64_t dev_reg_state64[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 8]; 170 }; 171 uint64_t event_status; 172 }; 173 MemoryRegion memory_device; 174 struct { 175 MemoryRegion caps; 176 union { 177 uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; 178 uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8]; 179 }; 180 }; 181 182 /* mmio for the mailbox registers 8.2.8.4 */ 183 struct { 184 MemoryRegion mailbox; 185 uint16_t payload_size; 186 union { 187 uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH]; 188 uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2]; 189 uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4]; 190 uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8]; 191 }; 192 }; 193 194 struct { 195 bool set; 196 uint64_t last_set; 197 uint64_t host_set; 198 } timestamp; 199 200 /* memory region size, HDM */ 201 uint64_t mem_size; 202 uint64_t pmem_size; 203 uint64_t vmem_size; 204 205 const struct cxl_cmd (*cxl_cmd_set)[256]; 206 CXLEventLog event_logs[CXL_EVENT_TYPE_MAX]; 207 } CXLDeviceState; 208 209 /* Initialize the register block for a device */ 210 void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev, 211 CXLCCI *cci); 212 213 typedef struct CXLType3Dev CXLType3Dev; 214 /* Set up default values for the register block */ 215 void cxl_device_register_init_t3(CXLType3Dev *ct3d); 216 217 /* 218 * CXL 2.0 - 8.2.8.1 including errata F4 219 * Documented as a 128 bit register, but 64 bit accesses and the second 220 * 64 bits are currently reserved. 221 */ 222 REG64(CXL_DEV_CAP_ARRAY, 0) 223 FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) 224 FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) 225 FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16) 226 227 void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type, 228 bool available); 229 230 /* 231 * Helper macro to initialize capability headers for CXL devices. 232 * 233 * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says: 234 * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that 235 * > is the maximum access size allowed for these registers. If this rule is not 236 * > followed, the behavior is undefined 237 * 238 * CXL 2.0 Errata F4 states further that the layouts in the specification are 239 * shown as greater than 128 bits, but implementations are expected to 240 * use any size of access up to 64 bits. 241 * 242 * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple 243 * access to be used for a register up to 64 bits. 244 */ 245 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \ 246 REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ 247 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ 248 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ 249 REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ 250 FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ 251 REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ 252 FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) 253 254 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET) 255 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ 256 CXL_DEVICE_CAP_REG_SIZE) 257 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE, 258 CXL_DEVICE_CAP_HDR1_OFFSET + 259 CXL_DEVICE_CAP_REG_SIZE * 2) 260 261 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max); 262 void cxl_init_cci(CXLCCI *cci, size_t payload_max); 263 void cxl_process_mailbox(CXLCCI *cci); 264 265 #define cxl_device_cap_init(dstate, reg, cap_id, ver) \ 266 do { \ 267 uint32_t *cap_hdrs = dstate->caps_reg_state32; \ 268 int which = R_CXL_DEV_##reg##_CAP_HDR0; \ 269 cap_hdrs[which] = \ 270 FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \ 271 CAP_ID, cap_id); \ 272 cap_hdrs[which] = FIELD_DP32( \ 273 cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, ver); \ 274 cap_hdrs[which + 1] = \ 275 FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \ 276 CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \ 277 cap_hdrs[which + 2] = \ 278 FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \ 279 CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \ 280 } while (0) 281 282 /* CXL 3.0 8.2.8.3.1 Event Status Register */ 283 REG64(CXL_DEV_EVENT_STATUS, 0) 284 FIELD(CXL_DEV_EVENT_STATUS, EVENT_STATUS, 0, 32) 285 286 /* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */ 287 REG32(CXL_DEV_MAILBOX_CAP, 0) 288 FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) 289 FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) 290 FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) 291 FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) 292 293 /* CXL 2.0 8.2.8.4.4 Mailbox Control Register */ 294 REG32(CXL_DEV_MAILBOX_CTRL, 4) 295 FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) 296 FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) 297 FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) 298 299 /* CXL 2.0 8.2.8.4.5 Command Register */ 300 REG64(CXL_DEV_MAILBOX_CMD, 8) 301 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8) 302 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8) 303 FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20) 304 305 /* CXL 2.0 8.2.8.4.6 Mailbox Status Register */ 306 REG64(CXL_DEV_MAILBOX_STS, 0x10) 307 FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) 308 FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) 309 FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) 310 311 /* CXL 2.0 8.2.8.4.7 Background Command Status Register */ 312 REG64(CXL_DEV_BG_CMD_STS, 0x18) 313 FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16) 314 FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7) 315 FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16) 316 FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16) 317 318 /* CXL 2.0 8.2.8.4.8 Command Payload Registers */ 319 REG32(CXL_DEV_CMD_PAYLOAD, 0x20) 320 321 REG64(CXL_MEM_DEV_STS, 0) 322 FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1) 323 FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1) 324 FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2) 325 FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) 326 FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) 327 328 typedef struct CXLError { 329 QTAILQ_ENTRY(CXLError) node; 330 int type; /* Error code as per FE definition */ 331 uint32_t header[CXL_RAS_ERR_HEADER_NUM]; 332 } CXLError; 333 334 typedef QTAILQ_HEAD(, CXLError) CXLErrorList; 335 336 typedef struct CXLPoison { 337 uint64_t start, length; 338 uint8_t type; 339 #define CXL_POISON_TYPE_EXTERNAL 0x1 340 #define CXL_POISON_TYPE_INTERNAL 0x2 341 #define CXL_POISON_TYPE_INJECTED 0x3 342 QLIST_ENTRY(CXLPoison) node; 343 } CXLPoison; 344 345 typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; 346 #define CXL_POISON_LIST_LIMIT 256 347 348 struct CXLType3Dev { 349 /* Private */ 350 PCIDevice parent_obj; 351 352 /* Properties */ 353 HostMemoryBackend *hostmem; /* deprecated */ 354 HostMemoryBackend *hostvmem; 355 HostMemoryBackend *hostpmem; 356 HostMemoryBackend *lsa; 357 uint64_t sn; 358 359 /* State */ 360 AddressSpace hostvmem_as; 361 AddressSpace hostpmem_as; 362 CXLComponentState cxl_cstate; 363 CXLDeviceState cxl_dstate; 364 CXLCCI cci; /* Primary PCI mailbox CCI */ 365 366 /* DOE */ 367 DOECap doe_cdat; 368 369 /* Error injection */ 370 CXLErrorList error_list; 371 372 /* Poison Injection - cache */ 373 CXLPoisonList poison_list; 374 unsigned int poison_list_cnt; 375 bool poison_list_overflowed; 376 uint64_t poison_list_overflow_ts; 377 }; 378 379 #define TYPE_CXL_TYPE3 "cxl-type3" 380 OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3) 381 382 struct CXLType3Class { 383 /* Private */ 384 PCIDeviceClass parent_class; 385 386 /* public */ 387 uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); 388 389 uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size, 390 uint64_t offset); 391 void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size, 392 uint64_t offset); 393 bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset, 394 uint8_t *data); 395 }; 396 397 MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, 398 unsigned size, MemTxAttrs attrs); 399 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, 400 unsigned size, MemTxAttrs attrs); 401 402 uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds); 403 404 void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num); 405 bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventLogType log_type, 406 CXLEventRecordRaw *event); 407 CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl, 408 uint8_t log_type, int max_recs, 409 size_t *len); 410 CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds, 411 CXLClearEventPayload *pl); 412 413 void cxl_event_irq_assert(CXLType3Dev *ct3d); 414 415 void cxl_set_poison_list_overflowed(CXLType3Dev *ct3d); 416 417 #endif 418